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clk: qcom: rcg2: Add DIV_ROUND_CLOSEST_ULL to roundoff RCG frequency

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The Alpha BW for Fabia PLL is 16 bit and the calculated hw rate has
additional KHz of frequency. Due to this additional frequency, the
source is wrongly selected. Truncate the additional KHz using the
DIV_ROUND_CLOSEST_ULL.

Change-Id: Ic9c523c87277c4813b676cf8a52a1207e8f1ecc2
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
This commit is contained in:
Shefali Jain 2018-09-11 10:26:35 +05:30 committed by Mike Tipton
parent 0fa01f415e
commit 42497813c1
1 changed files with 2 additions and 1 deletions
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3
drivers/clk/qcom/clk-rcg2.c
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@ -443,7 +443,8 @@ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
}
if (rcg->flags & FORCE_ENABLE_RCG) {
rcg->current_freq = clk_get_rate(hw->clk);
rcg->current_freq = DIV_ROUND_CLOSEST_ULL(
clk_get_rate(hw->clk), 1000) * 1000;
if (rcg->current_freq == cxo_f.freq)
curr_src_index = 0;
else {