Commit Graph

1127956 Commits

Author SHA1 Message Date
Manoj Vishwanathan
cdd2e05bb0 msm: pcie: Allow NULL as a valid return value for icc_get
As the ICC_GET stub function returns NULL and it's valid, PCIe controller
driver must continue without returning an error. This is the case when
CONFIG_INTERCONNECT is not set.

Change-Id: I0065caf71fd790feb0dbe6b459f203e58685be95
Signed-off-by: Manoj Vishwanathan <mvishwan@codeaurora.org>
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
2022-10-20 14:34:47 -07:00
Prudhvi Yarlagadda
dfb52a5eec pci: msm: Remove qcom_clk_dump calls from interrupt context
qcom_clk_dump function internally has sleeping calls like
mutext locks. We should not use this function in interrupt/
atomic context.

Change-Id: Ic10db12ec79158ea5a532a0de5a66a2c4a49a703
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
2022-10-20 14:34:38 -07:00
Hemant Kumar
7e927d7839 pci: msm: Add support to assert/de-assert Qactive signal
PCIe keeps Qactive signal asserted when link is active (L0).
It de-asserts it when link is in L1SS or D3Hot. In case of
L2, Qactive is not de-asserted, this prevents SNOC power
collapse. Fix this issue by asserting Qactive upon link
enable(L0) and de-assert it upon link disable(L2) using
PCIE20_PARF_CFG_BITS_3 register.

Change-Id: Iba8edb0360e6c6df9ffd1b65189fe8c92ca2c0b5
Signed-off-by: Hemant Kumar <quic_hemantk@quicinc.com>
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
2022-10-20 14:34:34 -07:00
Vivek Pernamitta
51dafa59bf msm: pci: Dump PCIe clock registers on link failure
Dump PCie clocks on failure to enter link into L0,
linkdown interrupt, and on receiving wake IRQ  from device.

Change-Id: I89430b25feeb165709ac44d3af65c73b8ab4eada
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com>
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
2022-10-20 14:34:29 -07:00
Jyothi Kumar Seerapu
0b800d87c4 pci: msm: Continue with probe even icc handles are missing on RUMI
This change is to proceed PCIe RC probe even icc handles are not present
in SDX75 RUMI validations. 
Currently icc changes are not mainlined and hence avoiding the issues
related to icc in PCIe code.

Change-Id: Ie66c62fae4e84cc68e08dfcd5a159dbdfaaebed1
Signed-off-by: Jyothi Kumar Seerapu <quic_jseerapu@quicinc.com>
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
2022-10-20 14:34:23 -07:00
Prudhvi Yarlagadda
b802f2a6b3 pci: msm: Add register dump for link status and control
Add debug support to print the PCI_L1SS_CTL1 and PCI_EXP_LNKSTA
registers during the aer interrupts.

Change-Id: I487c71bc691d70972fb7ff3c7d21b667a59a8838
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
2022-10-19 14:09:22 -07:00
Jyothi Kumar Seerapu
7a0bc21b15 pci:msm: Configure PCIe RC mode for RUMI
Add PCIe RC mode support to RUMI.

Change-Id: I211ac7aa4c546a2ce50d5df855112e3f90607700
Signed-off-by: Jyothi Kumar Seerapu <quic_jseerapu@quicinc.com>
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
2022-10-19 14:09:07 -07:00
Paras Sharma
d45e5fa01c msm: pcie: Dump PCIe registers for hang event
Dump limited set of pcie PARF, DBI and PHY registers for
hang event.

Change-Id: I6b8cd599da230968018587d10f326a9e6f10d4ac
Signed-off-by: Vivek Pernamitta <vpernami@codeaurora.org>
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Paras Sharma <quic_parass@quicinc.com>
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
2022-10-18 17:32:24 -07:00
qctecmdr
392f42735d Merge "soc: qcom: Add gpu info to revision 16 of socinfo structure" 2022-10-17 18:01:47 -07:00
qctecmdr
699e2e3f72 Merge "soc: qcom: memory_dump_v2: Initialize value of id" 2022-10-17 18:01:46 -07:00
qctecmdr
ab8ca56df5 Merge "soc: qcom: Fix uninitialized issue for memory dump driver" 2022-10-17 18:01:46 -07:00
qctecmdr
5d02b84396 Merge "msm: pcie: Adding 5th instance of PCIe Controller" 2022-10-17 18:01:45 -07:00
qctecmdr
ceee550247 Merge "msm_perf: fix warnings to enable msm_perf" 2022-10-17 12:13:10 -07:00
qctecmdr
3b97072e7f Merge "msm_perf: Handle out of bounds case" 2022-10-17 12:13:10 -07:00
qctecmdr
5c644f9800 Merge "msm_perf: check cpu_possible to improve stability" 2022-10-17 12:13:09 -07:00
qctecmdr
218f50a039 Merge "msm_perf: Update freq vote from UINT_MAX to FREQ_QOS_MAX_DEFAULT_VALUE" 2022-10-17 12:13:08 -07:00
qctecmdr
d2e12f2491 Merge "drivers: soc: msm_performance: Use pmu_lib to read pmu counters" 2022-10-17 12:13:08 -07:00
qctecmdr
78d49317e4 Merge "Revert "soc: qcom: Add snapshot of IPCC driver"" 2022-10-17 12:13:07 -07:00
qctecmdr
b350347ff8 Merge "net: qrtr: Add forwarding support based on net id" 2022-10-17 12:13:07 -07:00
qctecmdr
6f60b0843d Merge "defconfig: pineapple_tuivm: Add container configs" 2022-10-17 12:13:06 -07:00
Mrinmay Sarkar
e8134b4669 msm: pcie: Adding 5th instance of PCIe Controller
In some devices we have 5 PCIe controllers. This change
enables the 5th PCIe controller.

Change-Id: Ifb4c03eff307afe7f1cd6204eb5baa19a8188570
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
2022-10-16 23:50:07 -07:00
Vamsi Krishna Lanka
3684d8e225 soc: qcom: Add gpu info to revision 16 of socinfo structure
Update revision 16 partinfo to accommodate gpu info.

Change-Id: Iab5ab8b22db479e7f5609004db77b5ef4467867d
Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com>
2022-10-17 10:40:56 +05:30
qctecmdr
fac94f07d4 Merge "bus: mhi: devices: Fix number of arguments in API mhi_prepare_for_tranfer" 2022-10-15 21:06:26 -07:00
qctecmdr
4cab18afee Merge "bus: mhi: host: Enable and update IPC logging usage" 2022-10-15 21:06:25 -07:00
qctecmdr
6e308e1672 Merge "clk: qcom: clk-alpha-pll: Fix pll enable outout" 2022-10-14 13:36:41 -07:00
qctecmdr
5f267fb6b6 Merge "defconfig: pineapple-gki: Enable QCOM_SPSS and dependency" 2022-10-14 13:36:41 -07:00
qctecmdr
b87cea8461 Merge "slimbus: stream: add support to control port disconnect" 2022-10-14 13:36:41 -07:00
qctecmdr
e7af56b81b Merge "coresight: etm4x: Fetch device name in sysfs from device tree" 2022-10-14 13:36:40 -07:00
qctecmdr
748a67a29b Merge "soc: qcom: qcom_stats: Add API to get ddr freq information" 2022-10-14 13:36:39 -07:00
qctecmdr
fbff32ecf4 Merge "drivers: qcom: Add sys_pm_vx driver snapshot" 2022-10-14 13:36:38 -07:00
qctecmdr
915d25aab7 Merge "coresight: add support for device names" 2022-10-14 13:36:37 -07:00
qctecmdr
0a12785bd7 Merge "mem-buf: Exit mem_buf_lend_internal if the mem-buf not probed" 2022-10-14 13:36:37 -07:00
qctecmdr
6e89d3034b Merge "swiotlb: fix data abort on pineapple tuivm and oemvm" 2022-10-14 04:55:21 -07:00
qctecmdr
509c8ede30 Merge "bus: mhi: host: Move MHI_MAX_MTU to external header file" 2022-10-14 04:55:21 -07:00
qctecmdr
8680c038ee Merge "net: qrtr: ns: Add pr_fmt to ns" 2022-10-14 04:55:20 -07:00
qctecmdr
a097b57e48 Merge "build.config: kalama: Change Boot header version to 4" 2022-10-14 04:55:18 -07:00
Nitesh Gupta
526bca5904 msm: pcie: Add tcsr configuration
Add support for reading tcsr configuration from device tree and
configuring tcsr register dynamically.
This change for supporting sa8195p PCIe1. The default PCIe linkage
status of PCIe1 and 2 on sa8195p is:
PCIe1: not enabled
PCIe2: x4 lane
When config the register TCSR_PCIEPHY_LINK_CONFIG to 0(default 1),
the linkage status becomes:
PCIe1: x2 lane
PCIe2: x2 lane
This change add the ability to read tcsr value from device tree.

Change-Id: Iac53f61a147a839772c8411993f3be233b142b56
Signed-off-by: Xiang Li <lixiang@codeaurora.org>
Signed-off-by: Nitesh Gupta <nitegupt@codeaurora.org>
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
2022-10-14 00:33:44 -07:00
Chris Lew
188c64d260 net: qrtr: Add forwarding support based on net id
Add support for QRTR to forward messages between network clusters. The
network subnet id's are attached to the QRTR subnodes in the MHI and
RPMSG/GLINK nodes.

The current forwarding decisions are done based on the net ids and are
wrapped in a single function for easier maintenance of forwarding
decisions later on. The function will return true once it determines
a subnet has no connection to another subnet.

The NEW_SERVER, DEL_SERVER, and DEL_CLIENT control messages should be
forwarded while the DATA and RESUME_TX commands should be passed along
to their destination node.

The nameservice is expected to send NEW_SERVER commands for it's entire
database instead of just the local service database with these changes.
This is to make sure new nodes get service notifications that came
earlier and were meant to be forwarded to the new node.

This change squashes the following commits from msm-4.14:
  commit e5f6a6769ceb ("net: qrtr: Add forwarding support based on net id")
  commit 4516ab18718d ("net: qrtr: avoid deadlock in case of recursive
                        lock for node list")
  commit dc2d47cd12d3 ("net: qrtr: Only update pkts with broadcast node
                        ID")
  commit 4277aebeff91 ("net: qrtr: Free skb if qrtr_node_lookup fails
                        during qrtr_fwd_pkt")

In addition fix minor format issues and update copyright.

Change-Id: Iaf01dd212b07dfbb13ec087ea0aae980cda7c2fd
Signed-off-by: Chris Lew <quic_clew@quicinc.com>
2022-10-13 15:05:29 -07:00
Kishore Sri venkata Ganesh Bolisetty
62a38c3321 msm_perf: fix warnings to enable msm_perf
Handle error checks in reading attributes.

Change-Id: I12b693e469b8a8de21a2bef36c92a012e5a2c034
Signed-off-by: Kishore Sri venkata Ganesh Bolisetty <quic_bsrivenk@quicinc.com>
2022-10-13 14:20:34 -07:00
Badri Sampath
d6a47b123a msm_perf: Handle out of bounds case
KASAN seems to be flagging that bool
would only be 1 byte while %du would
want to write 4 bytes leading to out
of bounds.

Change-Id: I0e43b1103b882bbd61b5a0bef231efcc3d7d1e1b
Signed-off-by: Badri Sampath <quic_badris@quicinc.com>
2022-10-13 14:20:19 -07:00
Gaurav Singh
19cb3f2ce4 msm_perf: check cpu_possible to improve stability
check cpu_possible to improve stability

Change-Id: I9ce3b5a5a6b1e846f44ffb9e255cc5b6b701b377
Signed-off-by: Gaurav Singh <quic_sgaurav@quicinc.com>
2022-10-13 14:19:36 -07:00
Varun Garg
4a2cd1d8e8 msm_perf: Update freq vote from UINT_MAX to FREQ_QOS_MAX_DEFAULT_VALUE
As QoS driver takes freq value in s32 format, updated the max
vote value to FREQ_QOS_MAX_DEFAULT_VALUE, instead of UINT_MAX.

Change-Id: I5152ac65a9513ce7cafe9f72bbffc499571a0768
Signed-off-by: Varun Garg <quic_gargv@quicinc.com>
2022-10-13 14:19:10 -07:00
Rishabh Bhatnagar
8c8deb070a drivers: soc: msm_performance: Use pmu_lib to read pmu counters
Go through pmu library to read/request perf counters for
msm_performance usecase.

Change-Id: Idfa83c6c7f18b8a85ff13992e3ff5cd65df50c10
Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
2022-10-13 14:18:51 -07:00
Anvesh Salveru
ce345ff94d slimbus: stream: add support to control port disconnect
There is a requirement where slimbus slave don't expect ports
to be disconnected during stream unprepare for sample rates
other than 44.1/88.2k, which is causing mute issues.

Added new slim_stream_unprepare_disconnect_port API to support
disconnect port request from clients without freeing port memory
allocated during stream prepare.

Change-Id: Idb00a1fdf15d864cb6ee82f67c0db4777434b296
Signed-off-by: Anvesh Salveru <quic_asalveru@quicinc.com>
2022-10-12 20:47:39 -07:00
Huang Yiwei
d993f624e7 Revert "soc: qcom: Add snapshot of IPCC driver"
This reverts commit 5c4cca6534.
Since upstream IPCC driver is being used now, remove downstream
driver code.

Change-Id: Icb4bc6bb1bf5ce25b11f0e5b8d6d01d1d744e13d
Signed-off-by: Huang Yiwei <quic_hyiwei@quicinc.com>
2022-10-13 10:33:19 +08:00
Dennis Cagle
29fb6ea425 defconfig: pineapple_tuivm: Add container configs
Add configurations necessary for container framework

Change-Id: I5407bab5cf8e45bd6af8412576533b905a5f4b83
Signed-off-by: Dennis Cagle <quic_dcagle@quicinc.com>
2022-10-12 16:56:10 -07:00
Chris Goldsworthy
f484c0e648 mem-buf: Exit mem_buf_lend_internal if the mem-buf not probed
Exit with an error from mem_buf_lend_internal() if the driver hasn't
probed.

Change-Id: Ide42166c2f850197f989a228f9139d401411a914
Signed-off-by: Chris Goldsworthy <quic_cgoldswo@quicinc.com>
2022-10-11 20:31:32 -07:00
Mao Jinlong
c578bc78ac soc: qcom: memory_dump_v2: Initialize value of id
Id need to be initialized in function mem_dump_alloc.

Change-Id: Iddc3b4b09ea0a3b3554e5ab16e678240dcefe79e
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
2022-10-11 20:02:48 -07:00
Tao Zhang
f3f0fca72a soc: qcom: Fix uninitialized issue for memory dump driver
Initialize the variable "initialized" to avoid it being used
uninitialized.

Change-Id: I9c7cbedfb0cc0f7519fbc7305cb1c4f2072f61b0
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
2022-10-11 19:50:55 -07:00
Chris Lew
453bbe3dbd rpmsg: glink: Add name functionality back
IPC logging and IRQ naming depend on the name variable in the glink
data structure. Add device tree name reading code that was removed
by upstream.

Change-Id: Id1c521d94b8a3c9557273d8f8b072e7e87a1b759
Signed-off-by: Chris Lew <quic_clew@quicinc.com>
2022-10-11 17:55:32 -07:00