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pci: msm: Add support to assert/de-assert Qactive signal

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PCIe keeps Qactive signal asserted when link is active (L0).
It de-asserts it when link is in L1SS or D3Hot. In case of
L2, Qactive is not de-asserted, this prevents SNOC power
collapse. Fix this issue by asserting Qactive upon link
enable(L0) and de-assert it upon link disable(L2) using
PCIE20_PARF_CFG_BITS_3 register.

Change-Id: Iba8edb0360e6c6df9ffd1b65189fe8c92ca2c0b5
Signed-off-by: Hemant Kumar <quic_hemantk@quicinc.com>
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
This commit is contained in:
Hemant Kumar 2022-08-25 23:22:35 -07:00 committed by Gerrit - the friendly Code Review server
parent 51dafa59bf
commit 7e927d7839
1 changed files with 7 additions and 0 deletions
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7
drivers/pci/controller/pci-msm.c
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@ -4772,6 +4772,9 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev)
goto link_fail;
}
/* Disable override for fal10_veto logic to de-assert Qactive signal */
msm_pcie_write_mask(dev->parf + PCIE20_PARF_CFG_BITS_3, BIT(0), 0);
/**
* configure LANE_SKEW_OFF BIT-5 and PARF_CFG_BITS_3 BIT-8 to support
* dynamic link width upscaling.
@ -4898,6 +4901,10 @@ static void msm_pcie_disable(struct msm_pcie_dev_t *dev)
msm_pcie_write_mask(dev->parf + PCIE20_PARF_PHY_CTRL, 0,
BIT(0));
/* Enable override for fal10_veto logic to assert Qactive signal.*/
msm_pcie_write_mask(dev->parf + PCIE20_PARF_CFG_BITS_3, 0, BIT(0));
msm_pcie_clk_deinit(dev);
msm_pcie_vreg_deinit(dev);
msm_pcie_pipe_clk_deinit(dev);