msm: pcie: Adding 5th instance of PCIe Controller

In some devices we have 5 PCIe controllers. This change
enables the 5th PCIe controller.

Change-Id: Ifb4c03eff307afe7f1cd6204eb5baa19a8188570
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
This commit is contained in:
Mrinmay Sarkar 2022-05-12 12:00:30 +05:30 committed by Gerrit - the friendly Code Review server
parent 526bca5904
commit e8134b4669

View File

@ -201,7 +201,7 @@
#define MAX_PROP_SIZE (32)
#define MAX_RC_NAME_LEN (15)
#define MSM_PCIE_MAX_VREG (6)
#define MAX_RC_NUM (3)
#define MAX_RC_NUM (5)
#define MAX_DEVICE_NUM (20)
#define PCIE_TLP_RD_SIZE (0x5)
#define PCIE_LOG_PAGES (50)
@ -1108,6 +1108,20 @@ msm_pcie_reset_info[MAX_RC_NUM][MSM_PCIE_MAX_RESET] = {
{NULL, "pcie_phy_com_reset", false},
{NULL, "pcie_phy_nocsr_com_phy_reset", false},
{NULL, "pcie_2_phy_reset", false}
},
{
{NULL, "pcie_3_core_reset", false},
{NULL, "pcie_phy_reset", false},
{NULL, "pcie_phy_com_reset", false},
{NULL, "pcie_phy_nocsr_com_phy_reset", false},
{NULL, "pcie_3_phy_reset", false}
},
{
{NULL, "pcie_4_core_reset", false},
{NULL, "pcie_phy_reset", false},
{NULL, "pcie_phy_com_reset", false},
{NULL, "pcie_phy_nocsr_com_phy_reset", false},
{NULL, "pcie_4_phy_reset", false}
}
};
@ -1122,6 +1136,12 @@ msm_pcie_pipe_reset_info[MAX_RC_NUM][MSM_PCIE_MAX_PIPE_RESET] = {
},
{
{NULL, "pcie_2_phy_pipe_reset", false}
},
{
{NULL, "pcie_3_phy_pipe_reset", false}
},
{
{NULL, "pcie_4_phy_pipe_reset", false}
}
};