When setting plane degamma TF via AMD driver-specific color properties,
the driver uses PRE_DEGAM color block (ROM). However, this block cannot
be used with subsampled formats as it affects the linearity of color
space in which HW scaler operates. For subsampled format, use the AMD
color module to map plane degamma predefined curve to LUT and use GAMCOR
block instead (RAM).
This is based on Harry's implementation for Fixed Matrix Colorop.
Link: https://lore.kernel.org/dri-devel/20260330153451.99472-1-harry.wentland@amd.com/
Co-developed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Tested-by: Matthew Schwartz <matthew.schwartz@linux.dev>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The standalone_mode ip_discovery sysfs hierarchy is tied to the PCI
device lifetime and tracked in early_ip_discovery_list. It is torn down
only by amdgpu_discovery_sysfs_early_fini() on driver unbind, which is
why amdgpu_discovery_fini() already guards its teardown with
!standalone_mode.
Commit 7de02fe953 ("drm/amdgpu: clean up discovery and preempt sysfs
entries on shutdown") added an unconditional amdgpu_discovery_sysfs_fini()
call in amdgpu_device_sys_interface_fini(), which runs during
amdgpu_device_fini_hw() on every unbind/reload. On reload this freed the
PCI-device-owned ip_top via kobject_put()->ip_disc_release()->kfree(),
leaving a dangling pointer in early_ip_discovery_list. The subsequent
amdgpu_discovery_sysfs_early_fini() then dereferenced and put the freed
object, causing a use-after-free and double-free, and prematurely
destroyed the sysfs that was meant to persist across reloads.
Make amdgpu_discovery_sysfs_fini() skip standalone_mode objects so the
invariant is centralized at the teardown site and the new call site
cannot free the PCI-device-owned ip_top. Teardown of standalone sysfs
remains the sole responsibility of amdgpu_discovery_sysfs_early_fini().
Fixes: 7de02fe953 ("drm/amdgpu: clean up discovery and preempt sysfs entries on shutdown")
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
MQD used outside of dpm_lock is unsafe because the queue could be
destroyed during the window of dqm_unlock, moving into dqm_lock
range is the best practice.
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Replace dcn42 GPIO translation switch statements with the
generic table-based translation helpers.
This simplifies the GPIO mapping logic and reduces duplicated
translation code.
No functional changes intended.
Signed-off-by: Guilherme Ivo Bozi <guilherme.bozi@usp.br>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Acked-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Replace dcn401 GPIO translation switch statements with the
generic table-based translation helpers.
This simplifies the GPIO mapping logic and reduces duplicated
translation code.
No functional changes intended.
Signed-off-by: Guilherme Ivo Bozi <guilherme.bozi@usp.br>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Acked-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Replace dcn32 GPIO translation switch statements with the
generic table-based translation helpers.
This simplifies the GPIO mapping logic and reduces duplicated
translation code.
No functional changes intended.
Signed-off-by: Guilherme Ivo Bozi <guilherme.bozi@usp.br>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Acked-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Replace dcn315 GPIO translation switch statements with the
generic table-based translation helpers.
This simplifies the GPIO mapping logic and reduces duplicated
translation code.
No functional changes intended.
Signed-off-by: Guilherme Ivo Bozi <guilherme.bozi@usp.br>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Acked-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Replace dcn30 GPIO translation switch statements with the
generic table-based translation helpers.
This simplifies the GPIO mapping logic and reduces duplicated
translation code.
No functional changes intended.
Signed-off-by: Guilherme Ivo Bozi <guilherme.bozi@usp.br>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Acked-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Replace dcn21 GPIO translation switch statements with the
generic table-based translation helpers.
This simplifies the GPIO mapping logic and reduces duplicated
translation code.
No functional changes intended.
Signed-off-by: Guilherme Ivo Bozi <guilherme.bozi@usp.br>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Acked-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Replace dcn20 GPIO translation switch statements with the
generic table-based translation helpers.
This simplifies the GPIO mapping logic and reduces duplicated
translation code.
No functional changes intended.
Signed-off-by: Guilherme Ivo Bozi <guilherme.bozi@usp.br>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Acked-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Replace dcn10 GPIO translation switch statements with the
generic table-based translation helpers.
This simplifies the GPIO mapping logic and reduces duplicated
translation code.
No functional changes intended.
Signed-off-by: Guilherme Ivo Bozi <guilherme.bozi@usp.br>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Acked-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add generic helpers and lookup table types for GPIO hardware
translation.
The new helpers provide reusable conversions between GPIO IDs,
register offsets and DDC lines, allowing ASIC-specific drivers
to replace large switch statements with static lookup tables.
No functional changes intended.
Signed-off-by: Guilherme Ivo Bozi <guilherme.bozi@usp.br>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Acked-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/sspl/spl_debug.h checks for
CONFIG_HAVE_KGDB or CONFIG_KGDB to determine whether to call
kgdb_breakpoint(). CONFIG_HAVE_KGDB has never existed in the kernel.
Remove the check for it and retain only the correct check for
CONFIG_KGDB.
Discovered while searching for CONFIG_* symbols referenced in code but
not defined in any Kconfig file.
Signed-off-by: Ethan Nelson-Moore <enelsonmoore@gmail.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Acked-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The function has two arrays on the stack to hold temporary dsc_optc_config
and dsc_config objects. The combination blows through common stack frame
warning limits in combination with the other local variables:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:4070:22: error: stack frame size (1352) exceeds limit
(1280) in 'commit_planes_do_stream_update_sequence' [-Werror,-Wframe-larger-than]
Since neither array is initialized or used outside of the
add_link_update_dsc_config_sequence() function, there is no actual
need to keep each element around.
Replace the arrays with a single instance each to reduce the stack usage
to less than half.
Fixes: 9f49d3cd7e ("drm/amd/display: Implement block sequencing infrastructure for modular hardware operations.")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Acked-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHAT]
Remove the redundant IP_VERSION(4, 2, 0) case from
dm_get_default_ips_mode() since it only reassigns the same
DMUB_IPS_ENABLE value already set at initialization.
Also remove the corresponding KUnit test.
Reviewed-by: Chenyu Chen <chen-yu.chen@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DC Automatic Code Cutoff
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Acked-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
DML has been updated to use per-DPM derates when provided but per-DPM de-rates have not been finalized.
Need to validate to see what values should be stored in the bounding box.
[How]
Add debug options to set custom derates per DPM (starting at DPM0) and their values
Each entry in the custom derate expects the derates to be stored in the following format:
bits 0-7: dram_derate_percent_pixel
bits 8-15: fclk_derate_percent
bits 16-23: dcfclk_derate_percent
bits 24-31 are unused.
e.g. Using the value 0x414020 will set the following derates for DPM0
DPM0: 0x20, 0x40, 0x41 for dram, fclk, and dcfclk respectively
Note that global derate value will be used if the per-DPM derate is 0.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
When driver allows idle optimization, no HW state should be modified further
by DC. Refactor the skip PG logic in pg_cntl in DCN42.
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
Enable Driver PG for HUBP and DPP in DCN42.
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
DSCCLK is not required when power gating or ungating the DSC block.
Remove the unnecessary DSCCLK enable sequence.
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
There is an updated workaround for PG Repeater issue in DCN42. This PR is
addressing the dynamic power gating use cases (Driver PG) to align with
the new sequence.
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
- Previously linear copy commands for LSDMA assumed no DCC
- Update so that there is explicit assignment for DCC related fields
- Caller can 0 out the fields if DCC is not used
- For linear copy command don't subtract 1 from the count - this will
be done at a lower layer
Reviewed-by: Rafal Ostrowski <rafal.ostrowski@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Dynamic expansion is not needed when outputting 12bpc test patterns.
[How]
Add a debug flag to control disabling dynamic expansion in the case
of 12bpc test patterns.
Reviewed-by: Michael Strauss <michael.strauss@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Opening the CRC data file during active rendering can fail with -EINVAL.
Closing the CRC data file with ctrl+C (which will send SIGINT to the kernel
and if the wait thread in sleep, kernel will send the -ERESTARTSYS to the
wait_for_completion_interruptible_timeout)
resulting in intermittently getting -ERESTARTSYS. which will just do the
clean up without releasing the vblank reference causing -EINVAL while opening
the crc data file in the next iteration
[How]
Ignoring the ERESTARTSYS as this is a return value for the
wait_for_completion_interruptible_timeout()
Reviewed-by: Chen-Yu Chen <chen-yu.chen@amd.com>
Signed-off-by: Chandana G B <Chandana.GB@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Currently only a singular de-rate is used for all DPM levels.
The intent was to limit the bandwidth utilization at high DPMs
so the display requirements are not competing with other engines for bandwidth.
At lower DPMs, the de-rates could be more lenient so more bandwidth can be
utilized without the need to increase the DPM level and result in potential power savings.
i.e. DPM0 could be achieved on certain display configs instead of DPM1
if de-rates were a couple percentage points higher
The system average de-rates can be adjusted as needed as only urgent de-rates are defined for the SOC.
[How]
Update QOS parameters to have a table of derates with a per-DPM granularity
If the per-DPM value is provided, that will value be used.
Otherwise use the global value if there is no DPM specific value.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
In __set_dm_plane_colorop_shaper and __set_dm_plane_colorop_blend the
single colorop_state variable was reused sequentially: first to capture
the TF state, then (after mutating the colorop pointer) to capture the
LUT state.
Split into separate tf_state / lut_state pointers and introduce a
dedicated lut_colorop local. Resolve both pointers upfront before any
computation begins. This separates the concern of "find the states" from
"use the states" and makes the code easier to follow.
No functional change.
Assisted-by: Copilot:claude-opus-4.8
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DRM core builds the curve_1d_type enum property with only the supported
TF values, so any curve_1d_type that reaches atomic_commit is already
guaranteed to be in the supported set. The per-colorop type field is
immutable — it cannot change between the loop that finds colorop_state
and the if block that uses it, so re-checking colorop->type there is
dead code.
Remove the redundant checks:
- colorop->type == DRM_COLOROP_1D_CURVE in the shaper TF if block
- colorop->type == DRM_COLOROP_1D_LUT in the shaper LUT if block
- colorop->type == DRM_COLOROP_1D_CURVE in the blend TF if block
- colorop->type == DRM_COLOROP_1D_LUT in the blend LUT if block
- BIT(colorop_state->curve_1d_type) & supported_blnd_tfs in the blend
TF if block (already guaranteed by the loop filter)
- BIT(colorop_state->curve_1d_type) & supported_blnd_tfs in the blend
LUT if block (nonsensical: a 1D_LUT colorop has no curve_1d_type)
No functional change.
Assisted-by: Copilot:claude-opus-4.8
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
Some resources that exist in the DCN block are not needed and shouldn't
be used.
[how]
Remove defines from register lists.
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
snprintf() and vsnprintf() return the number of bytes that would have
been written if the buffer were large enough, not the actual bytes
written. If truncation occurs, the accumulated length can exceed the
buffer size, causing kfifo_in() to read past the fifo_in[] stack buffer.
Switch to scnprintf() and vscnprintf() which return the actual number
of bytes written, excluding the null terminator. This prevents the
potential buffer over-read when calculating the offset for subsequent
writes.
Signed-off-by: William Palacek <William.Palacek@amd.com>
Reviewed-by: Alysa Liu <Alysa.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
DCN42 reuses dccg42_init, which causes problems due to undefined masks.
[how]
- Read res_pool to determine the quantities of the respective resources
- Remove the physymclk root_clock_optimization check, as it seems like
it shouldn't do anything (defaults to disabled already).
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
The register lists used on DCN42 variants are different. Some reused
codepaths are trying to access registers not used.
[how]
Add DISPCLK_FREQ_CHANGECNTL, HUBPREQ_DEBUG, and HDMISTREAMCLK_CNTL to
the register lists.
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
'skip_frl_pretraining' was introduced and enabled along w/ HDMI 2.1
initial upstream, but is causing HDMI validation link training to be s
kipped on short hotplugs and compliance issues.
Remove this behaviour to force link training on all hotplugs for all
ASICs.
Reviewed-by: Relja (Reggie) Vojvodic <relja.vojvodic@amd.com>
Reviewed-by: Sun peng (Leo) Li <sunpeng.li@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
12bpc color ramp pattern was never implemented.
[HOW]
Add correct DPG_RAMP_CONTROL programming to match DP color ramp spec.
Reviewed-by: George Shen <george.shen@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Reduces file fragmentation in the power module by consolidating
power_helpers.c . The helper file contained minimal
functionality (single utility function and shared includes) that
didn't warrant a separate compilation unit, leading to increased
build complexity and maintenance overhead.
[How]
Consolidated power_helpers.c content into the internal module
implementation. Moved macro outside
platform-specific conditional block for wider availability.
Reviewed-by: Josip Pavic <josip.pavic@amd.com>
Signed-off-by: Lohita Mudimela <lohita.mudimela@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
It is required by Security Guidance for All Software Components.
[How]
Change variable type to unsigned in dc\dml\dcn314\display_mode_vba_31.c
and dc\dml\dcn31\display_mode_vba_314.c.
Explicit cast to unsigned in dc\link\protocols\link_hdmi_frl.c.
Move warning from UNSOLVED set to SOLVED set.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Enable PSR and Panel Replay on a DCN4 variant for display power
savings. On links without native I2C (no DDC pin), the AUX channel
must use aux_hw_inst to avoid NULL pointer access during PSR and
Replay setup.
[How]
Enable PSR and Replay in the DCN4 variant panel config defaults.
Add no_ddc_pin check in dp_setup_panel_replay(),
edp_setup_freesync_replay(), and fsft_send_msg_to_fw() to use
link->aux_hw_inst when dp_connector_no_native_i2c and no_ddc_pin
are set.
Reviewed-by: Matthew Stewart <matthew.stewart2@amd.com>
Signed-off-by: Gabe Teeger <gabe.teeger@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
DCN42B was not using its own max_ip_caps table. Need to create a
separate soc_and_ip_translator in order to not reuse the DCN42 one.
[how]
Separate DCN42B into its own soc_and_ip_translator.c file to handle this.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Split amdgpu_gfx_mes_reset_queue_start() into reset+unmap now and queue
reinit later, and do the remap only after amdgpu_mes_resume(). Avoids
re-adding legacy queues while MES gangs are still suspended.
Suggested-by: Shaoyun Liu <shaoyun.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Call the new userq reset helper, and dispatch KQs first by ring_id
before falling back to the user-queue lookup.
v2: squash in fixes
Co-developed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
If we get an interrupt for a bad user queue (bad opcode, etc.), add
a helper to handle the reset for user queues.
v2: squash in fixes
v3:
- schedule the reset via amdgpu_userq_start_hang_detect_work() instead
of open-coding mod_delayed_work()
- drop the per-queue guilty flag; always reset the queue the hang
detect work belongs to, matching the non-compute reset path
Co-developed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Pass flush_mes_queue=true in reset_queue_mes() to match the GFX
post-reset drop semantics.
Suggested-by: Shaoyun Liu <shaoyun.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Set remove_queue_after_reset=1 (MES >= 0x5a) so MES drops its internal
state instead of re-unmapping an already MMIO-reset queue, which can
timeout into a GPU reset.
Suggested-by: Shaoyun Liu <shaoyun.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
To avoid wraparound if the value is 0.
Signed-off-by: Xiaogang Chen <xiaogang.chen@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Fix a security vulnerability where malicious VCE command streams
with oversized dimensions (e.g. 65536×65536) cause 32-bit integer
overflow, wrapping the calculated buffer size to 0. This bypasses
validation and allows GPU firmware to perform out-of-bound memory
access.
The fix uses 64-bit arithmetic to detect overflow and rejects
invalid dimensions before they reach the hardware.
V2: remove redundant check
V3: modify max height value
V4: remove size64
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reuse the parameter length returned by
vcn_v4_0_enc_find_ib_param() instead of rereading it from
the IB.
This avoids a potential TOCTOU issue if the IB contents
change between reads.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
When width or height is less than 16, width_in_mb or height_in_mb
becomes 0, leading to fs_in_mb being 0. This causes a division by
zero when calculating num_dpb_buffer in H264 and H264 Perf decode
paths.
Add validation to reject frames with width < 16 or height < 16
before performing any calculations that depend on these values.
V2: Format change - move up all vaiable definitions.
V3: Use warn_once to avoid spam.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
These adapters typically are only supported by Barco on the
Windows platform. However, with these changes in the linux
driver, multiple monitor support should work correctly.
Signed-off-by: Matthew Jacob <mjacob@feralsw.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
