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drm/amdgpu/gfx11: handle error interrupts for userqs

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Call the new userq reset helper, and dispatch KQs first by ring_id
before falling back to the user-queue lookup.

v2: squash in fixes

Co-developed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jesse Zhang 2026-06-09 10:00:48 +08:00 committed by Alex Deucher
parent 395e142b43
commit 23d9db57f3
1 changed files with 23 additions and 9 deletions
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32
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
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@ -6654,22 +6654,29 @@ static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev,
struct amdgpu_iv_entry *entry)
{
u8 me_id, pipe_id, queue_id;
struct amdgpu_ring *ring;
int i;
me_id = (entry->ring_id & 0x0c) >> 2;
pipe_id = (entry->ring_id & 0x03) >> 0;
queue_id = (entry->ring_id & 0x70) >> 4;
u32 doorbell_offset = entry->src_data[0] & AMDGPU_CTXID0_DOORBELL_ID_MASK;
/*
* Try KQ first by ring_id (HW slot is authoritative). The
* KMD compute_hqd_mask contract guarantees KCQ and user queues
* never share a HW slot.
*/
if (!adev->gfx.disable_kq) {
u8 me_id = (entry->ring_id & 0x0c) >> 2;
u8 pipe_id = (entry->ring_id & 0x03) >> 0;
u8 queue_id = (entry->ring_id & 0x70) >> 4;
struct amdgpu_ring *ring;
int i;
switch (me_id) {
case 0:
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
ring = &adev->gfx.gfx_ring[i];
if (ring->me == me_id && ring->pipe == pipe_id &&
ring->queue == queue_id)
ring->queue == queue_id) {
drm_sched_fault(&ring->sched);
return;
}
}
break;
case 1:
@ -6677,8 +6684,10 @@ static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev,
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
ring = &adev->gfx.compute_ring[i];
if (ring->me == me_id && ring->pipe == pipe_id &&
ring->queue == queue_id)
ring->queue == queue_id) {
drm_sched_fault(&ring->sched);
return;
}
}
break;
default:
@ -6686,6 +6695,11 @@ static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev,
break;
}
}
/* No KQ matched: HW slot is a MES-scheduled user queue. */
if (adev->enable_mes && doorbell_offset)
amdgpu_userq_process_reset_irq(adev, entry->pasid,
doorbell_offset);
}
static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev,