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drm/amd/display: Rewrite dccg42_init

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[why]

DCN42 reuses dccg42_init, which causes problems due to undefined masks.

[how]

- Read res_pool to determine the quantities of the respective resources
- Remove the physymclk root_clock_optimization check, as it seems like
  it shouldn't do anything (defaults to disabled already).

Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Matthew Stewart 2026-06-08 11:22:02 -04:00 committed by Alex Deucher
parent 64142f9d51
commit 46fda8bda6
1 changed files with 9 additions and 20 deletions
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29
drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c
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@ -269,37 +269,26 @@ void dccg42_trigger_dio_fifo_resync(struct dccg *dccg)
static void dccg42_init(struct dccg *dccg)
{
int otg_inst;
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
unsigned int i;
struct resource_pool *res_pool = dccg->ctx->dc->res_pool;
/* Set HPO stream encoder to use refclk to avoid case where PHY is
* disabled and SYMCLK32 for HPO SE is sourced from PHYD32CLK which
* will cause DCN to hang.
*/
for (otg_inst = 0; otg_inst < 4; otg_inst++)
dccg35_disable_symclk32_se(dccg, otg_inst);
for (i = 0; i < res_pool->hpo_dp_stream_enc_count; i++)
dccg35_disable_symclk32_se(dccg, i);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) {
dccg401_disable_symclk32_le(dccg, 0);
dccg401_disable_symclk32_le(dccg, 1);
dccg401_disable_symclk32_le(dccg, 2);
dccg401_disable_symclk32_le(dccg, 3);
for (i = 0; i < res_pool->hpo_dp_link_enc_count; i++)
dccg401_disable_symclk32_le(dccg, i);
}
if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {
dccg401_disable_dpstreamclk(dccg, 0);
dccg401_disable_dpstreamclk(dccg, 1);
dccg401_disable_dpstreamclk(dccg, 2);
dccg401_disable_dpstreamclk(dccg, 3);
}
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) {
REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2,
PHYASYMCLK_ROOT_GATE_DISABLE, 1,
PHYBSYMCLK_ROOT_GATE_DISABLE, 1,
PHYCSYMCLK_ROOT_GATE_DISABLE, 1,
PHYDSYMCLK_ROOT_GATE_DISABLE, 1,
PHYESYMCLK_ROOT_GATE_DISABLE, 1);
for (i = 0; i < res_pool->hpo_dp_stream_enc_count; i++)
dccg401_disable_dpstreamclk(dccg, i);
}
dccg42_disable_hdmistreamclk(dccg);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar)
dccg42_disable_hdmicharclk(dccg, 0);