struct tegra_bpmp::clocks is a pointer to a dynamically allocated array
of pointers to 'struct tegra_bpmp_clk'.
But the size of the allocated area is calculated like it is an array
containing actual 'struct tegra_bpmp_clk' objects - it's not true, there
are just pointers.
Found by Linux Verification Center (linuxtesting.org) with Svace static
analysis tool.
Fixes: 2db12b15c6 ("clk: tegra: Register clocks from root to leaf")
Signed-off-by: Fedor Pchelkin <pchelkin@ispras.ru>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Change the 'ret' variable in ep93xx_uart_clock_init() from unsigned int to
int, as it needs to store either negative error codes or zero.
Storing the negative error codes in unsigned type, doesn't cause an issue
at runtime but can be confusing. Additionally, assigning negative error
codes to unsigned type may trigger a GCC warning when the -Wsign-conversion
flag is enabled.
No effect on runtime.
Signed-off-by: Qianfeng Rong <rongqianfeng@vivo.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for Samsung's S2MPG10 PMIC clock, which is similar to the
existing PMIC clocks supported by this driver.
S2MPG10 has three clock outputs @ 32kHz: AP, peri1 and peri2.
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The Samsung S2MPG10 clock controller is similar to the existing clock
controllers supported by this binding. Register offsets / layout are
slightly different, so it needs its own compatible.
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
st/stih407-clock.dtsi file has been removed in commit 65322c1daf51
("clk: st: flexgen: remove unused compatible"). This file has three
compatibles which are now dangling. Remove them from documentation.
Signed-off-by: Raphael Gallais-Pou <rgallaispou@gmail.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Following B2120 boards removal in commit dee546e1ad ("ARM: sti: drop
B2120 board support"), several compatibles are left unused. Remove
them.
Signed-off-by: Raphael Gallais-Pou <rgallaispou@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Defining i2s_bclk and i2s_sysclk as fixed-rate clocks is insufficient
for real I2S use cases.
Moreover, the current I2S clock configuration does not work as expected
due to missing parent clocks.
This patch adds the missing parent clocks, defines i2s_sysclk as
a DDN clock, and i2s_bclk as a DIV clock.
A special note for i2s_bclk:
From the register definition, the i2s_bclk divider always implies
an additional 1/2 factor.
The following table shows the correspondence between index
and frequency division coefficients:
| index | div |
|-------|-------|
| 0 | 2 |
| 1 | 4 |
| 2 | 6 |
| 3 | 8 |
From a software perspective, introducing i2s_bclk_factor as the
parent of i2s_bclk is sufficient to address the issue.
The I2S-related clock registers can be found here [1].
Link:
https://developer.spacemit.com/documentation?token=LCrKwWDasiJuROkVNusc2pWTnEb
[1]
Fixes: 1b72c59db0 ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Co-developer: Jinmei Wei <weijinmei@linux.spacemit.com>
Suggested-by: Haylen Chu <heylenay@4d2.org>
Signed-off-by: Jinmei Wei <weijinmei@linux.spacemit.com>
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The original DDN operations applied an implicit divide-by-2, which should
not be a default behavior.
This patch removes that assumption, letting each clock define its
actual behavior explicitly.
Reviewed-by: Haylen Chu <heylenay@4d2.org>
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Previously, the K1 clock driver did not include the parent clocks of
the I2S sysclk.
Introduce pre-clock to fix I2S clock.
Otherwise, the I2S clock may not work as expected.
This patch adds their definitions to allow proper registration
in the driver and usage in the device tree.
Fixes: 1b72c59db0 ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The mt8183-mfgcfg node uses a power domain in its device tree node.
To prevent schema validation warnings, add the optional `power-domains`
property to the binding schema for mediatek syscon clocks.
Fixes: 1781f2c461 ("arm64: dts: mediatek: mt8183: Add power-domains properity to mfgcfg")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Julien Massot <julien.massot@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Convert to use devm_kmemdup_array() which is more robust.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
As described in AM335x Errata Advisory 1.0.42, WKUP_DEBUGSS_CLKCTRL
can't be disabled - the clock module will just be stuck in transitioning
state forever, resulting in the following warning message after the wait
loop times out:
l3-aon-clkctrl:0000:0: failed to disable
Just add the clock to enable_init_clks, so no attempt is made to disable
it.
Signed-off-by: Matthias Schiffer <matthias.schiffer@tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This tag contains two commits that are shared with the soc tree.
In this cycle support for power-of-two single divider clocks was added.
This covers some of the clocks found in the A523 MCU PRCM clock and
reset controller, for which support was added as well.
Besides the new controller, a missing clock was added for the A523's
main clock controller. The RTC clock driver gained specifics for the
A523's RTC block for tweaking the clock rate of the internal oscillator
to get it closer to what the RTC needs.
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Merge tag 'sunxi-clk-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clk driver updates from Chen-Yu Tsai:
In this cycle support for power-of-two single divider clocks was added.
This covers some of the clocks found in the A523 MCU PRCM clock and
reset controller, for which support was added as well.
Besides the new controller, a missing clock was added for the A523's
main clock controller. The RTC clock driver gained specifics for the
A523's RTC block for tweaking the clock rate of the internal oscillator
to get it closer to what the RTC needs.
* tag 'sunxi-clk-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: add support for the A523/T527 MCU CCU
clk: sunxi-ng: div: support power-of-two dividers
clk: sunxi-ng: sun55i-a523-ccu: Add missing NPU module clock
dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller
dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock
clk: sunxi-ng: sun6i-rtc: Add A523 specifics
- Rework the i.MX95 BLK CTL driver to add the platform data to the
state container.
- Retain the state of the i.MS95 BLK CTL registers through both
runtime and system suspend.
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Merge tag 'clk-imx-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
Pull i.MX clk driver updates from Abel Vesa:
- Rework the i.MX95 BLK CTL driver to add the platform data to
the state container
- Retain the state of the i.MS95 BLK CTL registers through both
runtime and system suspend
* tag 'clk-imx-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
clk: imx95-blk-ctl: Save/restore registers when RPM routines are called
clk: imx95-blk-ctl: Save platform data in imx95_blk_ctl structure
Add "clock-output-names" which is a standard property for clock
providers.
Add the "always-on" boolean property which was undocumented, but
already in use for some time. The flag prevents a clock output from
being disabled.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Tested-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add DFLL support on Tegra114. This is quite similar to the existing
Tegra124 support and most of the code can be reused, except for the
CVB frequency tables.
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Merge tag 'for-6.18-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-tegra
Pull Tegra clk driver updates from Thierry Reding:
- Add DFLL support on Tegra114
This is quite similar to the existing Tegra124 support and most
of the code can be reused, except for the CVB frequency tables.
* tag 'for-6.18-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: dfll: Add CVB tables for Tegra114
clk: tegra: Add DFLL DVCO reset control for Tegra114
dt-bindings: arm: tegra: Add ASUS TF101G and SL101
dt-bindings: reset: Add Tegra114 CAR header
dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101)
dt-bindings: clock: tegra30: Add IDs for CSI pad clocks
dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI
dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C
Extend the Tegra124 DFLL driver to include configuration settings
required for Tegra114 compatibility.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
[treding@nvidia.com: Use TEGRA210 instead of T210]
Signed-off-by: Thierry Reding <treding@nvidia.com>
1. Tesla FSD: Expose CSI clocks to consumers (DTS).
2. Exynos990:
- Few fixes for fixed factor clocks, register widths and proper PLL
parents.
- Add four more clocks for the DPU and HSI0 clock for USB.
- Add PERIC0 and PERIC1 clock controllers (CMU), responsible for
providing clocks to serial engines.
3. Add seven clock controllers for the new Axis ARTPEC-8 SoC. The SoC
shares all main blocks, including the clock controllers, with Samsung
SoC, so same drivers and bindings are used.
4. Cleanups: switch to determine_rate().
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Merge tag 'samsung-clk-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung SoC clk driver updates from Krzysztof Kozlowski:
- Tesla FSD: Expose CSI clocks to consumers (DTS)
- Exynos990:
- Few fixes for fixed factor clocks, register widths and proper PLL
parents
- Add four more clocks for the DPU and HSI0 clock for USB
- Add PERIC0 and PERIC1 clock controllers (CMU), responsible for
providing clocks to serial engines
- Add seven clock controllers for the new Axis ARTPEC-8 SoC. The SoC
shares all main blocks, including the clock controllers, with Samsung
SoC, so same drivers and bindings are used.
- Cleanups: switch to clk_ops::determine_rate()
* tag 'samsung-clk-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
clk: samsung: exynos990: Add PERIC0 and PERIC1 clock support
dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units
clk: samsung: exynos990: Add missing USB clock registers to HSI0
clk: samsung: exynos990: Add LHS_ACEL gate clock for HSI0 and update CLK_NR_TOP
dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block
clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC
clk: samsung: Add clock PLL support for ARTPEC-8 SoC
dt-bindings: clock: Add ARTPEC-8 clock controller
clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP
dt-bindings: clock: exynos990: Extend clocks IDs
clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks
clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths
clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes
clk: samsung: pll: convert from round_rate() to determine_rate()
clk: samsung: cpu: convert from round_rate() to determine_rate()
clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block
dt-bindings: clock: Add CAM_CSI clock macro for FSD
Updates for the T-HEAD TH1520 clock controller:
- Describe gate clocks with clk_gate so that clock gates can be clock
parents. This is similar to the mux clock refactor in 54edba916e
("clk: thead: th1520-ap: Describe mux clocks with clk_mux").
- Add support for enabling/disabling PLLs. Some PLLs are put into a
disabled state by the bootloader, and clock driver now has the
ability to enable them.
- Set all AXI clocks to CLK_IS_CRITICAL. The AXI crossbar of TH1520 has
no proper timeout handling, which means gating AXI clocks can easily
lead to bus timeout and hang the system. All these clock gates are
ungated by default on system reset.
- Convert all current CLK_IGNORE_UNUSED usage to CLK_IS_CRITICAL to
prevent unwanted clock gating.
- Fix parent of padctrl0 clock, fix parent of DPU pixel clocks and
support changing DPU pixel clock rate.
All changes have been tested in linux-next.
Signed-off-by: Drew Fustini <fustini@kernel.org>
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Merge tag 'thead-clk-for-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into clk-thead
Pull T-HEAD clock driver updates from Drew Fustini:
- Describe gate clocks with clk_gate so that clock gates can be clock
parents. This is similar to the mux clock refactor in 54edba916e
("clk: thead: th1520-ap: Describe mux clocks with clk_mux").
- Add support for enabling/disabling PLLs. Some PLLs are put into a
disabled state by the bootloader, and clock driver now has the
ability to enable them.
- Set all AXI clocks to CLK_IS_CRITICAL. The AXI crossbar of TH1520 has
no proper timeout handling, which means gating AXI clocks can easily
lead to bus timeout and hang the system. All these clock gates are
ungated by default on system reset.
- Convert all current CLK_IGNORE_UNUSED usage to CLK_IS_CRITICAL to
prevent unwanted clock gating.
- Fix parent of padctrl0 clock, fix parent of DPU pixel clocks and
support changing DPU pixel clock rate.
* tag 'thead-clk-for-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux:
clk: thead: th1520-ap: set all AXI clocks to CLK_IS_CRITICAL
clk: thead: support changing DPU pixel clock rate
clk: thead: add support for enabling/disabling PLLs
clk: thead: Correct parent for DPU pixel clocks
clk: thead: th1520-ap: fix parent of padctrl0 clock
clk: thead: th1520-ap: describe gate clocks with clk_gate
The A523/T527 SoCs have a new MCU PRCM, which has more clocks and reset
controls for the RISC-V MCU and other peripherals. There is a second
audio PLL, but no bus clock dividers. The BSP driver uses the 24MHz main
oscillator as the parent for all the bus clocks. But the diagram
suggests busses from the other PRCM are used in this block as well.
Add a driver to support this part. Unlike the BSP driver, the SoC's main
MBUS clock is chosen as the parent for the MCU MBUS clock, and the
latter then serves as the parent of the MCU DMA controller's MBUS clock.
The bus gate clocks also use their respective bus clocks as parents
according to the system bus tree diagram. In cases where a block does
not appear in that diagram, an educated guess is made.
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250911174710.3149589-6-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Some clocks (for timers) on the A523 are mux-divider-gate types
with the divider being values of power-of-two.
Add a macro for these types of clocks so that we can use the divider
types instead of the M-P types without an M divider.
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250911174710.3149589-5-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The main clock controller on the A523/T527 has the NPU's module clock.
It was missing from the original submission, likely because that was
based on the A523 user manual; the A523 is marketed without the NPU.
Also, merge the private header back into the driver code itself. The
header only contains a macro containing the total number of clocks.
This has to be updated every time a missing clock gets added. Having
it in a separate file doesn't help the process. Instead just drop the
macro, and thus the header no longer has any reason to exist.
Also move the .num value to after the list of clks to make it obvious
that it should be updated when new clks are added.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250911174710.3149589-4-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
There are four clock controllers in the A523 SoC. The existing binding
already covers two of them that are critical for basic operation. The
remaining ones are the MCU clock controller and CPU PLL clock
controller.
Add a description for the MCU CCU. This unit controls and provides
clocks to the MCU (RISC-V) subsystem and peripherals meant to operate
under low power conditions.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250911174710.3149589-3-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The main clock controller on the A523/T527 has the NPU's module clock.
It was missing from the original submission, likely because that was
based on the A523 user manual; the A523 is marketed without the NPU.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250911174710.3149589-2-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
When runtime PM is used for clock providers that are part of a power
domain, the power domain supply is cut off during runtime suspend. This
causes all BLK CTL registers belonging to that power domain to reset. To
prevent this, save the state of the registers before entering suspend
and restore them on resume. Additionally, disable the APB clock during
suspend to minimize power consumption.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20250804131450.3918846-3-laurentiu.palcu@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Add a platform data (pdata) member to struct imx95_blk_ctl to store the
result of of_device_get_match_data() during probe to avoid redundant
calls in suspend and resume functions.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20250804131450.3918846-2-laurentiu.palcu@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
In case of krealloc_array() failure, the current error handling just
returns from the function without freeing the original array.
Fix this memory leak by freeing the original array.
Fixes: 6aa1754764 ("clk: renesas: cpg-mssr: Ignore all clocks assigned to non-Linux system")
Signed-off-by: Yuan CHen <chenyuan@kylinos.cn>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250908012810.4767-1-chenyuan_fl@163.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The A523's RTC block is backward compatible with the R329's, but it also
has a calibration function for its internal oscillator, which would
allow it to provide a clock rate closer to the desired 32.768 KHz. This
is useful on the Radxa Cubie A5E, which does not have an external 32.768
KHz crystal.
Add new compatible-specific data for it.
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250909170947.2221611-1-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The DVCO present in the DFLL IP block has a separate reset line, exposed
via the CAR IP block. This reset line is asserted upon SoC reset.
Unless something (such as the DFLL driver) deasserts this line, the DVCO
will not oscillate, although reads and writes to the DFLL IP block will
complete.
Based on a3c83ff2 ("clk: tegra: Add DFLL DVCO reset control for Tegra124")
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a compatible for ASUS Eee Pad Transformer TF101G and ASUS Eee Pad
Slider SL101.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The way that resets are handled on these Tegra devices is that there is a
set of peripheral clocks & resets which are paired up. This is because they
are laid out in banks within the CAR (clock and reset) controller. In most
cases we're referring to those resets, so you'll often see a clock ID used
in conjection with the same reset ID for a given IP block.
In addition to those peripheral resets, there are a number of extra resets
that don't have a corresponding clock and which are exposed in registers
outside of the peripheral banks, but still part of the CAR. To support
those "special" registers, the TEGRA*_RESET() is used to denote resets
outside of the regular peripheral resets. Essentially it defines the offset
within the CAR at which special resets start. In the above case, Tegra114
has 5 banks with 32 peripheral resets each. The first special reset,
TEGRA114_RESET(0), therefore gets ID 5 * 32 + 0 = 160.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a compatible for the Xiaomi Mi Pad (A0101) tablet.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra30 has CSI pad clock enable bits embedded into PLLD/PLLD2 registers.
Add ids for these clocks. Additionally, move TEGRA30_CLK_CLK_MAX into
clk-tegra30 source.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The avdd-dsi-csi-supply is CSI power supply, it has nothing to do with
VI, like same supply is used with DSI and has nothing to do with DC.
Move it to correct place.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra264 has 17 generic I2C controllers, two of which are in always-on
partition of the SoC. In addition to the features supported by Tegra194
it also supports a SW mutex register to allow sharing the same I2C
instance across multiple firmware.
Document compatible string "nvidia,tegra264-i2c" for Tegra264 I2C.
Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
