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clk: tegra: Changes for v6.18-rc1

Browse Source 
Add DFLL support on Tegra114. This is quite similar to the existing
 Tegra124 support and most of the code can be reused, except for the
 CVB frequency tables.
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Merge tag 'for-6.18-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-tegra

Pull Tegra clk driver updates from Thierry Reding:

 - Add DFLL support on Tegra114

 This is quite similar to the existing Tegra124 support and most
 of the code can be reused, except for the CVB frequency tables.

* tag 'for-6.18-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  clk: tegra: dfll: Add CVB tables for Tegra114
  clk: tegra: Add DFLL DVCO reset control for Tegra114
  dt-bindings: arm: tegra: Add ASUS TF101G and SL101
  dt-bindings: reset: Add Tegra114 CAR header
  dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101)
  dt-bindings: clock: tegra30: Add IDs for CSI pad clocks
  dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI
  dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C
This commit is contained in:
Stephen Boyd 2025-09-15 18:11:00 -07:00
commit ccd74beccd
11 changed files with 194 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
Documentation/devicetree/bindings/arm/tegra.yaml
View File

@ -36,8 +36,12 @@ properties:
- toradex,colibri_t20-iris
- const: toradex,colibri_t20
- const: nvidia,tegra20
- items:
- const: asus,tf101
- description: ASUS Transformers T20 Device family
items:
- enum:
- asus,sl101
- asus,tf101
- asus,tf101g
- const: nvidia,tegra20
- items:
- const: acer,picasso
@ -174,6 +178,10 @@ properties:
- const: google,nyan-big
- const: google,nyan
- const: nvidia,tegra124
- description: Xiaomi Mi Pad (A0101)
items:
- const: xiaomi,mocha
- const: nvidia,tegra124
- items:
- enum:
- nvidia,darcy

3
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
View File

@ -70,9 +70,6 @@ properties:
ranges:
maxItems: 1
avdd-dsi-csi-supply:
description: DSI/CSI power supply. Must supply 1.2 V.
vip:
$ref: /schemas/display/tegra/nvidia,tegra20-vip.yaml

3
Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
View File

@ -37,6 +37,9 @@ properties:
- const: cile
- const: csi_tpg
avdd-dsi-csi-supply:
description: DSI/CSI power supply. Must supply 1.2 V.
power-domains:
maxItems: 1

7
Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
View File

@ -80,6 +80,12 @@ properties:
support for 64 KiB transactions whereas earlier chips supported no
more than 4 KiB per transactions.
const: nvidia,tegra194-i2c
- description:
Tegra264 has 17 generic I2C controllers, two of which are in the AON
(always-on) partition of the SoC. In addition to the features from
Tegra194, a SW mutex register is added to support use of the same I2C
instance across multiple firmwares.
const: nvidia,tegra264-i2c
reg:
maxItems: 1
@ -186,6 +192,7 @@ allOf:
contains:
enum:
- nvidia,tegra194-i2c
- nvidia,tegra264-i2c
then:
required:
- resets

2
drivers/clk/tegra/Kconfig
View File

@ -4,7 +4,7 @@ config CLK_TEGRA_BPMP
depends on TEGRA_BPMP
config TEGRA_CLK_DFLL
depends on ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC
depends on ARCH_TEGRA_114_SOC || ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC
select PM_OPP
def_bool y

30
drivers/clk/tegra/clk-tegra114.c
View File

@ -11,6 +11,7 @@
#include <linux/export.h>
#include <linux/clk/tegra.h>
#include <dt-bindings/clock/tegra114-car.h>
#include <dt-bindings/reset/nvidia,tegra114-car.h>
#include "clk.h"
#include "clk-id.h"
@ -1272,7 +1273,7 @@ EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init);
*
* Assert the reset line of the DFLL's DVCO. No return value.
*/
void tegra114_clock_assert_dfll_dvco_reset(void)
static void tegra114_clock_assert_dfll_dvco_reset(void)
{
u32 v;
@ -1281,7 +1282,6 @@ void tegra114_clock_assert_dfll_dvco_reset(void)
writel_relaxed(v, clk_base + RST_DFLL_DVCO);
tegra114_car_barrier();
}
EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
/**
* tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
@ -1289,7 +1289,7 @@ EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
* Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
* operate. No return value.
*/
void tegra114_clock_deassert_dfll_dvco_reset(void)
static void tegra114_clock_deassert_dfll_dvco_reset(void)
{
u32 v;
@ -1298,7 +1298,26 @@ void tegra114_clock_deassert_dfll_dvco_reset(void)
writel_relaxed(v, clk_base + RST_DFLL_DVCO);
tegra114_car_barrier();
}
EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
static int tegra114_reset_assert(unsigned long id)
{
if (id == TEGRA114_RST_DFLL_DVCO)
tegra114_clock_assert_dfll_dvco_reset();
else
return -EINVAL;
return 0;
}
static int tegra114_reset_deassert(unsigned long id)
{
if (id == TEGRA114_RST_DFLL_DVCO)
tegra114_clock_deassert_dfll_dvco_reset();
else
return -EINVAL;
return 0;
}
static void __init tegra114_clock_init(struct device_node *np)
{
@ -1344,6 +1363,9 @@ static void __init tegra114_clock_init(struct device_node *np)
tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
&pll_x_params);
tegra_init_special_resets(1, tegra114_reset_assert,
tegra114_reset_deassert);
tegra_add_of_provider(np, of_clk_src_onecell_get);
tegra_register_devclks(devclks, ARRAY_SIZE(devclks));

158
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
View File

@ -28,6 +28,99 @@ struct dfll_fcpu_data {
unsigned int cpu_cvb_tables_size;
};
/* Maximum CPU frequency, indexed by CPU speedo id */
static const unsigned long tegra114_cpu_max_freq_table[] = {
[0] = 2040000000UL,
[1] = 1810500000UL,
[2] = 1912500000UL,
[3] = 1810500000UL,
};
#define T114_CPU_CVB_TABLE \
.min_millivolts = 1000, \
.max_millivolts = 1320, \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 306000000UL, { 2190643, -141851, 3576 } }, \
{ 408000000UL, { 2250968, -144331, 3576 } }, \
{ 510000000UL, { 2313333, -146811, 3576 } }, \
{ 612000000UL, { 2377738, -149291, 3576 } }, \
{ 714000000UL, { 2444183, -151771, 3576 } }, \
{ 816000000UL, { 2512669, -154251, 3576 } }, \
{ 918000000UL, { 2583194, -156731, 3576 } }, \
{ 1020000000UL, { 2655759, -159211, 3576 } }, \
{ 1122000000UL, { 2730365, -161691, 3576 } }, \
{ 1224000000UL, { 2807010, -164171, 3576 } }, \
{ 1326000000UL, { 2885696, -166651, 3576 } }, \
{ 1428000000UL, { 2966422, -169131, 3576 } }, \
{ 1530000000UL, { 3049183, -171601, 3576 } }, \
{ 1606500000UL, { 3112179, -173451, 3576 } }, \
{ 1708500000UL, { 3198504, -175931, 3576 } }, \
{ 1810500000UL, { 3304747, -179126, 3576 } }, \
{ 1912500000UL, { 3395401, -181606, 3576 } }, \
{ 0UL, { 0, 0, 0 } }, \
}, \
.cpu_dfll_data = { \
.tune0_low = 0x00b0039d, \
.tune0_high = 0x00b0009d, \
.tune1 = 0x0000001f, \
.tune_high_min_millivolts = 1050, \
}
static const struct cvb_table tegra114_cpu_cvb_tables[] = {
{
.speedo_id = 0,
.process_id = -1,
.min_millivolts = 1000,
.max_millivolts = 1250,
.speedo_scale = 100,
.voltage_scale = 100,
.entries = {
{ 306000000UL, { 107330, -1569, 0 } },
{ 408000000UL, { 111250, -1666, 0 } },
{ 510000000UL, { 110000, -1460, 0 } },
{ 612000000UL, { 117290, -1745, 0 } },
{ 714000000UL, { 122700, -1910, 0 } },
{ 816000000UL, { 125620, -1945, 0 } },
{ 918000000UL, { 130560, -2076, 0 } },
{ 1020000000UL, { 137280, -2303, 0 } },
{ 1122000000UL, { 146440, -2660, 0 } },
{ 1224000000UL, { 152190, -2825, 0 } },
{ 1326000000UL, { 157520, -2953, 0 } },
{ 1428000000UL, { 166100, -3261, 0 } },
{ 1530000000UL, { 176410, -3647, 0 } },
{ 1632000000UL, { 189620, -4186, 0 } },
{ 1734000000UL, { 203190, -4725, 0 } },
{ 1836000000UL, { 222670, -5573, 0 } },
{ 1938000000UL, { 256210, -7165, 0 } },
{ 2040000000UL, { 250050, -6544, 0 } },
{ 0UL, { 0, 0, 0 } },
},
.cpu_dfll_data = {
.tune0_low = 0x00b0019d,
.tune0_high = 0x00b0019d,
.tune1 = 0x0000001f,
.tune_high_min_millivolts = 1000,
}
},
{
.speedo_id = 1,
.process_id = -1,
T114_CPU_CVB_TABLE
},
{
.speedo_id = 2,
.process_id = -1,
T114_CPU_CVB_TABLE
},
{
.speedo_id = 3,
.process_id = -1,
T114_CPU_CVB_TABLE
},
};
/* Maximum CPU frequency, indexed by CPU speedo id */
static const unsigned long tegra124_cpu_max_freq_table[] = {
[0] = 2014500000UL,
@ -93,7 +186,7 @@ static const unsigned long tegra210_cpu_max_freq_table[] = {
[10] = 1504500000UL,
};
#define CPU_CVB_TABLE \
#define TEGRA210_CPU_CVB_TABLE \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
@ -120,7 +213,7 @@ static const unsigned long tegra210_cpu_max_freq_table[] = {
{ 0UL, { 0, 0, 0 } }, \
}
#define CPU_CVB_TABLE_XA \
#define TEGRA210_CPU_CVB_TABLE_XA \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
@ -143,7 +236,7 @@ static const unsigned long tegra210_cpu_max_freq_table[] = {
{ 0UL, { 0, 0, 0 } }, \
}
#define CPU_CVB_TABLE_EUCM1 \
#define TEGRA210_CPU_CVB_TABLE_EUCM1 \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
@ -166,7 +259,7 @@ static const unsigned long tegra210_cpu_max_freq_table[] = {
{ 0UL, { 0, 0, 0 } }, \
}
#define CPU_CVB_TABLE_EUCM2 \
#define TEGRA210_CPU_CVB_TABLE_EUCM2 \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
@ -188,7 +281,7 @@ static const unsigned long tegra210_cpu_max_freq_table[] = {
{ 0UL, { 0, 0, 0 } }, \
}
#define CPU_CVB_TABLE_EUCM2_JOINT_RAIL \
#define TEGRA210_CPU_CVB_TABLE_EUCM2_JOINT_RAIL \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
@ -209,7 +302,7 @@ static const unsigned long tegra210_cpu_max_freq_table[] = {
{ 0UL, { 0, 0, 0 } }, \
}
#define CPU_CVB_TABLE_ODN \
#define TEGRA210_CPU_CVB_TABLE_ODN \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
@ -238,7 +331,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 0,
.min_millivolts = 840,
.max_millivolts = 1120,
CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
TEGRA210_CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
@ -251,7 +344,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 1,
.min_millivolts = 840,
.max_millivolts = 1120,
CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
TEGRA210_CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
@ -264,7 +357,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 0,
.min_millivolts = 900,
.max_millivolts = 1162,
CPU_CVB_TABLE_EUCM2,
TEGRA210_CPU_CVB_TABLE_EUCM2,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
@ -276,7 +369,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 1,
.min_millivolts = 900,
.max_millivolts = 1162,
CPU_CVB_TABLE_EUCM2,
TEGRA210_CPU_CVB_TABLE_EUCM2,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
@ -288,7 +381,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 0,
.min_millivolts = 900,
.max_millivolts = 1195,
CPU_CVB_TABLE_EUCM2,
TEGRA210_CPU_CVB_TABLE_EUCM2,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
@ -300,7 +393,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 1,
.min_millivolts = 900,
.max_millivolts = 1195,
CPU_CVB_TABLE_EUCM2,
TEGRA210_CPU_CVB_TABLE_EUCM2,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
@ -312,7 +405,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 0,
.min_millivolts = 841,
.max_millivolts = 1227,
CPU_CVB_TABLE_EUCM1,
TEGRA210_CPU_CVB_TABLE_EUCM1,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
@ -325,7 +418,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 1,
.min_millivolts = 841,
.max_millivolts = 1227,
CPU_CVB_TABLE_EUCM1,
TEGRA210_CPU_CVB_TABLE_EUCM1,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
@ -338,7 +431,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 0,
.min_millivolts = 870,
.max_millivolts = 1150,
CPU_CVB_TABLE,
TEGRA210_CPU_CVB_TABLE,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune1 = 0x20091d9,
@ -349,7 +442,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 1,
.min_millivolts = 870,
.max_millivolts = 1150,
CPU_CVB_TABLE,
TEGRA210_CPU_CVB_TABLE,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune1 = 0x25501d0,
@ -360,7 +453,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 0,
.min_millivolts = 818,
.max_millivolts = 1227,
CPU_CVB_TABLE,
TEGRA210_CPU_CVB_TABLE,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
@ -373,7 +466,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 1,
.min_millivolts = 818,
.max_millivolts = 1227,
CPU_CVB_TABLE,
TEGRA210_CPU_CVB_TABLE,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
@ -386,7 +479,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = -1,
.min_millivolts = 918,
.max_millivolts = 1113,
CPU_CVB_TABLE_XA,
TEGRA210_CPU_CVB_TABLE_XA,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune1 = 0x17711BD,
@ -397,7 +490,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 0,
.min_millivolts = 825,
.max_millivolts = 1227,
CPU_CVB_TABLE_ODN,
TEGRA210_CPU_CVB_TABLE_ODN,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
@ -410,7 +503,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 1,
.min_millivolts = 825,
.max_millivolts = 1227,
CPU_CVB_TABLE_ODN,
TEGRA210_CPU_CVB_TABLE_ODN,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
@ -423,7 +516,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 0,
.min_millivolts = 870,
.max_millivolts = 1227,
CPU_CVB_TABLE,
TEGRA210_CPU_CVB_TABLE,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune1 = 0x20091d9,
@ -434,7 +527,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 1,
.min_millivolts = 870,
.max_millivolts = 1227,
CPU_CVB_TABLE,
TEGRA210_CPU_CVB_TABLE,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune1 = 0x25501d0,
@ -445,7 +538,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 0,
.min_millivolts = 837,
.max_millivolts = 1227,
CPU_CVB_TABLE,
TEGRA210_CPU_CVB_TABLE,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
@ -458,7 +551,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 1,
.min_millivolts = 837,
.max_millivolts = 1227,
CPU_CVB_TABLE,
TEGRA210_CPU_CVB_TABLE,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
@ -471,7 +564,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 0,
.min_millivolts = 850,
.max_millivolts = 1170,
CPU_CVB_TABLE,
TEGRA210_CPU_CVB_TABLE,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
@ -484,7 +577,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
.process_id = 1,
.min_millivolts = 850,
.max_millivolts = 1170,
CPU_CVB_TABLE,
TEGRA210_CPU_CVB_TABLE,
.cpu_dfll_data = {
.tune0_low = 0xffead0ff,
.tune0_high = 0xffead0ff,
@ -494,6 +587,13 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
},
};
static const struct dfll_fcpu_data tegra114_dfll_fcpu_data = {
.cpu_max_freq_table = tegra114_cpu_max_freq_table,
.cpu_max_freq_table_size = ARRAY_SIZE(tegra114_cpu_max_freq_table),
.cpu_cvb_tables = tegra114_cpu_cvb_tables,
.cpu_cvb_tables_size = ARRAY_SIZE(tegra114_cpu_cvb_tables)
};
static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = {
.cpu_max_freq_table = tegra124_cpu_max_freq_table,
.cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table),
@ -509,6 +609,10 @@ static const struct dfll_fcpu_data tegra210_dfll_fcpu_data = {
};
static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
{
.compatible = "nvidia,tegra114-dfll",
.data = &tegra114_dfll_fcpu_data,
},
{
.compatible = "nvidia,tegra124-dfll",
.data = &tegra124_dfll_fcpu_data,

1
drivers/clk/tegra/clk-tegra30.c
View File

@ -53,6 +53,7 @@
#define SYSTEM_CLK_RATE 0x030
#define TEGRA30_CLK_PERIPH_BANKS 5
#define TEGRA30_CLK_CLK_MAX 311
#define PLLC_BASE 0x80
#define PLLC_MISC 0x8c

2
drivers/clk/tegra/clk.h
View File

@ -897,8 +897,6 @@ static inline bool tegra124_clk_emc_driver_available(struct clk_hw *emc_hw)
void tegra114_clock_tune_cpu_trimmers_high(void);
void tegra114_clock_tune_cpu_trimmers_low(void);
void tegra114_clock_tune_cpu_trimmers_init(void);
void tegra114_clock_assert_dfll_dvco_reset(void);
void tegra114_clock_deassert_dfll_dvco_reset(void);
typedef void (*tegra_clk_apply_init_table_func)(void);
extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;

3
include/dt-bindings/clock/tegra30-car.h
View File

@ -271,6 +271,7 @@
#define TEGRA30_CLK_AUDIO3_MUX 306
#define TEGRA30_CLK_AUDIO4_MUX 307
#define TEGRA30_CLK_SPDIF_MUX 308
#define TEGRA30_CLK_CLK_MAX 309
#define TEGRA30_CLK_CSIA_PAD 309
#define TEGRA30_CLK_CSIB_PAD 310
#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */

13
include/dt-bindings/reset/nvidia,tegra114-car.h Normal file
View File

@ -0,0 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* This header provides Tegra114-specific constants for binding
* nvidia,tegra114-car.
*/
#ifndef _DT_BINDINGS_RESET_NVIDIA_TEGRA114_CAR_H
#define _DT_BINDINGS_RESET_NVIDIA_TEGRA114_CAR_H
#define TEGRA114_RESET(x) (5 * 32 + (x))
#define TEGRA114_RST_DFLL_DVCO TEGRA114_RESET(0)
#endif /* _DT_BINDINGS_RESET_NVIDIA_TEGRA114_CAR_H */