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Linux kernel source tree
3153d7b8f1
1. Tesla FSD: Expose CSI clocks to consumers (DTS).
2. Exynos990:
- Few fixes for fixed factor clocks, register widths and proper PLL
parents.
- Add four more clocks for the DPU and HSI0 clock for USB.
- Add PERIC0 and PERIC1 clock controllers (CMU), responsible for
providing clocks to serial engines.
3. Add seven clock controllers for the new Axis ARTPEC-8 SoC. The SoC
shares all main blocks, including the clock controllers, with Samsung
SoC, so same drivers and bindings are used.
4. Cleanups: switch to determine_rate().
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Merge tag 'samsung-clk-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung SoC clk driver updates from Krzysztof Kozlowski:
- Tesla FSD: Expose CSI clocks to consumers (DTS)
- Exynos990:
- Few fixes for fixed factor clocks, register widths and proper PLL
parents
- Add four more clocks for the DPU and HSI0 clock for USB
- Add PERIC0 and PERIC1 clock controllers (CMU), responsible for
providing clocks to serial engines
- Add seven clock controllers for the new Axis ARTPEC-8 SoC. The SoC
shares all main blocks, including the clock controllers, with Samsung
SoC, so same drivers and bindings are used.
- Cleanups: switch to clk_ops::determine_rate()
* tag 'samsung-clk-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
clk: samsung: exynos990: Add PERIC0 and PERIC1 clock support
dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units
clk: samsung: exynos990: Add missing USB clock registers to HSI0
clk: samsung: exynos990: Add LHS_ACEL gate clock for HSI0 and update CLK_NR_TOP
dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block
clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC
clk: samsung: Add clock PLL support for ARTPEC-8 SoC
dt-bindings: clock: Add ARTPEC-8 clock controller
clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP
dt-bindings: clock: exynos990: Extend clocks IDs
clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks
clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths
clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes
clk: samsung: pll: convert from round_rate() to determine_rate()
clk: samsung: cpu: convert from round_rate() to determine_rate()
clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block
dt-bindings: clock: Add CAM_CSI clock macro for FSD
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Linux kernel
============
There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.
In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``. The formatted documentation can also be read online at:
https://www.kernel.org/doc/html/latest/
There are various text files in the Documentation/ subdirectory,
several of them using the reStructuredText markup notation.
Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.