Commit Graph

1444057 Commits

Author SHA1 Message Date
Bjorn Andersson
23cee0d07a Merge branch '20260227061544.1785978-1-praveen.talari@oss.qualcomm.com' into drivers-for-7.2
Merge the refactoring and helper functions in the Qualcomm GENI Serial
Engine driver through a topic branch.

These changes will provide the ability to add support managing power and
performance for the GENI instances in platforms where these are
controlled as SCMI resources.

The patches are merged through a topic branch to avoid conflicts with other
changes, while making them available to other subsystems.

Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-21 22:00:31 -05:00
Praveen Talari
c012e28e9a soc: qcom: geni-se: Introduce helper APIs for performance control
The GENI Serial Engine (SE) drivers (I2C, SPI, and SERIAL) currently
manage performance levels and operating points directly. This resulting
in code duplication across drivers. such as configuring a specific level
or find and apply an OPP based on a clock frequency.

Introduce two new helper APIs, geni_se_set_perf_level() and
geni_se_set_perf_opp(), addresses this issue by providing a streamlined
method for the GENI Serial Engine (SE) drivers to find and set the OPP
based on the desired performance level, thereby eliminating redundancy.

Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260227061544.1785978-8-praveen.talari@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-21 21:56:38 -05:00
Praveen Talari
f1a325d281 soc: qcom: geni-se: Introduce helper API for attaching power domains
The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently handle
the attachment of power domains. This often leads to duplicated code
logic across different driver probe functions.

Introduce a new helper API, geni_se_domain_attach(), to centralize
the logic for attaching "power" and "perf" domains to the GENI SE
device.

Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260227061544.1785978-7-praveen.talari@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-21 21:56:38 -05:00
Praveen Talari
8f4ce470ff soc: qcom: geni-se: Add resources activation/deactivation helpers
The GENI SE protocol drivers (I2C, SPI, UART) implement similar resource
activation/deactivation sequences independently, leading to code
duplication.

Introduce geni_se_resources_activate()/geni_se_resources_deactivate() to
power on/off resources.The activate function enables ICC, clocks, and TLMM
whereas the deactivate function disables resources in reverse order
including OPP rate reset, clocks, ICC and TLMM.

Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260227061544.1785978-6-praveen.talari@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-21 21:56:38 -05:00
Praveen Talari
e5f54cda9d soc: qcom: geni-se: Handle core clk in geni_se_clks_off() and geni_se_clks_on()
Currently, core clk is handled individually in protocol drivers like
the I2C driver. Move this clock management to the common clock APIs
(geni_se_clks_on/off) that are already present in the common GENI SE
driver to maintain consistency across all protocol drivers.

Core clk is now properly managed alongside the other clocks (se->clk
and wrapper clocks) in the fundamental clock control functions,
eliminating the need for individual protocol drivers to handle this
clock separately.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260227061544.1785978-5-praveen.talari@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-21 21:56:38 -05:00
Praveen Talari
5b8a39dcf9 soc: qcom: geni-se: Introduce helper API for resource initialization
The GENI Serial Engine drivers (I2C, SPI, and SERIAL) currently duplicate
code for initializing shared resources such as clocks and interconnect
paths.

Introduce a new helper API, geni_se_resources_init(), to centralize this
initialization logic, improving modularity and simplifying the probe
function.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260227061544.1785978-4-praveen.talari@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-21 21:56:38 -05:00
Praveen Talari
f746fedb89 soc: qcom: geni-se: Add geni_icc_set_bw_ab() function
Add a new function geni_icc_set_bw_ab() that allows callers to set
average bandwidth values for all ICC (Interconnect) paths in a single
call. This function takes separate parameters for core, config, and DDR
average bandwidth values and applies them to the respective ICC paths.

This provides a more convenient API for drivers that need to configure
specific average bandwidth values.

Co-developed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260227061544.1785978-3-praveen.talari@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-21 21:56:38 -05:00
Praveen Talari
e231930279 soc: qcom: geni-se: Refactor geni_icc_get() and make qup-memory ICC path optional
The "qup-memory" interconnect path is optional and may not be defined
in all device trees. Unroll the loop-based ICC path initialization to
allow specific error handling for each path type.

The "qup-core" and "qup-config" paths remain mandatory and will fail
probe if missing, while "qup-memory" is now handled as optional and
skipped when not present in the device tree.

Co-developed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
Reviewed-by: Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>
[...]
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Link: https://lore.kernel.org/r/20260227061544.1785978-2-praveen.talari@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-21 21:56:37 -05:00
Dan Carpenter
db0ec1ad72 soc: qcom: llcc-qcom: Fix NULL vs IS_ERR() bug in qcom_llcc_get_fw_config()
The devm_memremap() function doesn't return NULL, it returns error
pointers.  Fix the error checking to match.

Fixes: ac23106a9b ("soc: qcom: llcc-qcom: get SCT descriptors from fw-populated memory")
Signed-off-by: Dan Carpenter <error27@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/ag1N_rAHEQ1YJsa7@stanley.mountain
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-21 21:51:04 -05:00
Abel Vesa
0a4d53ae2c soc: qcom: llcc-qcom: Add support for Eliza
Eliza uses a 4-region LLCC register layout made up of two per-bank base
register regions together with the broadcast OR and AND regions.

So add this SoC specific configuration and its compatible string.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260513-eliza-llcc-v2-2-27381ae833d5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-21 16:16:03 -05:00
Abel Vesa
6487b12a87 dt-bindings: cache: qcom,llcc: Document Eliza LLCC block
Document the Last Level Cache Controller on Eliza SoC. Eliza LLCC has 2
base register regions and an additional AND, OR broadcast region, total 4
register regions.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260513-eliza-llcc-v2-1-27381ae833d5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-21 16:15:49 -05:00
Bjorn Andersson
51c4071888 Merge branch '20260507-ubwc-rework-v4-4-c19593d20c1d@oss.qualcomm.com' into drivers-for-7.2
Merge the initial set of UBWC rework through a topic branch, to allow it
being shared with the DRM/MSM branch for the continuation.
2026-05-19 21:30:01 -05:00
Dmitry Baryshkov
c5e3f2a3ab soc: qcom: ubwc: add helper controlling AMSBC enablement
Adreno and MDSS drivers need to know whether to enable AMSBC. Add
separate helper, describing that feature.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260507-ubwc-rework-v4-4-c19593d20c1d@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-19 21:29:19 -05:00
Dmitry Baryshkov
b5f7365c44 soc: qcom: ubwc: define helper for MDSS and Adreno drivers
Define special helper returning version setting for MDSS and A8xx
drivers.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260507-ubwc-rework-v4-3-c19593d20c1d@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-19 21:29:19 -05:00
Dmitry Baryshkov
ab7e4d7cf6 soc: qcom: ubwc: define UBWC 3.1
Follow the comment for the macrotile_mode and introduce separate
revision for UBWC 3.0 + 8-channel macrotiling mode. It is not used by
the database (since the drivers are not yet changed to handle it yet).

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260507-ubwc-rework-v4-2-c19593d20c1d@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-19 21:29:18 -05:00
Deepti Jaggi
b0bc160c31 soc: qcom: socinfo: Add SoC ID for Nord SA8797P
Add Nord SA8797P SoC ID to socinfo driver.

Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260427003531.229671-3-shengchao.guo@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-18 22:39:45 -05:00
Deepti Jaggi
0670a10b7c dt-bindings: arm: qcom,ids: Add SoC ID for Nord SA8797P
Nord is a SoC family from Qualcomm designed as the next generation of
Lemans series. SA8797P is the automotive variant of Nord, where platform
resources such as clocks, regulators, interconnects, etc. are managed
by firmware through SCMI.

Add SoC ID for Nord SA8797P.

Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260427003531.229671-2-shengchao.guo@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-18 22:39:36 -05:00
Alexander Koskovich
d8eae83cef soc: qcom: socinfo: Add SoC ID for SM7750
Recognize the SM7750 SoC which is an Eliza SoC variant.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260412-sm7550-id-v1-2-958a673ff791@pm.me
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-18 22:39:05 -05:00
Alexander Koskovich
5073d28465 dt-bindings: arm: qcom,ids: Add SoC ID for SM7750
Document the ID for SM7750, an Eliza SoC variant that can be found on
the Nothing Phone (4a) Pro.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260412-sm7550-id-v1-1-958a673ff791@pm.me
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-18 22:39:05 -05:00
Shawn Guo
a92d3fdb44 soc: qcom: socinfo: Add PMIC PMAU0102
Add PMAU0102 found on Nord boards to pmic_models array.

Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260419131523.1232835-1-shengchao.guo@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-18 22:38:50 -05:00
Alexander Koskovich
b3990b52de soc: qcom: socinfo: Add PMIV0102 & PMIV0104 PMICs
Add the PMIV0102 and PMIV0104 to the pmic_models array.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
Link: https://lore.kernel.org/r/20260413-add-pmic-ids-v1-1-1f40b8773ef8@pm.me
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-18 22:38:17 -05:00
Harrison Vanderbyl
667d05a09d firmware: qcom: scm: Allow QSEECOM on Surface Pro 12in
Add the Surface Pro 12in to the QSEECOM allowlist
so that the Qualcomm Secure Execution Environment
interface is available on this device.

Signed-off-by: Harrison Vanderbyl <harrison.vanderbyl@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/92171ad5e7851e6758dd205246b4289f32e12655.1778498477.git.harrison.vanderbyl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13 12:13:31 -05:00
Mukesh Ojha
b758be0232 soc: qcom: pd-mapper: Add support for Hawi SoC
Hawi uses the same protection domain layout as Kaanapali, so reuse the
kaanapali_domains table. Also add the missing adsp_ois_pd entry (OIS
protection domain, instance_id 74) to kaanapali_domains, which is
required by both Kaanapali and Hawi.

Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260506110226.2256249-1-mukesh.ojha@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13 11:52:28 -05:00
Mukesh Ojha
c5f5156ed4 dt-bindings: soc: qcom,aoss-qmp: Document the Hawi AOSS side channel
Document the Always-on Subsystem side channel on Qualcomm Hawi SoC.

Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260427181609.3648384-1-mukesh.ojha@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13 11:46:30 -05:00
Fenglin Wu
676f67060a dt-bindings: soc: qcom: qcom,pmic-glink: Add Hawi compatible string
Hawi is a mobile platform that is compatible with Kaanapali platform
with respect to pmic-glink support. Add the Hawi compatible string
with Kaanapali as a fallback.

Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260419-hawi-pmic-glink-v1-1-a26908c468fc@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13 11:46:09 -05:00
Mukesh Ojha
35246d44bb dt-bindings: firmware: qcom,scm: Document SCM on Hawi SoC
Document SCM compatible for the Qualcomm Hawi SoC.

Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20260401123825.589452-1-mukesh.ojha@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13 11:46:04 -05:00
Francisco Munoz Ruiz
06a84c2d3c soc: qcom: llcc-qcom: Capitalize LLCC/EDAC in comments and diagnostics
Capitalize occurrences of the acronym "LLCC" and "EDAC" in comments
and diagnostic text to improve consistency and readability.

Signed-off-by: Francisco Munoz Ruiz <francisco.ruiz@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260407-external_llcc_changes2set-v2-3-b5017ce2020b@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13 11:45:57 -05:00
Francisco Munoz Ruiz
ac23106a9b soc: qcom: llcc-qcom: get SCT descriptors from fw-populated memory
Retrieve System Cache Table (SCT) descriptors from a shared memory
region populated by firmware.

SCT initialization and programming are performed entirely by firmware
outside of Linux. The LLCC driver only consumes the pre-initialized
descriptor data and does not configure SCT itself.

Support this mechanism for future SoCs that provide SCT programming
via firmware.

Signed-off-by: Francisco Munoz Ruiz <francisco.ruiz@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260407-external_llcc_changes2set-v2-2-b5017ce2020b@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13 11:45:57 -05:00
Francisco Munoz Ruiz
cb4a414bac dt-bindings: cache: qcom,llcc: Document Hawi SoC
Add documentation for the Last Level Cache Controller (LLCC) bindings
to support Hawi SoC where the System Cache Table (SCT) is programmed
by firmware outside of Linux.

Introduce a property that specifies the base address of the shared
memory region from which the driver should read SCT descriptors
provided by firmware.

Signed-off-by: Francisco Munoz Ruiz <francisco.ruiz@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260407-external_llcc_changes2set-v2-1-b5017ce2020b@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13 11:45:57 -05:00
Konrad Dybcio
e225c13b15 soc: qcom: socinfo: Add PMICs that ship with Glymur
Add the missing REVID_PERPH_SUBTYPE<->name mappings for PMICs that ship
with Glymur.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260410-topic-glymur_pmics-v1-1-26bdbb577000@oss.qualcomm.com
[bjorn: Dropped 92,93,96,97,98 as these have already been applied]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-11 20:01:44 -05:00
Raj Aryan
95e3c6fe70 soc: qcom: spmi-pmic: add SUBTYPEs for Glymur/Kaanapali/SM8750 PMICs
On Glymur, Kaanapali, and SM8750, PMIC info is not being properly populated
in qcom_socinfo. Its shows `unknown` as PMIC subtypes are
not updated in the socinfo.

root@glymur-crd:/sys/kernel/debug/qcom_socinfo# cat pmic_model
unknown (92)
root@glymur-crd:/sys/kernel/debug/qcom_socinfo# cat pmic_model_array
unknown (92)
unknown (93)
unknown (98)
unknown (98)
unknown (97)
unknown (97)
unknown (96)
unknown (96)

Update the SUBTYPE info for PMICs present on Glymur,Kaanapali and
SM8750 boards, to fix this issue.

Also, there are some PMIC subtypes present in the socinfo but not
present in the spmi header file, add these entries to keep both definitions
aligned.

Signed-off-by: Raj Aryan <raryan@qti.qualcomm.com>
Link: https://lore.kernel.org/r/20260507-fury-v1-1-d24e4bb5b774@qti.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09 22:29:05 -05:00
Tony Truong
79602b750b soc: qcom: smem: Switch partitions to xarray
The partitions array is currently statically sized and uses the remote
host ID as an index.

Future protocol improvements to allow for more than two hosts in a
partition will require hostIDs to be bitwise significant integers.
This will result in large, sparse host IDs that generally exceed the
current static limit.

Switch to using xarray to efficiently handle these sparse indices and
allow for dynamic growth.

Signed-off-by: Tony Truong <tony.truong@oss.qualcomm.com>
Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> # On Nord
Tested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> # Glymur CRD
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Pranav Mahesh Phansalkar <pranav.phansalkar@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260423-smem-v3-1-582befff289a@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09 21:03:34 -05:00
Kathiravan Thirumoorthy
6fe5ea1989 soc: qcom: socinfo: add SoC ID for IPQ9650 family
Add SoC IDs for Qualcomm's IPQ9650 family.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260408-ipq9650_soc_ids-v1-2-e76faac33f77@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09 10:32:41 -05:00
Kathiravan Thirumoorthy
8baf66cc4c dt-bindings: arm: qcom,ids: add SOC IDs for IPQ9650 family
Add SoC IDs for Qualcomm's IPQ9650 family.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260408-ipq9650_soc_ids-v1-1-e76faac33f77@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09 10:32:41 -05:00
Rosen Penev
75c9015d0d soc: qcom: wcnss: fix leak of fw
The kzalloc_flex call needs to release it, not just blindly return.

Also move kfree up as it is allocated after fw.

Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <error27@gmail.com>
Closes: https://lore.kernel.org/r/202604060902.awXdPsBh-lkp@intel.com/
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://lore.kernel.org/r/20260407221519.6824-1-rosenp@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09 10:28:49 -05:00
Shawn Guo
a1b9413104 dt-bindings: firmware: qcom,scm: Document SCM for Nord SoC
Document SCM on Qualcomm Nord SoC which is compatible with 'qcom,scm'.

Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260427130800.271146-1-shengchao.guo@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09 10:02:03 -05:00
Deepti Jaggi
35466ef5db dt-bindings: qcom: geni-se-qup: Add compatible for SA8797P SoC
Document GENI Serial Engine QUP Wrapper Controller on Nord SA8797P SoC
which is compatible with SA8255P one.

Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260427005901.230237-1-shengchao.guo@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09 10:00:28 -05:00
Komal Bajaj
b828561684 soc: qcom: socinfo: Add SoC ID for Shikra IoT variants
Add SoC ID for Shikra IoT variants: CQ2390M, CQ2390S and IQ2390S.

Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260428-shikra-socid-v1-2-6ff16bad5ea2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09 10:00:13 -05:00
Komal Bajaj
928f6a0b1d dt-bindings: arm: qcom,ids: Add SoC ID for Shikra IoT variants
Document the IDs used by Shikra SoC IoT variants:
- CQ2390M: Shikra Retail with modem
- CQ2390S: Shikra Retail without modem
- IQ2390S: Shikra Industrial without modem

Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260428-shikra-socid-v1-1-6ff16bad5ea2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-09 10:00:12 -05:00
Komal Bajaj
f2e4a121f4 dt-bindings: cache: qcom,llcc: Document Shikra LLCC
Document the Last Level Cache Controller on Shikra SoC.

Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260502-shikra-llcc-binding-v1-1-1da4b1eff0a8@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-07 20:30:07 -05:00
Abel Vesa
7754a6b6a1 dt-bindings: soc: qcom,aoss-qmp: Document the Eliza Always-On Subsystem side channel
Document the Always-On Subsystem (AOSS) side channel found on the Qualcomm
Eliza SoC. It is used for communication with other clients, like
remoteprocs.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260504-eliza-bindings-aoss-v2-1-c3628ca79a25@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-07 20:29:57 -05:00
Abel Vesa
a390203b7e dt-bindings: soc: qcom: qcom,pmic-glink: Document Eliza compatible
Document the compatible for the PMIC GLINK interface found on the
Qualcomm Eliza SoC.

It is fully compatible with the one found on SM8550, so use that as
fallback.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260504-eliza-bindings-pmic-glink-v2-1-d6b5397b7899@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-07 20:29:50 -05:00
Linus Torvalds
254f49634e Linux 7.1-rc1 2026-04-26 14:19:00 -07:00
Linus Torvalds
14479877c1 One more fix for the merge window to avoid a boot hang on
Raspberry Pi 3B by marking the VEC clk critical so it doesn't get
 turned off and hang the bus.
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fix from Stephen Boyd:
 "One more fix for the merge window to avoid a boot hang on
  Raspberry Pi 3B by marking the VEC clk critical so that it
  doesn't get turned off and hang the bus"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: bcm: rpi: Mark VEC clock as CLK_IGNORE_UNUSED
2026-04-26 14:03:20 -07:00
Linus Torvalds
20b64cf870 tsm for 7.1
- Drop class_create() for the "tsm" class
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Merge tag 'tsm-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/devsec/tsm

Pull PCIe TSP update from Dan Williams:
 "A small update for the TSM core. It is arguably a fix and coming in
  late as I have been offline the past few weeks:

   - Drop class_create() for the 'tsm' class"

* tag 'tsm-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/devsec/tsm:
  virt: coco: change tsm_class to a const struct
2026-04-26 09:51:29 -07:00
Linus Torvalds
b935117fe6 First round of Kbuild fixes for 7.1
- kbuild: builddeb - avoid recompiles for non-cross-compiles
 
     Avoid triggering complete rebuilds for non-cross-compile Debian
     package builds by only triggering the rebuild of host tools for
     actual cross-compile builds.
 
   - kbuild: Never respect CONFIG_WERROR / W=e to fixdep
 
     Avoid spurious rebuilds of fixdep w/ and w/o -Werror during a single
     kbuild invocation by never respecting CONFIG_WERROR for fixdep.
 
 Cc: Masahiro Yamada <masahiroy@kernel.org>
 Cc: Mathias Krause <minipli@grsecurity.net>
 Cc: Nathan Chancellor <nathan@kernel.org>
 Cc: Thomas Weißschuh <linux@weissschuh.net>
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Merge tag 'kbuild-fixes-7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kbuild/linux

Pull Kbuild fixes from Nicolas Schier:

 - builddeb - avoid recompiles for non-cross-compiles

   Avoid triggering complete rebuilds for non-cross-compile Debian
   package builds by only triggering the rebuild of host tools for
   actual cross-compile builds

 - Never respect CONFIG_WERROR / W=e to fixdep

   Avoid spurious rebuilds of fixdep w/ and w/o -Werror during a single
   kbuild invocation by never respecting CONFIG_WERROR for fixdep

* tag 'kbuild-fixes-7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kbuild/linux:
  kbuild: Never respect CONFIG_WERROR / W=e to fixdep
  kbuild: builddeb - avoid recompiles for non-cross-compiles
2026-04-25 17:04:15 -07:00
Linus Torvalds
2ff1bc41ef Power Utilities 2026.04.25
tools/power x86_energy_perf_policy: v2026.04.25
 
 	Since v2025.11.22:
 
 	Initial SoC Slider support
 
 tools/power turbostat: v2026.04.21
 
 	Since v2026.02.14
 
 	Display HT siblings in cpu# order.
 	Add Module-ID column.
 	Print Core-ID and APIC-ID in hex.
 	Fix misc bugs.
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Merge tag 'power-utilities-2026.04.25' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux

Pull power utility updates from Len Brown:
 "x86_energy_perf_policy:
   - Initial SoC Slider support

 turbostat:
   - Display HT siblings in cpu# order
   - Add Module-ID column
   - Print Core-ID and APIC-ID in hex
   - Fix misc bugs"

* tag 'power-utilities-2026.04.25' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux:
  tools/power x86_energy_perf_policy: Version 2026.04.25
  tools/power x86_energy_perf_policy.8: Document SoC Slider Options
  tools/power x86_energy_perf_policy: Enhances SoC Slider related checks
  tools/power turbostat: v2026.04.21
  tools/power turbostat: Process HT siblings in CPU order
  tools/power turbostat: Show module_id column
  tools/power turbostat: Print core_id and apic_id in hex
  tools/power turbostat: Cleanup print helper functions
  tools/power turbostat: Fix --cpu-set 1 regression on HT systems
  tools/power turbostat: Fix --cpu-set 0 regression on HT systems
  tools/power turbostat: Fix unrecognized option '-P'
  tools/power turbostat: Fix AMD RAPL regression on big systems
  tools/power/x86: Add SOC slider and platform profile support
2026-04-25 16:58:34 -07:00
Linus Torvalds
211d593314 RTC for 7.1
Subsystem:
  - add data_race() in rtc_dev_poll()
 
 Drivers:
  - remove i2c_match_id usage
  - abx80x: Disable alarm feature if no interrupt attached
  - ti-k3: support resuming from IO DDR low power mode
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Merge tag 'rtc-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux

Pull RTC updates from Alexandre Belloni:
 "Subsystem:
   - add data_race() in rtc_dev_poll()

  Drivers:
   - remove i2c_match_id usage
   - abx80x: Disable alarm feature if no interrupt attached
   - ti-k3: support resuming from IO DDR low power mode"

* tag 'rtc-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux:
  rtc: abx80x: Disable alarm feature if no interrupt attached
  rtc: ntxec: fix OF node reference imbalance
  rtc: pic32: allow driver to be compiled with COMPILE_TEST
  rtc: ti-k3: Add support to resume from IO DDR low power mode
  rtc: cmos: Use platform_get_irq_optional() in cmos_platform_probe()
  dt-bindings: rtc: add olpc,xo1-rtc to trivial-rtc
  dt-bindings: rtc: sc2731: Add compatible for SC2730
  rtc: add data_race() in rtc_dev_poll()
  rtc: armada38x: zalloc + calloc to single allocation
  dt-bindings: rtc: isl12026: convert to YAML schema
  dt-bindings: rtc: microcrystal,rv3028: Allow to specify vdd-supply
  rtc: max77686: convert to i2c_new_ancillary_device
  dt-bindings: rtc: mpfs-rtc: permit resets
  rtc: rx8025: Remove use of i2c_match_id()
  rtc: rv8803: Remove use of i2c_match_id()
  rtc: rs5c372: Remove use of i2c_match_id()
  rtc: pcf2127: Remove use of i2c_match_id()
  rtc: m41t80: Remove use of i2c_match_id()
  rtc: abx80x: Remove use of i2c_match_id()
2026-04-25 16:39:03 -07:00
Linus Torvalds
1d9f1b5e43 Here are the accumulated fixes for 7.1-rc1 and a single structural worth of
mentioning separately: Rafael's commit converting tpm_crb from ACPI driver
 to a platform driver. Starting from this release cycle, the branch with TPM
 changes mirrored to next is 'for-next-tpm', and patches for keys have their
 own separate 'for-next-keys' branch.
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Merge tag 'for-next-tpm-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd

Pull tpm updates from Jarkko Sakkinen:
 "Here are the accumulated fixes for 7.1-rc1 and a single structural
  change worth mentioning separately: Rafael's commit converting tpm_crb
  from ACPI driver to a platform driver"

* tag 'for-next-tpm-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd:
  tpm: tpm_tis: stop transmit if retries are exhausted
  tpm: tpm_tis: add error logging for data transfer
  tpm: avoid -Wunused-but-set-variable
  tpm: Use kfree_sensitive() to free auth session in tpm_dev_release()
  tpm2-sessions: Fix missing tpm_buf_destroy() in tpm2_read_public()
  tpm: Fix auth session leak in tpm2_get_random() error path
  tpm: i2c: atmel: fix block comment formatting
  tpm_crb: Convert ACPI driver to a platform one
  tpm: Make tcpci_pm_ops variable static const
2026-04-25 16:20:52 -07:00
Len Brown
6112da1ea4 Merge branches 'turbostat' and 'x86_energy_perf_policy' into power-utilities 2026-04-25 14:26:32 -04:00