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dt-bindings: cache: qcom,llcc: Document Hawi SoC
Add documentation for the Last Level Cache Controller (LLCC) bindings to support Hawi SoC where the System Cache Table (SCT) is programmed by firmware outside of Linux. Introduce a property that specifies the base address of the shared memory region from which the driver should read SCT descriptors provided by firmware. Signed-off-by: Francisco Munoz Ruiz <francisco.ruiz@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260407-external_llcc_changes2set-v2-1-b5017ce2020b@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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@ -21,6 +21,7 @@ properties:
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compatible:
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enum:
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- qcom,glymur-llcc
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- qcom,hawi-llcc
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- qcom,ipq5424-llcc
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- qcom,kaanapali-llcc
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- qcom,qcs615-llcc
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@ -58,6 +59,11 @@ properties:
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interrupts:
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maxItems: 1
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memory-region:
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maxItems: 1
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description: handle to a reserved-memory node used for firmware-populated
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SLC/SCT shared memory.
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nvmem-cells:
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items:
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- description: Reference to an nvmem node for multi channel DDR
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@ -320,6 +326,7 @@ allOf:
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contains:
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enum:
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- qcom,kaanapali-llcc
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- qcom,hawi-llcc
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- qcom,sm8450-llcc
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- qcom,sm8550-llcc
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- qcom,sm8650-llcc
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@ -342,6 +349,18 @@ allOf:
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- const: llcc3_base
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- const: llcc_broadcast_base
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- const: llcc_broadcast_and_base
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,hawi-llcc
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then:
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required:
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- memory-region
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else:
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properties:
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memory-region: false
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additionalProperties: false
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