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Author SHA1 Message Date
Linus Torvalds
4ee64205ff We've finally gotten rid of the struct clk_ops::round_rate() code after months 
of effort from Brian Masney. Now the only option is to use determine_rate(),
 which is good because that takes a struct argument instead of just a couple
 unsigned longs, allowing us to easily modify the way we determine and set rates
 in the clk tree.
 
 Beyond that core framework change we've got the typical pile of new SoC clk
 driver additions, fixes for clk data and/or adding missing clks because the
 consumer driver using those clks wasn't ready, etc. The usual suspects are all
 here: Qualcomm, Samsung, Mediatek, and Rockchip along with some newcomers
 making RISC-V SoCs like ESWIN's eic700 and Tenstorrent's Atlantis. The clk
 driver side of this looks pretty normal.
 
 Core:
  - Remove the round_rate() clk op (yay!)
 
 New Drivers:
  - ESWIN eic700 SoC clk support
  - Econet EN751221 SoC clock/reset support
  - Global TCSR, RPMh, and display clock controller support for
    the Qualcomm Eliza platform
  - TCSR, the multiple global, and the RPMh clock controller
    support for the Qualcomm Nord platform
  - GPU clock controller support for Qualcomm SM8750
  - Video and GPU clock controller support for Qualcomm Glymur
  - Global clock controller support for Qualcomm IPQ5210
  - Axis ARTPEC-9: Add new PLL clocks and new drivers for eight clock
    controllers on the SoC
  - ExynosAutov920: Add G3D (GPU) clock controller
  - Clock driver for the Rockchip RV1103B SoC
  - Initial support for the Renesas RZ/G3L (R9A08G046) SoC
  - Clock and reset controllers (e.g. PRCM) in the Tenstorrent Atlantis SoC
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "We've finally gotten rid of the struct clk_ops::round_rate() code
  after months of effort from Brian Masney. Now the only option is to
  use determine_rate(), which is good because that takes a struct
  argument instead of just a couple unsigned longs, allowing us to
  easily modify the way we determine and set rates in the clk tree.

  Beyond that core framework change we've got the typical pile of new
  SoC clk driver additions, fixes for clk data and/or adding missing
  clks because the consumer driver using those clks wasn't ready, etc.
  The usual suspects are all here: Qualcomm, Samsung, Mediatek, and
  Rockchip along with some newcomers making RISC-V SoCs like ESWIN's
  eic700 and Tenstorrent's Atlantis. The clk driver side of this looks
  pretty normal.

  Core:
   - Remove the round_rate() clk op (yay!)

  New Drivers:
   - ESWIN eic700 SoC clk support
   - Econet EN751221 SoC clock/reset support
   - Global TCSR, RPMh, and display clock controller support for the
     Qualcomm Eliza platform
   - TCSR, the multiple global, and the RPMh clock controller support
     for the Qualcomm Nord platform
   - GPU clock controller support for Qualcomm SM8750
   - Video and GPU clock controller support for Qualcomm Glymur
   - Global clock controller support for Qualcomm IPQ5210
   - Axis ARTPEC-9: Add new PLL clocks and new drivers for eight clock
     controllers on the SoC
   - ExynosAutov920: Add G3D (GPU) clock controller
   - Clock driver for the Rockchip RV1103B SoC
   - Initial support for the Renesas RZ/G3L (R9A08G046) SoC
   - Clock and reset controllers (e.g. PRCM) in the Tenstorrent Atlantis SoC"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (132 commits)
  clk: visconti: pll: initialize clk_init_data to zero
  clk: fsl-sai: Add MCLK generation support
  clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()
  dt-bindings: clock: fsl-sai: Document clock-cells = <1> support
  clk: fsl-sai: Add i.MX8M support with 8 byte register offset
  clk: fsl-sai: Sort the headers
  dt-bindings: clock: fsl-sai: Document i.MX8M support
  clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC
  clk: qcom: rpmh: Add support for Nord rpmh clocks
  clk: qcom: Add TCSR clock driver for Nord SoC
  dt-bindings: clock: qcom: Add Nord Global Clock Controller
  dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs
  dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller
  clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON
  clk: qcom: Constify list of critical CBCR registers
  clk: qcom: Constify qcom_cc_driver_data
  clk: qcom: videocc-glymur: Constify qcom_cc_desc
  clk: qcom: Add a driver for SM8750 GPU clocks
  dt-bindings: clock: qcom: Add SM8750 GPU clocks
  clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support
  ...
 2026-04-21 08:33:26 -07:00
Linus Torvalds
d730905bc3 Support for Mobileye EyeQ6Lplus 
Cleanups and fixes
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Merge tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Thomas Bogendoerfer:

 - Support for Mobileye EyeQ6Lplus

 - Cleanups and fixes

* tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits)
  MIPS/mtd: Handle READY GPIO in generic NAND platform data
  MIPS/input: Move RB532 button to GPIO descriptors
  MIPS: validate DT bootargs before appending them
  MIPS: Alchemy: Remove unused forward declaration
  MAINTAINERS: Mobileye: Add EyeQ6Lplus files
  MIPS: config: add eyeq6lplus_defconfig
  MIPS: Add Mobileye EyeQ6Lplus evaluation board dts
  MIPS: Add Mobileye EyeQ6Lplus SoC dtsi
  clk: eyeq: Add Mobileye EyeQ6Lplus OLB
  clk: eyeq: Adjust PLL accuracy computation
  clk: eyeq: Skip post-divisor when computing PLL frequency
  pinctrl: eyeq5: Add Mobileye EyeQ6Lplus OLB
  pinctrl: eyeq5: Use match data
  reset: eyeq: Add Mobileye EyeQ6Lplus OLB
  MIPS: Add Mobileye EyeQ6Lplus support
  dt-bindings: soc: mobileye: Add EyeQ6Lplus OLB
  dt-bindings: mips: Add Mobileye EyeQ6Lplus SoC
  MIPS: dts: loongson64g-package: Switch to Loongson UART driver
  mips: pci-mt7620: rework initialization procedure
  mips: pci-mt7620: add more register init values
  ...
 2026-04-17 08:53:23 -07:00
Stephen Boyd
6b701fde9b
Merge branches 'clk-samsung', 'clk-qcom', 'clk-round', 'clk-sai' and 'clk-cleanup' into clk-next 
* clk-samsung:
  clk: samsung: exynos850: Add APM-to-AP mailbox clock
  dt-bindings: clock: exynos850: Add APM_AP MAILBOX clock
  clk: samsung: Use %pe format to simplify
  clk: samsung: pll: Fix possible truncation in a9fraco recalc rate
  clk: samsung: exynosautov920: add block G3D clock support
  dt-bindings: clock: exynosautov920: add G3D clock definitions
  clk: samsung: gs101: harmonise symbol names (clock arrays)
  clk: samsung: artpec-9: Add initial clock support for ARTPEC-9 SoC
  clk: samsung: Add clock PLL support for ARTPEC-9 SoC
  dt-bindings: clock: Add ARTPEC-9 clock controller

* clk-qcom: (67 commits)
  clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC
  clk: qcom: rpmh: Add support for Nord rpmh clocks
  clk: qcom: Add TCSR clock driver for Nord SoC
  dt-bindings: clock: qcom: Add Nord Global Clock Controller
  dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs
  dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller
  clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON
  clk: qcom: Constify list of critical CBCR registers
  clk: qcom: Constify qcom_cc_driver_data
  clk: qcom: videocc-glymur: Constify qcom_cc_desc
  clk: qcom: Add a driver for SM8750 GPU clocks
  dt-bindings: clock: qcom: Add SM8750 GPU clocks
  clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support
  dt-bindings: clock: qcom: Add CMN PLL support for IPQ8074
  clk: qcom: ipq-cmn-pll: Add IPQ6018 SoC support
  dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018
  clk: qcom: gdsc: Fix error path on registration of multiple pm subdomains
  dt-bindings: clock: qcom: Add missing power-domains property
  clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock
  clk: qcom: dispcc-sc7180: Add missing MDSS resets
  ...

* clk-round:
  clk: divider: remove divider_round_rate() and divider_round_rate_parent()
  clk: divider: remove divider_ro_round_rate_parent()
  clk: remove round_rate() clk ops
  clk: composite: convert from round_rate() to determine_rate()
  clk: test: remove references to clk_ops.round_rate

* clk-sai:
  clk: fsl-sai: Add MCLK generation support
  clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()
  dt-bindings: clock: fsl-sai: Document clock-cells = <1> support
  clk: fsl-sai: Add i.MX8M support with 8 byte register offset
  clk: fsl-sai: Sort the headers
  dt-bindings: clock: fsl-sai: Document i.MX8M support

* clk-cleanup:
  clk: visconti: pll: initialize clk_init_data to zero
  clk: xgene: Fix mapping leak in xgene_pllclk_init()
  clk: Simplify clk_is_match()
  clk: baikal-t1: Remove not-going-to-be-supported code for Baikal SoC
  clk: mvebu: armada-37xx-periph: fix __iomem casts in structure init
  clk: qoriq: avoid format string warning
 2026-04-16 10:12:43 -07:00
Stephen Boyd
522a83abc3
Merge branches 'clk-tenstorrent', 'clk-rockchip', 'clk-imx' and 'clk-allwinner' into clk-next 
* clk-tenstorrent:
  clk: tenstorrent: Add Atlantis clock controller driver
  reset: tenstorrent: Add reset controller for Atlantis
  dt-bindings: clk: tenstorrent: Add tenstorrent,atlantis-prcm-rcpu

* clk-rockchip:
  clk: rockchip: rk3568: Add PCIe pipe clock gates
  clk: rockchip: Add clock controller for the RV1103B
  dt-bindings: clock: rockchip: Add RV1103B CRU support

* clk-imx:
  clk: imx8mq: Correct the CSI PHY sels
  clk: vf610: Add support for the Ethernet switch clocks
  dt-bindings: clock: vf610: Add definitions for MTIP L2 switch
  dt-bindings: clock: vf610: Drop VF610_CLK_END define
  clk: vf610: Move VF610_CLK_END define to clk-vf610 driver
  clk: imx: imx8-acm: fix flags for acm clocks
  clk: imx: imx6q: Fix device node reference leak in of_assigned_ldb_sels()
  clk: imx: imx6q: Fix device node reference leak in pll6_bypassed()
  clk: imx: fracn-gppll: Add 477.4MHz support
  clk: imx: fracn-gppll: Add 333.333333 MHz support
  clk: imx: pll14xx: Use unsigned format specifier
  dt-bindings: clock: imx6q[ul]-clock: add optional clock enet[1]_ref_pad

* clk-allwinner:
  clk: sunxi-ng: sun55i-a523-r: Add missing r-spi module clock
 2026-04-16 10:12:33 -07:00
Stephen Boyd
699646e684
Merge branches 'clk-fixes', 'clk-renesas', 'clk-rpi', 'clk-eswin' and 'clk-mediatek' into clk-next 
- ESWIN eic700 SoC clk support
 - Econet EN751221 SoC clock/reset support

* clk-fixes:
  clk: spacemit: ccu_mix: fix inverted condition in ccu_mix_trigger_fc()
  clk: microchip: mpfs-ccc: fix out of bounds access during output registration
  clk: qcom: dispcc-sm8450: use RCG2 ops for DPTX1 AUX clock source

* clk-renesas:
  clk: renesas: Add support for RZ/G3L SoC
  dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC
  clk: renesas: rzg2l: Re-enable critical module clocks during resume
  clk: renesas: rzg2l: Add rzg2l_mod_clock_init_mstop_helper()
  clk: renesas: rzg2l: Add helper for mod clock enable/disable
  clk: renesas: r9a0{7g04[34],8g045}: Add critical reset entries
  clk: renesas: rzg2l: Add support for critical resets
  clk: renesas: r9a09g056: Remove entries for WDT{0,2,3}
  clk: renesas: r9a06g032: Enable watchdog reset sources
  clk: renesas: cpg-mssr: Use struct_size() helper
  clk: renesas: r9a09g047: Add PCIe clocks and reset
  clk: renesas: r9a09g057: Add PCIe clocks and reset
  clk: renesas: r9a09g056: Add PCIe clocks and reset
  clk: renesas: r9a09g047: Add entries for the RSPIs
  clk: renesas: r9a09g056: Add clock and reset entries for RTC
  clk: renesas: r9a09g057: Remove entries for WDT{0,2,3}
  clk: renesas: r9a09g056: Fix ordering of module clocks array
  clk: renesas: r9a09g057: Fix ordering of module clocks array

* clk-rpi:
  clk: bcm: rpi: Manage clock rate in prepare/unprepare callbacks

* clk-eswin:
  MAINTAINERS: Add entry for ESWIN EIC7700 clock driver
  clk: eswin: Add eic7700 clock driver
  clk: divider: Add devm_clk_hw_register_divider_parent_data
  dt-bindings: clock: eswin: Documentation for eic7700 SoC

* clk-mediatek:
  clk: airoha: Add econet EN751221 clock/reset support to en7523-scu
  dt-bindings: clock, reset: Add econet EN751221
 2026-04-16 10:07:47 -07:00
Benoît Monin
4434c3896f dt-bindings: soc: mobileye: Add EyeQ6Lplus OLB 
The "Other Logic Block" found in the EyeQ6Lplus from Mobileye provides
various functions for the controllers present in the SoC.

The OLB produces 22 clocks derived from its input, which is connected
to the main oscillator of the SoC.

It provides reset signals via two reset domains.

It also controls 32 pins to be either a GPIO or an alternate function.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
 2026-04-13 15:31:40 +02:00
Krzysztof Kozlowski
4177ec9d58 Support for the RV1103B SoC and the Onion Omega4 board using it. 
While the RV1103B only got a B-extension to its name, the SoC internals
 were reworked heavily. So likely it's mainly pin compatible to the
 non-B variant.
 
 The dt-binding for the RV1103B clock driver is shared with the clock-
 driver branch going into the clock-tree.
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Merge tag 'v7.1-rockchip-dts32-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt

Support for the RV1103B SoC and the Onion Omega4 board using it.
While the RV1103B only got a B-extension to its name, the SoC internals
were reworked heavily. So likely it's mainly pin compatible to the
non-B variant.

The dt-binding for the RV1103B clock driver is shared with the clock-
driver branch going into the clock-tree.

* tag 'v7.1-rockchip-dts32-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: Add Onion Omega4 Evaluation Board
  dt-bindings: arm: rockchip: Add Omega4 Evaluation board
  ARM: dts: rockchip: Add support for RV1103B
  dt-bindings: soc: rockchip: grf: Add RV1103B compatibles
  dt-bindings: clock: rockchip: Add RV1103B CRU support

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
 2026-04-11 10:09:33 +02:00
Taniya Das
06498d59bb dt-bindings: clock: qcom: Add Nord Global Clock Controller 
Add device tree bindings for the global clock controller on Qualcomm
Nord platform. The global clock controller on Nord SoC is divided into
multiple clock controllers (GCC,SE_GCC,NE_GCC and NW_GCC). Add each of
the bindings to define the clock controllers.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260403-nord-clks-v1-3-018af14979fd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-04-08 20:57:01 -05:00
Taniya Das
31fcf6995e dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller 
The Nord SoC TCSR block provides CLKREF clocks for DP, PCIe, UFS, SGMII
and USB.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
[Shawn: Use compatible qcom,nord-tcsrcc rather than qcom,nord-tcsr]
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260403-nord-clks-v1-1-018af14979fd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-04-08 20:57:01 -05:00
Arnd Bergmann
8366b60cbe Qualcomm Arm64 DeviceTree updates for v7.1 
Introduce the Eliza, Glymur, Mahua, and IPQ5210 Qualcomm SoCs.
 
 Introduce the Redmi 4A, Redmi Go, Arduino Monza (VENTUNO Q), Redmi Note
 8T, Purwa EVK, ECS Liva QCS710, additional variants of the DB820c,
 Ayaneo Pocket S2, Thundercomm AI Mini PC G1, Samsung Galaxy Core Prime
 LTE Verizon Wireless, Wiko Pulp 4G, the Purwa-variant of ASUS Vivobook
 S15, the Eliza MTP, and the Glymur and Mahua CRDs.
 
 Introduce UFS support and flatten the DWC3 node on Hamoa. Enable UFS,
 SDC, DisplayPort audio playback, and an EL2 overlay for the Hamoa IoT
 EVK. Enable DisplayPort audio on the Hamoa CRD and add HDMI support on
 the ASUS Zenbook A14. Reduce the duplication of thermal sensors across
 Purwa and Hamoa.
 
 Add the QPIC SPI NAND controller on IPQ5332 and IPQ9574. Describe and
 enable the eMMC controller on IPQ9574.
 
 Add display, audio/compute remoteprocs, QUP devices, thermal sensors,
 display, and CoreSight on the Kaanapali platform. Enable audio, compute
 display, PMIC, Bluetooth, and WiFi on the MTP. Describe PMIC, audio and
 compute remoteprocs on QRD.
 
 Add role-switching support for the tertiary USB controller on Lemans.
 Enable the tertiary USB controller and the GPIO expander on the Lemans
 EVK, and add an overlay for the IFP Mezzanine.
 
 Add UFS, camera control interface, audio GPR, and FastRPC support on
 Milos. Enable UFS, camera EEPROMs, and hall effect sensor on the
 Fairphone FP6.
 
 Add camera control interface and fix a variety of things on the Monaco
 platform, add missing FastRPC compute banks. Add eMMC support, describe
 the DisplayPort bridge and GPIO expander on the Monaco EVK. Add overlay
 for EVK camera and the IFP mezzanine.
 
 Add touchscreen to the Xiaomi Redmi 4A, 5A, and Go, and fix the board-id
 on the 4A.
 
 Add the ambient light and proximity sensor on the Asus ZenFone 2
 Laser/Selfie.
 
 On Kodiak-based boards, enable the ethernet and USB Type-A ports on the
 Rb3Gen2, correct the LT9611 routing on the RubikPi3, add Bluetooth on
 the IDP, and add front camera support on the Fairphone FP5.
 Introduce an overlay for the Rb3Gen2 Industrial Mezzanine.
 
 Describe DSI on the Monaco SoC and enable Bluetooth, WiFi and DSI/DP
 bridge on the Ride board.
 
 Describe the WiFi/BT combo chip properly on the QRB2210 RB1 and QRB4210.
 The describe the DSI/DP bringde on the Arduino UnoQ.
 
 01022af2d2 arm64: dts: qcom: sc7280-chrome-common: disable Venus
 
 Introduce DSI display support on SC8280XP.
 
 Add LLCC on SDM670 and another SPI controller on SDM630.
 
 Properly describe the WiFi/BT chip on a variety of SDM845-based
 devices. Introduce the "alert slider" on the OnePlus 6 and OnePlus 6T
 devices.
 
 Introduce the PRNG, describe the debug UART, and add the MDSS core reset
 on SM6125. Enable the debug UART and fix various issues on the Xiaomi
 Redmi Note 8. Describe the touchscreen on the Xiaomi Mi A3.
 
 Properly describe the WiFi/BT combo chip in SM8150 HDK.
 
 Improve the EAS properties on SM8550, in addition to various other
 fixes. Introduce a new overlay for the HDK display card.
 
 Introduce various smaller fixes across SM8450 and SM8650.
 
 Add display support on SM8750 and enable DSI and DisplayPort on the MTP.
 Also add tsens and thermal-zones.
 
 Add ETR devices, flatten the USB controller node, and mark USB
 controllers as wakeup-capable devices, on Talos.
 
 Properly describe the IPA IMEM slice on a variety of platforms.
 
 Drop redundant non-controllable regulator definitions from a variety of
 boards.
 
 Drop redundant VSYNC pin state definition from various platforms.
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Merge tag 'qcom-arm64-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Qualcomm Arm64 DeviceTree updates for v7.1

Introduce the Eliza, Glymur, Mahua, and IPQ5210 Qualcomm SoCs.

Introduce the Redmi 4A, Redmi Go, Arduino Monza (VENTUNO Q), Redmi Note
8T, Purwa EVK, ECS Liva QCS710, additional variants of the DB820c,
Ayaneo Pocket S2, Thundercomm AI Mini PC G1, Samsung Galaxy Core Prime
LTE Verizon Wireless, Wiko Pulp 4G, the Purwa-variant of ASUS Vivobook
S15, the Eliza MTP, and the Glymur and Mahua CRDs.

Introduce UFS support and flatten the DWC3 node on Hamoa. Enable UFS,
SDC, DisplayPort audio playback, and an EL2 overlay for the Hamoa IoT
EVK. Enable DisplayPort audio on the Hamoa CRD and add HDMI support on
the ASUS Zenbook A14. Reduce the duplication of thermal sensors across
Purwa and Hamoa.

Add the QPIC SPI NAND controller on IPQ5332 and IPQ9574. Describe and
enable the eMMC controller on IPQ9574.

Add display, audio/compute remoteprocs, QUP devices, thermal sensors,
display, and CoreSight on the Kaanapali platform. Enable audio, compute
display, PMIC, Bluetooth, and WiFi on the MTP. Describe PMIC, audio and
compute remoteprocs on QRD.

Add role-switching support for the tertiary USB controller on Lemans.
Enable the tertiary USB controller and the GPIO expander on the Lemans
EVK, and add an overlay for the IFP Mezzanine.

Add UFS, camera control interface, audio GPR, and FastRPC support on
Milos. Enable UFS, camera EEPROMs, and hall effect sensor on the
Fairphone FP6.

Add camera control interface and fix a variety of things on the Monaco
platform, add missing FastRPC compute banks. Add eMMC support, describe
the DisplayPort bridge and GPIO expander on the Monaco EVK. Add overlay
for EVK camera and the IFP mezzanine.

Add touchscreen to the Xiaomi Redmi 4A, 5A, and Go, and fix the board-id
on the 4A.

Add the ambient light and proximity sensor on the Asus ZenFone 2
Laser/Selfie.

On Kodiak-based boards, enable the ethernet and USB Type-A ports on the
Rb3Gen2, correct the LT9611 routing on the RubikPi3, add Bluetooth on
the IDP, and add front camera support on the Fairphone FP5.
Introduce an overlay for the Rb3Gen2 Industrial Mezzanine.

Describe DSI on the Monaco SoC and enable Bluetooth, WiFi and DSI/DP
bridge on the Ride board.

Describe the WiFi/BT combo chip properly on the QRB2210 RB1 and QRB4210.
The describe the DSI/DP bringde on the Arduino UnoQ.

01022af2d2 arm64: dts: qcom: sc7280-chrome-common: disable Venus

Introduce DSI display support on SC8280XP.

Add LLCC on SDM670 and another SPI controller on SDM630.

Properly describe the WiFi/BT chip on a variety of SDM845-based
devices. Introduce the "alert slider" on the OnePlus 6 and OnePlus 6T
devices.

Introduce the PRNG, describe the debug UART, and add the MDSS core reset
on SM6125. Enable the debug UART and fix various issues on the Xiaomi
Redmi Note 8. Describe the touchscreen on the Xiaomi Mi A3.

Properly describe the WiFi/BT combo chip in SM8150 HDK.

Improve the EAS properties on SM8550, in addition to various other
fixes. Introduce a new overlay for the HDK display card.

Introduce various smaller fixes across SM8450 and SM8650.

Add display support on SM8750 and enable DSI and DisplayPort on the MTP.
Also add tsens and thermal-zones.

Add ETR devices, flatten the USB controller node, and mark USB
controllers as wakeup-capable devices, on Talos.

Properly describe the IPA IMEM slice on a variety of platforms.

Drop redundant non-controllable regulator definitions from a variety of
boards.

Drop redundant VSYNC pin state definition from various platforms.

* tag 'qcom-arm64-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (254 commits)
  arm64: dts: qcom: sm8250: Add missing CPU7 3.09GHz OPP
  arm64: dts: qcom: sm8550-hdk: add support for the Display Card overlay
  arm64: dts: qcom: msm8916-samsung-coreprimeltevzw: add device tree
  dt-bindings: qcom: Document samsung,coreprimeltevzw
  arm64: dts: qcom: msm8916-samsung-fortuna: Move SM5504 from rossa and refactor MUIC
  arm64: dts: qcom: sdm670: add llcc
  arm64: dts: qcom: qcm6490-fairphone-fp5: Add front camera support
  arm64: dts: qcom: qcm6490-fairphone-fp5: Sort pinctrl nodes by pins
  arm64: dts: qcom: milos-fairphone-fp6: Add camera EEPROMs on CCI busses
  arm64: dts: qcom: milos: Add CCI busses
  arm64: dts: qcom: purwa-iot-evk: Enable UFS
  arm64: dts: qcom: eliza: Add thermal sensors
  arm64: dts: qcom: sc8280xp: Add dsi nodes on SC8280XP
  arm64: dts: qcom: sdm845-oneplus: Describe Wi-Fi/BT properly
  arm64: dts: qcom: sdm845-google: Describe Wi-Fi/BT properly
  arm64: dts: qcom: drop redundant zap-shader memory-region
  arm64: dts: qcom: fix remaining gpu_zap_shader labels
  arm64: dts: qcom: msm8996: fix indentation in sdhc2 node
  arm64: dts: qcom: monaco-evk: enable UART6 for robot expansion board
  arm64: dts: qcom: lemans-evk: enable UART0 for robot expansion board
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2026-04-03 00:08:34 +02:00
Arnd Bergmann
cce3c4db86 Renesas DTS updates for v7.1 (take two) 
- Add DT overlay support for the MayQueen PixPaper display on the
     Yuridenki-Shokai Kakip board,
   - Add Ethernet PHY interrupt support for the RZ/T2H and RZ/N2H EVK
     boards,
   - Add SPI and PCIe support for the RZ/G3E SoC and the RZ/G3E SMARC EVK
     board,
   - Add DT overlay support for the WaveShare 13.3" 1920x1080 DSI
     Capacitive Touch Display and the Olimex MIPI-HDMI adapter on the
     Retronix Sparrow Hawk board,
   - Drop several superfluous C22 Ethernet PHY compatible strings,
   - Remove WDT nodes meant for other CPU cores on the RZ/V2N SoC,
   - Remove unavailable LVDS panel support for the Beacon ReneSoM base
     board,
   - Add initial support for the RZ/G3L (R9A08G046) SoC, and the RZ/G3L
     SMARC SoM and EVK boards,
   - Add Versa3 clock generator support for the RZ/V2H EVK development
     board,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-dts-for-v7.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v7.1 (take two)

  - Add DT overlay support for the MayQueen PixPaper display on the
    Yuridenki-Shokai Kakip board,
  - Add Ethernet PHY interrupt support for the RZ/T2H and RZ/N2H EVK
    boards,
  - Add SPI and PCIe support for the RZ/G3E SoC and the RZ/G3E SMARC EVK
    board,
  - Add DT overlay support for the WaveShare 13.3" 1920x1080 DSI
    Capacitive Touch Display and the Olimex MIPI-HDMI adapter on the
    Retronix Sparrow Hawk board,
  - Drop several superfluous C22 Ethernet PHY compatible strings,
  - Remove WDT nodes meant for other CPU cores on the RZ/V2N SoC,
  - Remove unavailable LVDS panel support for the Beacon ReneSoM base
    board,
  - Add initial support for the RZ/G3L (R9A08G046) SoC, and the RZ/G3L
    SMARC SoM and EVK boards,
  - Add Versa3 clock generator support for the RZ/V2H EVK development
    board,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v7.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (29 commits)
  ARM: dts: renesas: Drop KSZ8041 PHY C22 compatible strings
  ARM: dts: renesas: rza2mevb: Drop RTL8201F PHY C22 compatible string
  ARM: dts: renesas: r8a7742-iwg21d-q7-dbcm-ca: Drop KSZ8081 PHY C22 compatible string
  arm64: dts: renesas: Add initial device tree for RZ/G3L SMARC EVK board
  arm64: dts: renesas: renesas-smarc2: Move usb3 nodes to board DTS
  arm64: dts: renesas: Add initial support for RZ/G3L SMARC SoM
  arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC
  arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add versa3 clock generator node
  dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC
  arm64: dts: renesas: beacon-renesom: Remove LVDS Panel
  ARM: dts: r9a06g032: Add #address-cells to the GIC node
  arm64: dts: renesas: r9a09g056: Remove wdt{0,2,3} nodes
  arm64: dts: renesas: sparrow-hawk: Add overlay for Olimex MIPI-HDMI adapter
  arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe
  arm64: dts: renesas: r9a09g047e57-smarc-som: Add PCIe reference clock
  arm64: dts: renesas: r9a09g047: Add PCIe node
  arm64: dts: renesas: Fix KSZ9131 PHY bogus txdv-skew-psec properties
  arm64: dts: renesas: Drop KSZ9131 PHY C22 compatible strings
  arm64: dts: renesas: Drop RTL8211F PHY C22 compatible strings
  arm64: dts: renesas: Drop RTL8211E PHY C22 compatible strings
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2026-04-01 19:20:18 +02:00
Konrad Dybcio
4aeadf8a18 dt-bindings: clock: qcom: Add SM8750 GPU clocks 
The SM8750 features a "traditional" GPU_CC block, much of which is
controlled through the GMU microcontroller. GPU_CC block requires the MX
and CX rail control and thus add the corresponding power-domains and
require-opps. Additionally, there's an separate GX_CC block, where
the GX GDSC is moved.

Update the bindings to accommodate for SM8750 SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260305-gpucc_sm8750_v2-v5-1-78292b40b053@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-30 09:08:53 -05:00
John Crispin
7156c65030 dt-bindings: clock: qcom: Add CMN PLL support for IPQ8074 
The CMN PLL block in the IPQ8074 SoC takes 48 MHz as the reference
input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and
bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking
subsystem.

Add the related compatible for IPQ8074 to the ipq9574-cmn-pll
generic schema.

Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311183942.10134-4-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-30 09:02:12 -05:00
John Crispin
a57666004f dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018 
The CMN PLL block in the IPQ6018 SoC takes 48 MHz as the reference
input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and
bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking
subsystem.

Add the related compatible for IPQ6018 to the ipq9574-cmn-pll
generic schema.

Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311183942.10134-2-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-30 09:02:11 -05:00
Biju Das
b822fb8250 dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC 
Document the device tree bindings for the Renesas RZ/G3L SoC Clock Pulse
Generator (CPG). RZ/G3L CPG is similar to RZ/G2L CPG but has 5 clocks
compared to 1 clock on other SoCs.

Also define RZ/G3L (R9A08G046) Clock Pulse Generator Core Clocks, as
listed in section 4.4.4.1 ("Block Diagram of the Clock System"), module
clock outputs, as listed in section 4.4.2 ("Clock List r1.00") and add
Reset definitions referring to registers CPG_RST_* in Section 4.4.3
("Register") of the RZ/G3L Hardware User's Manual (Rev.1.00 Oct, 2025).

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260324114329.268249-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2026-03-26 19:44:48 +01:00
Bjorn Andersson
4d059454d3 Merge branch '20260318-ipq5210_boot_to_shell-v2-1-a87e27c37070@oss.qualcomm.com' into HEAD 
Merge the IPQ5210 global clock controller DeviceTree binding, in order
to gain access to the constants.
 2026-03-26 09:40:57 -05:00
Bjorn Andersson
c10e71b0b7 Merge branch '20260311-eliza-clocks-v6-1-453c4cf657a2@oss.qualcomm.com' into HEAD 
Merge Eliza Global, RPMH, and TCSR clock controller bindings from topic
branch, in order to gain access to the clock defines.
 2026-03-26 09:40:36 -05:00
Caleb James DeLisle
35af99f748
dt-bindings: clock, reset: Add econet EN751221 
Add clock and reset bindings for EN751221 as well as a "chip-scu" which is
an additional regmap that is used by the clock driver as well as others.
This split of the SCU across two register areas is the same as the Airoha
AN758x family.

Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2026-03-24 21:55:41 -07:00
Xuyang Dong
1fb8313260
dt-bindings: clock: eswin: Documentation for eic7700 SoC 
Add device tree binding documentation for the ESWIN eic7700
clock controller module.

Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Troy Mitchell <troy.mitchell@linux.dev>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com> # ebc77
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2026-03-24 19:11:25 -07:00
Krzysztof Kozlowski
495920b5d5 Merge branch 'for-v7.1/dt-bindings-clk' into next/clk 2026-03-24 13:43:09 +01:00
Alexey Klimov
bf9462c827 dt-bindings: clock: exynos850: Add APM_AP MAILBOX clock 
Add a constant for APM-to-AP mailbox clock. This clock is needed
to access this mailbox registers.

Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
Link: https://patch.msgid.link/20260320-exynos850-ap2apm-mailbox-v1-1-983eb3f296fc@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
 2026-03-24 13:42:23 +01:00
Bjorn Andersson
2064d21768 Merge branch '20260120-topic-7180_dispcc_bcr-v1-1-0b1b442156c3@oss.qualcomm.com' into clk-for-7.1 
Merge the addition of reset constants to the SC7180 display clock
controller through a topic branch, in order to make them available to
the DeviceTree branch as well.
 2026-03-23 22:16:44 -05:00
Konrad Dybcio
fc6e29d428 dt-bindings: clock: qcom,dispcc-sc7180: Define MDSS resets 
The MDSS resets have so far been left undescribed. Fix that.

Fixes: 75616da712 ("dt-bindings: clock: Introduce QCOM sc7180 display clock bindings")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Tested-by: Val Packett <val@packett.cool> # sc7180-ecs-liva-qc710
Link: https://lore.kernel.org/r/20260120-topic-7180_dispcc_bcr-v1-1-0b1b442156c3@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-23 22:16:35 -05:00
Andy Shevchenko
5d6c477687
clk: baikal-t1: Remove not-going-to-be-supported code for Baikal SoC 
As noticed in the discussion [1] the Baikal SoC and platforms
are not going to be finalized, hence remove stale code.

Reviewed-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/lkml/22b92ddf-6321-41b5-8073-f9c7064d3432@infradead.org/ [1]
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2026-03-23 17:17:59 -07:00
Bjorn Andersson
7f9ccf3b99 Merge branch '20260319-clk-qcom-dispcc-eliza-v3-1-d1f2b19a6e6b@oss.qualcomm.com' into clk-for-7.1 
Merge the Eliza display clock controller binding through a topic branch,
to allow the constants to be shared with the DeviceTree branch.
 2026-03-23 11:29:06 -05:00
Krzysztof Kozlowski
a4f78912ae dt-bindings: clock: qcom,eliza-dispcc: Add Eliza SoC display CC 
Add bindings for Qualcomm Eliza SoC display clock controller (dispcc),
which is very similar to one in SM8750, except new HDMI-related clocks
and additional clock input from HDMI PHY PLL.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260319-clk-qcom-dispcc-eliza-v3-1-d1f2b19a6e6b@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-23 11:28:52 -05:00
Lukasz Majewski
77f18a1f7d dt-bindings: clock: vf610: Add definitions for MTIP L2 switch 
This patch adds VF610_CLK_ESW and VF610_CLK_ESW_MAC_TAB{0123}
macros definitions for L2 switch.

Those definitions describe clocks for MoreThanIP switch IP block;
the switch itself and the MAC address lookup table clocks.

Signed-off-by: Lukasz Majewski <lukma@nabladev.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://patch.msgid.link/20260129095442.1646748-4-lukma@nabladev.com
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
 2026-03-19 16:15:32 +02:00
Lukasz Majewski
2f4788cca8 dt-bindings: clock: vf610: Drop VF610_CLK_END define 
The VF610_CLK_END should be dropped as it is not part of the ABI.

Signed-off-by: Lukasz Majewski <lukma@nabladev.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://patch.msgid.link/20260129095442.1646748-3-lukma@nabladev.com
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
 2026-03-19 16:15:32 +02:00
Val Packett
76404ffbf0 dt-bindings: clock: qcom,gcc-sc8180x: Add missing GDSCs 
There are 5 more GDSCs that we were ignoring and not putting to sleep,
which are listed in downstream DTS. Add them.

Signed-off-by: Val Packett <val@packett.cool>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260312112321.370983-2-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-18 21:08:51 -05:00
Bjorn Andersson
1279298702 Merge branch '20260318-ipq5210_boot_to_shell-v2-1-a87e27c37070@oss.qualcomm.com' into clk-for-7.1 
Merge the IPQ5210 Global clock controller binding through a topic
branch, to allow the constants to also be merged into the DeviceTree
branch.
 2026-03-18 20:53:02 -05:00
Kathiravan Thirumoorthy
20a107bca2 dt-bindings: clock: add Qualcomm IPQ5210 GCC 
Add binding for the Qualcomm IPQ5210 Global Clock Controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318-ipq5210_boot_to_shell-v2-1-a87e27c37070@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-18 20:52:54 -05:00
Bjorn Andersson
8081dbb031 Merge branch '20260303034847.13870-2-val@packett.cool' into clk-for-7.1 
Merge the definition of MDSS resets for SM6115 and SM6125 to allow them
to be made available in the DeviceTree branch.
 2026-03-11 15:44:31 -05:00
Val Packett
0221b14be8 dt-bindings: clock: qcom,dispcc-sm6125: Define MDSS resets 
Add the missing defines for MDSS resets, which are necessary to reset
the display subsystem in order to avoid issues caused by state left over
from the bootloader.

While here, align comment style with other SoCs.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Val Packett <val@packett.cool>
Link: https://lore.kernel.org/r/20260303034847.13870-3-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-11 15:44:18 -05:00
Val Packett
a5c7b4fc84 dt-bindings: clock: qcom,sm6115-dispcc: Define MDSS resets 
Add the missing defines for MDSS resets, which are necessary to reset
the display subsystem in order to avoid issues caused by state left over
from the bootloader.

While here, align comment style with other SoCs.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Val Packett <val@packett.cool>
Link: https://lore.kernel.org/r/20260303034847.13870-2-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-11 15:44:18 -05:00
Bjorn Andersson
b671f2f351 Merge branch '20260311-eliza-clocks-v6-1-453c4cf657a2@oss.qualcomm.com' into clk-for-7.1 
Merge DeviceTree bindings for Eliza global, rpmh, and tcsr clock
controllers through a topic branch, in case we need them in the
DeviceTree branch as well.
 2026-03-11 15:31:22 -05:00
Taniya Das
b7518e0d1c dt-bindings: clock: qcom: Document the Eliza TCSR Clock Controller 
Add bindings documentation for TCSR Clock Controller for Eliza SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311-eliza-clocks-v6-2-453c4cf657a2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-11 15:31:14 -05:00
Taniya Das
8e3a93e7a1 dt-bindings: clock: qcom: document the Eliza Global Clock Controller 
Add bindings documentation for the Global Clock Controller on Qualcomm
Eliza SoC. Reuse the Milos bindings schema since the controller resources
are exactly the same, even though the controllers are incompatible between
them.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311-eliza-clocks-v6-1-453c4cf657a2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-11 15:31:14 -05:00
Anirudh Srinivasan
1227a8f6c3 dt-bindings: clk: tenstorrent: Add tenstorrent,atlantis-prcm-rcpu 
Document bindings for Tenstorrent Atlantis PRCM that manages clocks
and resets. This block is instantiated multiple times in the SoC.
This commit documents the clocks from the RCPU PRCM block.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Drew Fustini <fustini@kernel.org>
 2026-03-09 20:10:26 -07:00
Fabio Estevam
75d627e557 dt-bindings: clock: rockchip: Add RV1103B CRU support 
Add support for the Rockchip RV1103B Clock and Reset Unit (CRU).

The RV1103B CRU is compatible with the existing RV1126B binding.
Add the compatible string to the schema and introduce the
corresponding clock ID definitions.

Signed-off-by: Fabio Estevam <festevam@nabladev.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260210022620.172570-1-festevam@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2026-03-02 12:51:26 +01:00
Raghav Sharma
6e59133281 dt-bindings: clock: exynosautov920: add G3D clock definitions 
Add device tree clock binding definitions for CMU_G3D

Signed-off-by: Raghav Sharma <raghav.s@samsung.com>
Link: https://patch.msgid.link/20260202103555.2089376-2-raghav.s@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
 2026-02-28 15:42:02 +01:00
GyoungBo Min
6974ae5aa2 dt-bindings: clock: Add ARTPEC-9 clock controller 
Add dt-schema for Axis ARTPEC-9 SoC clock controller.

The Clock Management Unit (CMU) has a top-level block CMU_CMU
which generates clocks for other blocks.

Add device-tree binding definitions for following CMU blocks:
- CMU_CMU
- CMU_BUS
- CMU_CORE
- CMU_CPUCL
- CMU_FSYS0
- CMU_FSYS1
- CMU_IMEM
- CMU_PERI

Signed-off-by: GyoungBo Min <mingyoungbo@coasia.com>
Reviewed-by: Kyunghwan Kim <kenkim@coasia.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251029130731.51305-2-ravi.patel@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
 2026-02-24 12:37:44 +01:00
Taniya Das
ed9ca82961 dt-bindings: clock: qcom: Add video clock controller on Glymur SoC 
Add compatible string for Glymur video clock controller and the bindings
for Glymur Qualcomm SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260202-glymur_videocc-v2-2-8f7d8b4d8edd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-02-23 10:42:54 -06:00
Taniya Das
7c3260327f dt-bindings: clock: qcom: Add GCC video axi reset clock for Glymur 
The global clock controller video axi reset clocks are required by
the video SW driver to assert and deassert the clock resets.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260202-glymur_videocc-v2-1-8f7d8b4d8edd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-02-23 10:42:54 -06:00
Taniya Das
4aff230cf2 dt-bindings: clock: qcom: document the Glymur GPU Clock Controller 
Glymur SoC has Qualcomm GX(graphics) clock controller and also the
Graphics clock controller. The GX graphics clock controller helps in the
recovery of the Graphics subsystem.

Add bindings documentation for the Glymur Graphics Clock and Graphics
power domain Controller for Glymur SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20260127-glymur_gpucc-v1-1-547334c81ba2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-02-23 10:39:07 -06:00
Linus Torvalds
13c916af3a Not much changed in the clk framework this time except the clk.h consumer API 
moved the context saving APIs around to fix a build error in certain
 configurations. There was a change to the core framework for
 CLK_OPS_PARENT_ENABLE behavior during registration, but it wrecked existing
 drivers that didn't expect things to be turned off during clk registration so
 it got reverted.
 
 This cycle is really a large collection of new clk drivers, primarily for
 Qualcomm SoCs but also for Amlogic, SpacemiT, Google, and Aspeed. Another big
 change in here is support for automatic hardware clock gating on Samsung SoCs
 where the clks turn on and off when needed. Ideally more vendors move to this
 method for better power savings. The highlights are in the updates section
 below.
 
 Beyond all the new drivers we have a bunch of cleanups like converting drivers
 from divider_round_rate() to divider_determine_rate() and using scoped for each
 OF child loops. Otherwise it's the usual data fixes and plugging reference
 leaks, etc. that's all pretty ordinary but not critical enough to fix until the
 next release.
 
 New Drivers:
  - Qualcomm Kaanapali global, tcsr, rpmh, display, gpu, camera, and video clk
    controllers
  - Qualcomm SM8750 camera clk controllers
  - Qualcomm MSM8940 and SDM439 global clk controllers
  - Google GS101 Display Process Unit (DPU) clk controllers
  - SpacemiT K3 clk controllers
  - Amlogic t7 clk controllers
  - Aspeed AST2700 clk controllers
 
 Updates:
  - Convert clock dividers from round_rate() to determine_rate()
  - Fix sparse warnings, kernel-doc warnings, and plug leaked OF refs
  - Automatic hardware clk gating on Google GS101 SoCs
  - Amlogic s4 video clks
  - CAN-FD clks and resets on Renesas RZ/T2H, RZ/N2H, RZ/V2H, and RZ/V2N
  - Expanded Serial Peripheral Interface (xSPI) clocks and resets on Renesas
    RZ/T21H and RZ/N2H
  - DMAC, interrupt controller (ICU), SPI, and thermal (TSU) clocks and resets
    on Renesas RZ/V2N
  - More serial (RSCI) clocks and resets on Renesas RZ/V2H and RZ/V2N
  - CPU frequency scaling on T-HEAD TH1520
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "Not much changed in the clk framework this time except the clk.h
  consumer API moved the context saving APIs around to fix a build error
  in certain configurations.

  There was a change to the core framework for CLK_OPS_PARENT_ENABLE
  behavior during registration, but it wrecked existing drivers that
  didn't expect things to be turned off during clk registration so it
  got reverted.

  This cycle is really a large collection of new clk drivers, primarily
  for Qualcomm SoCs but also for Amlogic, SpacemiT, Google, and Aspeed.
  Another big change in here is support for automatic hardware clock
  gating on Samsung SoCs where the clks turn on and off when needed.
  Ideally more vendors move to this method for better power savings. The
  highlights are in the updates section below.

  Beyond all the new drivers we have a bunch of cleanups like converting
  drivers from divider_round_rate() to divider_determine_rate() and
  using scoped for each OF child loops. Otherwise it's the usual data
  fixes and plugging reference leaks, etc. that's all pretty ordinary
  but not critical enough to fix until the next release.

  New Drivers:
   - Qualcomm Kaanapali global, tcsr, rpmh, display, gpu, camera, and
     video clk controllers
   - Qualcomm SM8750 camera clk controllers
   - Qualcomm MSM8940 and SDM439 global clk controllers
   - Google GS101 Display Process Unit (DPU) clk controllers
   - SpacemiT K3 clk controllers
   - Amlogic t7 clk controllers
   - Aspeed AST2700 clk controllers

  Updates:
   - Convert clock dividers from round_rate() to determine_rate()
   - Fix sparse warnings, kernel-doc warnings, and plug leaked OF refs
   - Automatic hardware clk gating on Google GS101 SoCs
   - Amlogic s4 video clks
   - CAN-FD clks and resets on Renesas RZ/T2H, RZ/N2H, RZ/V2H, and
     RZ/V2N
   - Expanded Serial Peripheral Interface (xSPI) clocks and resets on
     Renesas RZ/T21H and RZ/N2H
   - DMAC, interrupt controller (ICU), SPI, and thermal (TSU) clocks and
     resets on Renesas RZ/V2N
   - More serial (RSCI) clocks and resets on Renesas RZ/V2H and RZ/V2N
   - CPU frequency scaling on T-HEAD TH1520"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (165 commits)
  clk: aspeed: Add reset for HACE/VIDEO
  dt-bindings: clock: aspeed: Add VIDEO reset definition
  clk: aspeed: add AST2700 clock driver
  MAINTAINERS: Add entry for ASPEED clock drivers.
  clk: aspeed: Move the existing ASPEED clk drivers into aspeed subdirectory.
  Revert "clk: Respect CLK_OPS_PARENT_ENABLE during recalc"
  clk: Disable KUNIT_UML_PCI
  dt-bindings: clk: rs9: Fix DIF pattern match
  clk: rs9: Convert to DEFINE_SIMPLE_DEV_PM_OPS()
  clk: rs9: Reserve 8 struct clk_hw slots for for 9FGV0841
  clk: qcom: sm8750: Constify 'qcom_cc_desc' in SM8750 camcc
  clk: zynqmp: pll: Fix zynqmp_clk_divider_determine_rate kerneldoc
  clk: zynqmp: divider: Fix zynqmp_clk_divider_determine_rate kerneldoc
  clk: mediatek: Fix error handling in runtime PM setup
  clk: mediatek: don't select clk-mt8192 for all ARM64 builds
  clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
  clk: mediatek: Refactor pllfh registration to pass device
  clk: mediatek: Pass device to clk_hw_register for PLLs
  clk: mediatek: Refactor pll registration to pass device
  clk: Respect CLK_OPS_PARENT_ENABLE during recalc
  ...
 2026-02-15 08:18:57 -08:00
Stephen Boyd
5921ae27ea
Merge branches 'clk-aspeed' and 'clk-qcom' into clk-next 
* clk-aspeed:
  clk: aspeed: Add reset for HACE/VIDEO
  dt-bindings: clock: aspeed: Add VIDEO reset definition
  clk: aspeed: add AST2700 clock driver
  MAINTAINERS: Add entry for ASPEED clock drivers.
  clk: aspeed: Move the existing ASPEED clk drivers into aspeed subdirectory.

* clk-qcom: (49 commits)
  clk: qcom: sm8750: Constify 'qcom_cc_desc' in SM8750 camcc
  clk: qcom: gfx3d: add parent to parent request map
  clk: qcom: dispcc-sm7150: Fix dispcc_mdss_pclk1_clk_src
  clk: qcom: dispcc-sdm845: Enable parents for pixel clocks
  clk: qcom: regmap-divider: convert from divider_round_rate() to divider_determine_rate()
  clk: qcom: regmap-divider: convert from divider_ro_round_rate() to divider_ro_determine_rate()
  clk: qcom: alpha-pll: convert from divider_round_rate() to divider_determine_rate()
  clk: qcom: Add support for GPUCC and GXCLK for Kaanapali
  clk: qcom: Add support for VideoCC driver for Kaanapali
  clk: qcom: camcc: Add support for camera clock controller for Kaanapali
  clk: qcom: dispcc: Add support for display clock controller Kaanapali
  clk: qcom: clk-alpha-pll: Add support for controlling Pongo EKO_T PLL
  clk: qcom: clk-alpha-pll: Update the PLL support for cal_l
  clk: qcom: camcc: Add camera clock controller driver for SM8750 SoC
  clk: qcom: clk-alpha-pll: Add support for controlling Rivian PLL
  dt-bindings: clock: qcom: document the Kaanapali GPU Clock Controller
  dt-bindings: clock: qcom: Add Kaanapali video clock controller
  dt-bindings: clock: qcom: Add support for CAMCC for Kaanapali
  dt-bindings: clock: qcom: document Kaanapali DISPCC clock controller
  dt-bindings: clock: qcom: Add camera clock controller for SM8750 SoC
  ...
 2026-02-14 10:23:59 -08:00
Stephen Boyd
b675697d80
Merge branches 'clk-amlogic', 'clk-thead', 'clk-mediatek' and 'clk-samsung' into clk-next 
* clk-amlogic:
  clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro
  clk: meson: g12a: Limit the HDMI PLL OD to /4
  clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs
  clk: amlogic: remove potentially unsafe flags from S4 video clocks
  clk: amlogic: add video-related clocks for S4 SoC
  dt-bindings: clock: add video clock indices for Amlogic S4 SoC
  clk: meson: t7: add t7 clock peripherals controller driver
  clk: meson: t7: add support for the T7 SoC PLL clock
  dt-bindings: clock: add Amlogic T7 peripherals clock controller
  dt-bindings: clock: add Amlogic T7 SCMI clock controller
  dt-bindings: clock: add Amlogic T7 PLL clock controller

* clk-thead:
  clk: thead: th1520-ap: Support CPU frequency scaling
  clk: thead: th1520-ap: Add macro to define multiplexers with flags
  clk: thead: th1520-ap: Support setting PLL rates
  clk: thead: th1520-ap: Add C910 bus clock
  clk: thead: th1520-ap: Poll for PLL lock and wait for stability
  dt-bindings: clock: thead,th1520-clk-ap: Add ID for C910 bus clock

* clk-mediatek:
  Revert "clk: Respect CLK_OPS_PARENT_ENABLE during recalc"
  clk: mediatek: Fix error handling in runtime PM setup
  clk: mediatek: don't select clk-mt8192 for all ARM64 builds
  clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
  clk: mediatek: Refactor pllfh registration to pass device
  clk: mediatek: Pass device to clk_hw_register for PLLs
  clk: mediatek: Refactor pll registration to pass device
  clk: Respect CLK_OPS_PARENT_ENABLE during recalc
  dt-bindings: clock: mediatek,mt7622-pciesys: Remove syscon compatible
  clk: mediatek: Drop __initconst from gates

* clk-samsung:
  clk: samsung: gs101: add support for Display Process Unit (DPU) clocks
  dt-bindings: samsung: exynos-sysreg: add gs101 dpu compatible
  dt-bindings: clock: google,gs101-clock: Add DPU clock management unit
  dt-bindings: clock: google,gs101-clock: fix alphanumeric ordering
  clk: samsung: fix sysreg save/restore when PM is enabled for CMU
  clk: samsung: avoid warning message on legacy Exynos (auto clock gating)
  clk: samsung: gs101: Enable auto_clock_gate mode for each gs101 CMU
  clk: samsung: Implement automatic clock gating mode for CMUs
  dt-bindings: clock: google,gs101-clock: add samsung,sysreg property as required
  clk: samsung: exynosautov920: add clock support
  dt-bindings: clock: exynosautov920: add MFD clock definitions
 2026-02-14 10:23:37 -08:00
Stephen Boyd
16c3c4e288
Merge branches 'clk-renesas', 'clk-cleanup', 'clk-spacemit' and 'clk-tegra' into clk-next 
* clk-renesas: (25 commits)
  dt-bindings: clk: rs9: Fix DIF pattern match
  clk: rs9: Convert to DEFINE_SIMPLE_DEV_PM_OPS()
  clk: rs9: Reserve 8 struct clk_hw slots for for 9FGV0841
  clk: renesas: Add missing log message terminators
  clk: renesas: rzg2l: Remove DSI clock rate restrictions
  clk: renesas: rzv2h: Deassert reset on assert timeout
  clk: renesas: rzg2l: Deassert reset on assert timeout
  clk: renesas: cpg-mssr: Unlock before reset verification
  clk: renesas: r9a09g056: Add entries for CANFD
  clk: renesas: r9a09g057: Add entries for CANFD
  clk: renesas: r9a09g077: Add CANFD clocks
  clk: renesas: cpg-mssr: Handle RZ/T2H register layout in PM callbacks
  dt-bindings: clock: renesas,r9a09g077/87: Add PCLKCAN ID
  clk: renesas: cpg-mssr: Simplify pointer math in cpg_rzt2h_mstp_read()
  clk: renesas: r9a09g056: Add clock and reset entries for TSU
  clk: renesas: r9a09g057: Add entries for RSCIs
  clk: renesas: r9a09g056: Add entries for RSCIs
  clk: renesas: r9a09g056: Add entries for the RSPIs
  clk: renesas: r9a09g056: Add entries for ICU
  clk: renesas: r9a09g056: Add entries for the DMACs
  ...

* clk-cleanup:
  clk: Disable KUNIT_UML_PCI
  clk: zynqmp: pll: Fix zynqmp_clk_divider_determine_rate kerneldoc
  clk: zynqmp: divider: Fix zynqmp_clk_divider_determine_rate kerneldoc
  clk: tegra: tegra124-emc: fix device leak on set_rate()
  clk: Annotate #else and #endif
  clk: Merge prepare and unprepare sections
  clk: Move clk_{save,restore}_context() to COMMON_CLK section
  clk: clk-apple-nco: Add "apple,t8103-nco" compatible
  clk: versatile: impd1: Simplify with scoped for each OF child loop
  clk: scpi: Simplify with scoped for each OF child loop
  clk: lmk04832: Simplify with scoped for each OF child loop

* clk-spacemit:
  clk: spacemit: k3: add the clock tree
  clk: spacemit: k3: extract common header
  clk: spacemit: ccu_pll: add plla type clock
  clk: spacemit: ccu_mix: add inverted enable gate clock
  dt-bindings: soc: spacemit: k3: add clock support
  clk: spacemit: add platform SoC prefix to reset name
  clk: spacemit: extract common ccu functions
  reset: spacemit: fix auxiliary device id
  clk: spacemit: prepare common ccu header
  clk: spacemit: Hide common clock driver from user controller
  clk: spacemit: Respect Kconfig setting when building modules

* clk-tegra:
  clk: tegra30: Add CSI pad clock gates
  clk: tegra: Set CSUS as vi_sensor's gate for Tegra20, Tegra30 and Tegra114
  clk: tegra20: Reparent dsi clock to pll_d_out0
  clk: tegra: tegra124-emc: Simplify with scoped for each OF child loop
  clk: tegra: Adjust callbacks in tegra_clock_pm
  clk: tegra: tegra124-emc: Fix potential memory leak in tegra124_clk_register_emc()
 2026-02-14 10:23:04 -08:00
Linus Torvalds
098b6e44cb Devicetree updates for v7.0: 
DT core:
 - Sync dtc/libfdt with upstream v1.7.2-62-ga26ef6400bd8
 
 - Add a for_each_compatible_node_scoped() loop and convert users in
   cpufreq, dmaengine, clk, cdx, powerpc and Arm
 
 - Simplify of/platform.c with scoped loop helpers
 
 - Add fw_devlink tracking for "mmc-pwrseq"
 
 - Optimize fw_devlink callback code size for pinctrl-N properties
 
 - Replace strcmp_suffix() with strends()
 
 DT bindings:
 - Support building single binding targets
 
 - Convert google,goldfish-fb, cznic,turris-mox-rwtm, ti,prm-inst
 
 - Add bindings for Freescale AVIC, Realtek RTD1xxx system controllers,
   Microchip 25AA010A EEPROM, OnSemi FIN3385, IEI WT61P803 PUZZLE, Delta
   Electronics DPS-800-AB power supply, Infineon IR35221 Digital
   Multi-phase Controller, Infineon PXE1610 Digital Dual Output 6+1
   VR12.5 & VR13 CPU Controller, socionext,uniphier-smpctrl, and
   xlnx,zynqmp-firmware
 
 - Lots of trivial binding fixes to address warnings in DTS files. These
   are mostly for arm64 platforms which is getting closer to be warning
   free. Some public shaming has helped.
 
 - Fix I2C bus node names in examples
 
 - Drop obsolete brcm,vulcan-soc binding
 
 - Drop unreferenced binding headers
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Merge tag 'devicetree-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree updates from Rob Herring:
 "DT core:

   - Sync dtc/libfdt with upstream v1.7.2-62-ga26ef6400bd8

   - Add a for_each_compatible_node_scoped() loop and convert users in
     cpufreq, dmaengine, clk, cdx, powerpc and Arm

   - Simplify of/platform.c with scoped loop helpers

   - Add fw_devlink tracking for "mmc-pwrseq"

   - Optimize fw_devlink callback code size for pinctrl-N properties

   - Replace strcmp_suffix() with strends()

  DT bindings:

   - Support building single binding targets

   - Convert google,goldfish-fb, cznic,turris-mox-rwtm, ti,prm-inst

   - Add bindings for Freescale AVIC, Realtek RTD1xxx system
     controllers, Microchip 25AA010A EEPROM, OnSemi FIN3385, IEI
     WT61P803 PUZZLE, Delta Electronics DPS-800-AB power supply,
     Infineon IR35221 Digital Multi-phase Controller, Infineon PXE1610
     Digital Dual Output 6+1 VR12.5 & VR13 CPU Controller,
     socionext,uniphier-smpctrl, and xlnx,zynqmp-firmware

   - Lots of trivial binding fixes to address warnings in DTS files.
     These are mostly for arm64 platforms which is getting closer to be
     warning free. Some public shaming has helped.

   - Fix I2C bus node names in examples

   - Drop obsolete brcm,vulcan-soc binding

   - Drop unreferenced binding headers"

* tag 'devicetree-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (60 commits)
  dt-bindings: interrupt-controller: Add compatiblie string fsl,imx(1|25|27|31|35)-avic
  dt-bindings: soc: imx: add fsl,aips and fsl,emi compatible strings
  dt-bindings: display: bridge: lt8912b: Drop reset gpio requirement
  dt-bindings: firmware: fsl,scu: Mark multi-channel MU layouts as deprecated
  cpufreq: s5pv210: Simplify with scoped for each OF child loop
  dmaengine: fsl_raid: Simplify with scoped for each OF child loop
  clk: imx: imx31: Simplify with scoped for each OF child loop
  clk: imx: imx27: Simplify with scoped for each OF child loop
  cdx: Use mutex guard to simplify error handling
  cdx: Simplify with scoped for each OF child loop
  powerpc/wii: Simplify with scoped for each OF child loop
  powerpc/fsp2: Simplify with scoped for each OF child loop
  ARM: exynos: Simplify with scoped for each OF child loop
  ARM: at91: Simplify with scoped for each OF child loop
  of: Add for_each_compatible_node_scoped() helper
  dt-bindings: Fix emails with spaces or missing brackets
  scripts/dtc: Update to upstream version v1.7.2-62-ga26ef6400bd8
  dt-bindings: crypto: inside-secure,safexcel: Mandate only ring IRQs
  dt-bindings: crypto: inside-secure,safexcel: Add SoC compatibles
  of: reserved_mem: Fix placement of __free() annotation
  ...
 2026-02-11 18:27:08 -08:00
Jammy Huang
2ad2d0e291
dt-bindings: clock: aspeed: Add VIDEO reset definition 
ASPEED clock controller provides a couple of resets. Add the define of
video to allow referring to it.

Signed-off-by: Jammy Huang <jammy_huang@aspeedtech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2026-02-03 21:37:05 -08:00