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Renesas DTS updates for v7.1 (take two)

Browse Source 
- Add DT overlay support for the MayQueen PixPaper display on the
     Yuridenki-Shokai Kakip board,
   - Add Ethernet PHY interrupt support for the RZ/T2H and RZ/N2H EVK
     boards,
   - Add SPI and PCIe support for the RZ/G3E SoC and the RZ/G3E SMARC EVK
     board,
   - Add DT overlay support for the WaveShare 13.3" 1920x1080 DSI
     Capacitive Touch Display and the Olimex MIPI-HDMI adapter on the
     Retronix Sparrow Hawk board,
   - Drop several superfluous C22 Ethernet PHY compatible strings,
   - Remove WDT nodes meant for other CPU cores on the RZ/V2N SoC,
   - Remove unavailable LVDS panel support for the Beacon ReneSoM base
     board,
   - Add initial support for the RZ/G3L (R9A08G046) SoC, and the RZ/G3L
     SMARC SoM and EVK boards,
   - Add Versa3 clock generator support for the RZ/V2H EVK development
     board,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-dts-for-v7.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v7.1 (take two)

  - Add DT overlay support for the MayQueen PixPaper display on the
    Yuridenki-Shokai Kakip board,
  - Add Ethernet PHY interrupt support for the RZ/T2H and RZ/N2H EVK
    boards,
  - Add SPI and PCIe support for the RZ/G3E SoC and the RZ/G3E SMARC EVK
    board,
  - Add DT overlay support for the WaveShare 13.3" 1920x1080 DSI
    Capacitive Touch Display and the Olimex MIPI-HDMI adapter on the
    Retronix Sparrow Hawk board,
  - Drop several superfluous C22 Ethernet PHY compatible strings,
  - Remove WDT nodes meant for other CPU cores on the RZ/V2N SoC,
  - Remove unavailable LVDS panel support for the Beacon ReneSoM base
    board,
  - Add initial support for the RZ/G3L (R9A08G046) SoC, and the RZ/G3L
    SMARC SoM and EVK boards,
  - Add Versa3 clock generator support for the RZ/V2H EVK development
    board,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v7.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (29 commits)
  ARM: dts: renesas: Drop KSZ8041 PHY C22 compatible strings
  ARM: dts: renesas: rza2mevb: Drop RTL8201F PHY C22 compatible string
  ARM: dts: renesas: r8a7742-iwg21d-q7-dbcm-ca: Drop KSZ8081 PHY C22 compatible string
  arm64: dts: renesas: Add initial device tree for RZ/G3L SMARC EVK board
  arm64: dts: renesas: renesas-smarc2: Move usb3 nodes to board DTS
  arm64: dts: renesas: Add initial support for RZ/G3L SMARC SoM
  arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC
  arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add versa3 clock generator node
  dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC
  arm64: dts: renesas: beacon-renesom: Remove LVDS Panel
  ARM: dts: r9a06g032: Add #address-cells to the GIC node
  arm64: dts: renesas: r9a09g056: Remove wdt{0,2,3} nodes
  arm64: dts: renesas: sparrow-hawk: Add overlay for Olimex MIPI-HDMI adapter
  arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe
  arm64: dts: renesas: r9a09g047e57-smarc-som: Add PCIe reference clock
  arm64: dts: renesas: r9a09g047: Add PCIe node
  arm64: dts: renesas: Fix KSZ9131 PHY bogus txdv-skew-psec properties
  arm64: dts: renesas: Drop KSZ9131 PHY C22 compatible strings
  arm64: dts: renesas: Drop RTL8211F PHY C22 compatible strings
  arm64: dts: renesas: Drop RTL8211E PHY C22 compatible strings
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2026-04-01 19:20:09 +02:00
commit cce3c4db86
41 changed files with 1269 additions and 237 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
View File

@ -28,19 +28,30 @@ properties:
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
- renesas,r9a07g054-cpg # RZ/V2L
- renesas,r9a08g045-cpg # RZ/G3S
- renesas,r9a08g046-cpg # RZ/G3L
- renesas,r9a09g011-cpg # RZ/V2M
reg:
maxItems: 1
clocks:
maxItems: 1
minItems: 1
items:
- description: Clock source to CPG can be either from external clock
input (EXCLK) or crystal oscillator (XIN/XOUT).
- description: ETH0 TXC clock input
- description: ETH0 RXC clock input
- description: ETH1 TXC clock input
- description: ETH1 RXC clock input
clock-names:
description:
Clock source to CPG can be either from external clock input (EXCLK) or
crystal oscillator (XIN/XOUT).
const: extal
minItems: 1
items:
- const: extal
- const: eth0_txc_tx_clk
- const: eth0_rxc_rx_clk
- const: eth1_txc_tx_clk
- const: eth1_rxc_rx_clk
'#clock-cells':
description: |
@ -74,6 +85,25 @@ required:
- '#power-domain-cells'
- '#reset-cells'
allOf:
- if:
properties:
compatible:
contains:
const: renesas,r9a08g046-cpg
then:
properties:
clocks:
minItems: 5
clock-names:
minItems: 5
else:
properties:
clocks:
maxItems: 1
clock-names:
maxItems: 1
additionalProperties: false
examples:

3
arch/arm/boot/dts/renesas/r7s9210-rza2mevb.dts
View File

@ -94,8 +94,7 @@ &ether1 {
renesas,no-ether-link;
phy-handle = <&phy1>;
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id001c.c816",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id001c.c816";
reg = <0>;
};
};

3
arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ca.dts
View File

@ -85,8 +85,7 @@ &ether {
status = "okay";
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1560",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1560";
reg = <1>;
micrel,led-mode = <1>;
};

3
arch/arm/boot/dts/renesas/r8a7743-sk-rzg1m.dts
View File

@ -70,8 +70,7 @@ &ether {
status = "okay";
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1537",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1537";
reg = <1>;
interrupts-extended = <&irqc 0 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;

3
arch/arm/boot/dts/renesas/r8a7745-sk-rzg1e.dts
View File

@ -65,8 +65,7 @@ &ether {
status = "okay";
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1537",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1537";
reg = <1>;
interrupts-extended = <&irqc 8 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;

3
arch/arm/boot/dts/renesas/r8a7790-lager.dts
View File

@ -685,8 +685,7 @@ &ether {
status = "okay";
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1537",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1537";
reg = <1>;
interrupts-extended = <&irqc0 0 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;

3
arch/arm/boot/dts/renesas/r8a7790-stout.dts
View File

@ -208,8 +208,7 @@ &ether {
status = "okay";
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1537",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1537";
reg = <1>;
interrupts-extended = <&irqc0 1 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;

3
arch/arm/boot/dts/renesas/r8a7791-koelsch.dts
View File

@ -676,8 +676,7 @@ &ether {
status = "okay";
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1537",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1537";
reg = <1>;
interrupts-extended = <&irqc0 0 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;

3
arch/arm/boot/dts/renesas/r8a7791-porter.dts
View File

@ -326,8 +326,7 @@ &ether {
status = "okay";
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1537",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1537";
reg = <1>;
interrupts-extended = <&irqc0 0 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;

3
arch/arm/boot/dts/renesas/r8a7793-gose.dts
View File

@ -616,8 +616,7 @@ &ether {
status = "okay";
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1537",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1537";
reg = <1>;
interrupts-extended = <&irqc0 0 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;

3
arch/arm/boot/dts/renesas/r8a7794-alt.dts
View File

@ -378,8 +378,7 @@ &ether {
status = "okay";
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1537",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1537";
reg = <1>;
interrupts-extended = <&irqc0 8 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;

3
arch/arm/boot/dts/renesas/r8a7794-silk.dts
View File

@ -412,8 +412,7 @@ &ether {
status = "okay";
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1537",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1537";
reg = <1>;
interrupts-extended = <&irqc0 8 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;

1
arch/arm/boot/dts/renesas/r9a06g032.dtsi
View File

@ -554,6 +554,7 @@ gic: interrupt-controller@44101000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <0>;
reg = <0x44101000 0x1000>, /* Distributer */
<0x44102000 0x2000>, /* CPU interface */
<0x44104000 0x2000>, /* Virt interface control */

11
arch/arm64/boot/dts/renesas/Makefile
View File

@ -114,12 +114,18 @@ dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-argon40.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtbo
r8a779g3-sparrow-hawk-fan-pwm-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-fan-pwm.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-olimex-dsi-hdmi.dtbo
r8a779g3-sparrow-hawk-olimex-dsi-hdmi-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-olimex-dsi-hdmi.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-olimex-dsi-hdmi.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-5in.dtbo
r8a779g3-sparrow-hawk-rpi-display-2-5in-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-rpi-display-2-5in.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-5in.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-7in.dtbo
r8a779g3-sparrow-hawk-rpi-display-2-7in-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-rpi-display-2-7in.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-7in.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-ws-display-13in.dtbo
r8a779g3-sparrow-hawk-ws-display-13in-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-ws-display-13in.dtbo
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-ws-display-13in.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-white-hawk-single.dtb
r8a779g3-white-hawk-single-ard-audio-da7212-dtbs := r8a779g3-white-hawk-single.dtb white-hawk-ard-audio-da7212.dtbo
@ -179,6 +185,8 @@ dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtbo
r9a08g045s33-smarc-pmod1-type-3a-dtbs := r9a08g045s33-smarc.dtb r9a08g045s33-smarc-pmod1-type-3a.dtbo
dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtb
dtb-$(CONFIG_ARCH_R9A08G046) += r9a08g046l48-smarc.dtb
dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb
@ -202,6 +210,9 @@ dtb-$(CONFIG_ARCH_R9A09G057) += rzv2-evk-cn15-sd.dtbo
r9a09g057h44-rzv2h-evk-cn15-sd-dtbs := r9a09g057h44-rzv2h-evk.dtb rzv2-evk-cn15-sd.dtbo
dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk-cn15-sd.dtb
dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb
dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip-pixpaper.dtbo
r9a09g057h48-kakip-pixpaper-dtbs := r9a09g057h48-kakip.dtb r9a09g057h48-kakip-pixpaper.dtbo
dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip-pixpaper.dtb
dtb-$(CONFIG_ARCH_R9A09G077) += r9a09g077m44-rzt2h-evk.dtb

74
arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
View File

@ -8,15 +8,6 @@
#include <dt-bindings/clock/versaclock.h>
/ {
backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
power-supply = <&reg_lcd>;
enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_HIGH>;
pwms = <&pwm2 0 25000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
backlight_dpi: backlight-dpi {
compatible = "pwm-backlight";
power-supply = <&reg_lcd>;
@ -101,38 +92,6 @@ led3 {
};
};
lvds {
compatible = "panel-lvds";
power-supply = <&reg_lcd_reset>;
width-mm = <223>;
height-mm = <125>;
backlight = <&backlight_lvds>;
data-mapping = "vesa-24";
panel-timing {
/* 800x480@60Hz */
clock-frequency = <30000000>;
hactive = <800>;
vactive = <480>;
hsync-len = <48>;
hfront-porch = <40>;
hback-porch = <40>;
vfront-porch = <13>;
vback-porch = <29>;
vsync-len = <1>;
hsync-active = <1>;
vsync-active = <3>;
de-active = <1>;
pixelclk-active = <0>;
};
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
rgb {
/* Different LCD with compatible timings */
compatible = "rocktech,rk070er9427";
@ -164,16 +123,6 @@ reg_lcd: regulator-lcd {
enable-active-high;
};
reg_lcd_reset: regulator-lcd-reset {
compatible = "regulator-fixed";
regulator-name = "nLCD_RESET";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_lcd>;
};
reg_cam0: regulator-cam0 {
compatible = "regulator-fixed";
regulator-name = "reg_cam0";
@ -480,18 +429,6 @@ gpio_exp1: gpio@70 {
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
&msiof1 {
pinctrl-0 = <&msiof1_pins>;
pinctrl-names = "default";
@ -562,11 +499,6 @@ pwm0_pins: pwm0 {
function = "pwm0";
};
pwm2_pins: pwm2 {
groups = "pwm2_a";
function = "pwm2";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
@ -617,12 +549,6 @@ &pwm0 {
status = "okay";
};
&pwm2 {
pinctrl-0 = <&pwm2_pins>;
pinctrl-names = "default";
status = "okay";
};
&rcar_sound {
pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";

3
arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi
View File

@ -59,8 +59,7 @@ &avb {
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1640";
reg = <0>;
interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;

3
arch/arm64/boot/dts/renesas/cat875.dtsi
View File

@ -22,8 +22,7 @@ &avb {
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id001c.c915",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id001c.c915";
reg = <0>;
interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;

3
arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
View File

@ -24,8 +24,7 @@ &avb {
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id001c.c915",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id001c.c915";
reg = <0>;
interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;

92
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-olimex-dsi-hdmi.dtso Normal file
View File

@ -0,0 +1,92 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Overlay for Olimex MIPI-HDMI adapter connected to J4:DSI
* on R-Car V4H ES3.0 Sparrow Hawk board
*
* Copyright (C) 2026 Scott Murray <scott.murray@konsulko.com>
*/
/dts-v1/;
/plugin/;
&{/} {
hdmi-connector {
compatible = "hdmi-connector";
label = "HDMI1";
type = "a";
ddc-i2c-bus = <&i2c0_mux3>;
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&lt8912b_out>;
};
};
};
reg_vr1: regulator-vr1 {
compatible = "regulator-fixed";
regulator-name = "VR1-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
vin-supply = <&reg_3p3v>;
};
};
&i2c0_mux3 {
#address-cells = <1>;
#size-cells = <0>;
hdmi-bridge@48 {
compatible = "lontium,lt8912b";
reg = <0x48>;
vcchdmipll-supply = <&reg_vr1>;
vcchdmitx-supply = <&reg_vr1>;
vcclvdspll-supply = <&reg_vr1>;
vcclvdstx-supply = <&reg_vr1>;
vccmipirx-supply = <&reg_vr1>;
vccsysclk-supply = <&reg_vr1>;
vdd-supply = <&reg_vr1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_out_in: endpoint {
data-lanes = <1 2>;
remote-endpoint = <&dsi0_out>;
};
};
port@1 {
reg = <1>;
lt8912b_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
};
&dsi0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&hdmi_out_in>;
data-lanes = <1 2>;
};
};
};
};

88
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-ws-display-13in.dtso Normal file
View File

@ -0,0 +1,88 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Overlay for the Waveshare 13.3 MIPI DSI panel connected
* to J4:DSI on R-Car V4H ES3.0 Sparrow Hawk board
*
* Copyright (C) 2025-2026 Marek Vasut <marek.vasut+renesas@mailbox.org>
*/
/dts-v1/;
/plugin/;
&{/} {
panel {
compatible = "waveshare,13.3inch-panel";
power-supply = <&reg_5p0v>;
port {
panel_in: endpoint {
remote-endpoint = <&bridge_out>;
};
};
};
reg_5p0v: regulator-5p0v {
compatible = "regulator-fixed";
regulator-name = "fixed-5.0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
};
&i2c0_mux3 {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@41 {
compatible = "ilitek,ili251x";
reg = <0x41>;
};
bridge@45 {
compatible = "waveshare,dsi2dpi";
reg = <0x45>;
power-supply = <&reg_5p0v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_in: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&dsi0_out>;
};
};
port@1 {
reg = <1>;
bridge_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
};
&dsi0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi0_out: endpoint {
remote-endpoint = <&bridge_in>;
data-lanes = <1 2 3 4>;
};
};
};
};

212
arch/arm64/boot/dts/renesas/r9a08g046.dtsi Normal file
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@ -0,0 +1,212 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G3L SoC
*
* Copyright (C) 2026 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "renesas,r9a08g046";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
};
cpu1: cpu@100 {
compatible = "arm,cortex-a55";
reg = <0x100>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
};
cpu2: cpu@200 {
compatible = "arm,cortex-a55";
reg = <0x200>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
};
cpu3: cpu@300 {
compatible = "arm,cortex-a55";
reg = <0x300>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
};
L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x80000>;
cache-level = <3>;
};
};
eth0_txc_tx_clk: eth0-txc-tx-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
eth0_rxc_rx_clk: eth0-rxc-rx-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
eth1_txc_tx_clk: eth1-txc-tx-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
eth1_rxc_rx_clk: eth1-rxc-rx-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
extal_clk: extal-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
scif0: serial@100ac000 {
compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
reg = <0 0x100ac000 0 0x400>;
interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A08G046_SCIF0_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_SCIF0_RST_SYSTEM_N>;
status = "disabled";
};
i2c0: i2c@100ae000 {
reg = <0 0x100ae000 0 0x400>;
#address-cells = <1>;
#size-cells = <0>;
/* placeholder */
};
canfd: can@100c0000 {
reg = <0 0x100c0000 0 0x20000>;
/* placeholder */
};
cpg: clock-controller@11010000 {
compatible = "renesas,r9a08g046-cpg";
reg = <0 0x11010000 0 0x10000>;
clocks = <&extal_clk>,
<&eth0_txc_tx_clk>, <&eth0_rxc_rx_clk>,
<&eth1_txc_tx_clk>, <&eth1_rxc_rx_clk>;
clock-names = "extal",
"eth0_txc_tx_clk", "eth0_rxc_rx_clk",
"eth1_txc_tx_clk", "eth1_rxc_rx_clk";
#clock-cells = <2>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
sysc: system-controller@11020000 {
compatible = "renesas,r9a08g046-sysc";
reg = <0 0x11020000 0 0x10000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "lpm_int", "ca55stbydone_int",
"cm33stbyr_int", "ca55_deny";
};
pinctrl: pinctrl@11030000 {
reg = <0 0x11030000 0 0x10000>;
gpio-controller;
#gpio-cells = <2>;
/* placeholder */
};
sdhi1: mmc@11c10000 {
reg = <0x0 0x11c10000 0 0x10000>;
/* placeholder */
};
pcie: pcie@11e40000 {
reg = <0 0x11e40000 0 0x10000>;
ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
/* placeholder */
pcie_port0: pcie@0,0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
ranges;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
/* placeholder */
};
};
gic: interrupt-controller@12400000 {
compatible = "arm,gic-v3";
reg = <0x0 0x12400000 0 0x20000>,
<0x0 0x12440000 0 0x80000>;
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
};
};

37
arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts Normal file
View File

@ -0,0 +1,37 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G3L SMARC EVK board
*
* Copyright (C) 2026 Renesas Electronics Corp.
*/
/dts-v1/;
/* Add place holder to avoid compilation error with renesas-smarc2.dtsi */
#define KEY_1_GPIO 1
#define KEY_2_GPIO 2
#define KEY_3_GPIO 3
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "r9a08g046l48.dtsi"
#include "rzg3l-smarc-som.dtsi"
#include "renesas-smarc2.dtsi"
/ {
model = "Renesas SMARC EVK version 2 based on r9a08g046l48";
compatible = "renesas,smarc2-evk", "renesas,rzg3l-smarcm",
"renesas,r9a08g046l48", "renesas,r9a08g046";
aliases {
serial3 = &scif0;
};
};
&keys {
status = "disabled";
/delete-node/ key-1;
/delete-node/ key-2;
/delete-node/ key-3;
};

13
arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi Normal file
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@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G3L R9A08G046L48 SoC specific parts
*
* Copyright (C) 2026 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r9a08g046.dtsi"
/ {
compatible = "renesas,r9a08g046l48", "renesas,r9a08g046";
};

3
arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
View File

@ -100,8 +100,7 @@ &avb {
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id001c.c916",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id001c.c916";
reg = <0>;
};
};

153
arch/arm64/boot/dts/renesas/r9a09g047.dtsi
View File

@ -591,6 +591,90 @@ channel5 {
};
};
rspi0: spi@12800000 {
compatible = "renesas,r9a09g047-rspi", "renesas,r9a09g057-rspi";
reg = <0x0 0x12800000 0x0 0x400>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 500 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 501 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "idle", "error", "end", "rx", "tx";
clocks = <&cpg CPG_MOD 0x54>,
<&cpg CPG_MOD 0x55>,
<&cpg CPG_MOD 0x56>;
clock-names = "pclk", "pclk_sfr", "tclk";
resets = <&cpg 0x7b>, <&cpg 0x7c>;
reset-names = "presetn", "tresetn";
dmas = <&dmac0 0x448c>, <&dmac0 0x448d>,
<&dmac1 0x448c>, <&dmac1 0x448d>,
<&dmac2 0x448c>, <&dmac2 0x448d>,
<&dmac3 0x448c>, <&dmac3 0x448d>,
<&dmac4 0x448c>, <&dmac4 0x448d>;
dma-names = "rx", "tx", "rx", "tx", "rx", "tx",
"rx", "tx", "rx", "tx";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rspi1: spi@12800400 {
compatible = "renesas,r9a09g047-rspi", "renesas,r9a09g057-rspi";
reg = <0x0 0x12800400 0x0 0x400>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 502 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 503 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "idle", "error", "end", "rx", "tx";
clocks = <&cpg CPG_MOD 0x57>,
<&cpg CPG_MOD 0x58>,
<&cpg CPG_MOD 0x59>;
clock-names = "pclk", "pclk_sfr", "tclk";
resets = <&cpg 0x7d>, <&cpg 0x7e>;
reset-names = "presetn", "tresetn";
dmas = <&dmac0 0x448e>, <&dmac0 0x448f>,
<&dmac1 0x448e>, <&dmac1 0x448f>,
<&dmac2 0x448e>, <&dmac2 0x448f>,
<&dmac3 0x448e>, <&dmac3 0x448f>,
<&dmac4 0x448e>, <&dmac4 0x448f>;
dma-names = "rx", "tx", "rx", "tx", "rx", "tx",
"rx", "tx", "rx", "tx";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rspi2: spi@12800800 {
compatible = "renesas,r9a09g047-rspi", "renesas,r9a09g057-rspi";
reg = <0x0 0x12800800 0x0 0x400>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 504 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 505 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "idle", "error", "end", "rx", "tx";
clocks = <&cpg CPG_MOD 0x5a>,
<&cpg CPG_MOD 0x5b>,
<&cpg CPG_MOD 0x5c>;
clock-names = "pclk", "pclk_sfr", "tclk";
resets = <&cpg 0x7f>, <&cpg 0x80>;
reset-names = "presetn", "tresetn";
dmas = <&dmac0 0x4490>, <&dmac0 0x4491>,
<&dmac1 0x4490>, <&dmac1 0x4491>,
<&dmac2 0x4490>, <&dmac2 0x4491>,
<&dmac3 0x4490>, <&dmac3 0x4491>,
<&dmac4 0x4490>, <&dmac4 0x4491>;
dma-names = "rx", "tx", "rx", "tx", "rx", "tx",
"rx", "tx", "rx", "tx";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rsci0: serial@12800c00 {
compatible = "renesas,r9a09g047-rsci";
reg = <0 0x12800c00 0 0x400>;
@ -841,6 +925,75 @@ wdt3: watchdog@13000400 {
status = "disabled";
};
pcie: pcie@13400000 {
compatible = "renesas,r9a09g047-pcie";
reg = <0 0x13400000 0 0x10000>;
ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x43000000 4 0x40000000 4 0x40000000 6 0x00000000>;
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 2 0x00000000>;
bus-range = <0x0 0xff>;
interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "serr", "serr_cor", "serr_nonfatal",
"serr_fatal", "axi_err", "inta",
"intb", "intc", "intd", "msi",
"link_bandwidth", "pm_pme", "dma",
"pcie_evt", "msg", "all",
"link_equalization_request",
"turn_off_event", "pmu_poweroff",
"d3_event_f0", "d3_event_f1",
"cfg_pmcsr_writeclear_f0",
"cfg_pmcsr_writeclear_f1";
#interrupt-cells = <1>;
interrupt-controller;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */
<0 0 0 2 &pcie 0 0 0 1>, /* INTB */
<0 0 0 3 &pcie 0 0 0 2>, /* INTC */
<0 0 0 4 &pcie 0 0 0 3>; /* INTD */
clocks = <&cpg CPG_MOD 0xc4>, <&cpg CPG_MOD 0xc5>;
clock-names = "aclk", "pmu";
resets = <&cpg 0xb2>;
reset-names = "aresetn";
power-domains = <&cpg>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
renesas,sysc = <&sys>;
status = "disabled";
pcie_port0: pcie@0,0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
ranges;
device_type = "pci";
vendor-id = <0x1912>;
device-id = <0x0039>;
#address-cells = <3>;
#size-cells = <2>;
};
};
tsu: thermal@14002000 {
compatible = "renesas,r9a09g047-tsu";
reg = <0 0x14002000 0 0x1000>;

38
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
View File

@ -122,6 +122,11 @@ key-sleep {
#endif
};
&pcie {
pinctrl-0 = <&pcie_pins>;
pinctrl-names = "default";
};
&pinctrl {
canfd_pins: canfd {
can1_pins: can1 {
@ -145,6 +150,17 @@ nmi_pins: nmi {
input-schmitt-enable;
};
pcie-clkreq-n-hog {
gpio-hog;
gpios = <RZG3E_GPIO(4, 5) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "PCIE_M2B_CKREQ";
};
pcie_pins: pcie {
pinmux = <RZG3E_PORT_PINMUX(G, 7, 1)>; /* PCIE_RST_OUT# */
};
rsci2_pins: rsci2 {
pinmux = <RZG3E_PORT_PINMUX(1, 0, 1)>, /* RXD2 */
<RZG3E_PORT_PINMUX(1, 1, 1)>, /* TXD2 */
@ -167,6 +183,13 @@ rsci9_pins: rsci9 {
bias-pull-up;
};
rspi0_pins: rspi0 {
pinmux = <RZG3E_PORT_PINMUX(M, 4, 2)>, /* MISOA */
<RZG3E_PORT_PINMUX(M, 5, 2)>, /* MOSIA */
<RZG3E_PORT_PINMUX(M, 6, 2)>, /* RSPCKA */
<RZG3E_PORT_PINMUX(M, 7, 2)>; /* SSLA0 */
};
scif_pins: scif {
pins = "SCIF_TXD", "SCIF_RXD";
renesas,output-impedance = <1>;
@ -234,6 +257,15 @@ &rsci9 {
};
#endif
&rspi0 {
pinctrl-0 = <&rspi0_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif_pins>;
pinctrl-names = "default";
@ -248,7 +280,13 @@ &sdhi1 {
vqmmc-supply = <&vqmmc_sd1_pvdd>;
};
&usb3_phy {
status = "okay";
};
&xhci {
pinctrl-0 = <&usb3_pins>;
pinctrl-names = "default";
status = "okay";
};

30
arch/arm64/boot/dts/renesas/r9a09g056.dtsi
View File

@ -599,16 +599,6 @@ ostm7: timer@12c03000 {
status = "disabled";
};
wdt0: watchdog@11c00400 {
compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt";
reg = <0 0x11c00400 0 0x400>;
clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
clock-names = "pclk", "oscclk";
resets = <&cpg 0x75>;
power-domains = <&cpg>;
status = "disabled";
};
wdt1: watchdog@14400000 {
compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt";
reg = <0 0x14400000 0 0x400>;
@ -619,26 +609,6 @@ wdt1: watchdog@14400000 {
status = "disabled";
};
wdt2: watchdog@13000000 {
compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt";
reg = <0 0x13000000 0 0x400>;
clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
clock-names = "pclk", "oscclk";
resets = <&cpg 0x77>;
power-domains = <&cpg>;
status = "disabled";
};
wdt3: watchdog@13000400 {
compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt";
reg = <0 0x13000400 0 0x400>;
clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
clock-names = "pclk", "oscclk";
resets = <&cpg 0x78>;
power-domains = <&cpg>;
status = "disabled";
};
rtc: rtc@11c00800 {
compatible = "renesas,r9a09g056-rtca3", "renesas,rz-rtca3";
reg = <0 0x11c00800 0 0x400>;

8
arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
View File

@ -260,12 +260,12 @@ raa215300: pmic@12 {
&mdio0 {
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1640";
reg = <0>;
rxc-skew-psec = <0>;
txc-skew-psec = <0>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
@ -279,12 +279,12 @@ phy0: ethernet-phy@0 {
&mdio1 {
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1640";
reg = <0>;
rxc-skew-psec = <0>;
txc-skew-psec = <0>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;

33
arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
View File

@ -108,6 +108,12 @@ vqmmc_sdhi1: regulator-vccq-sdhi1 {
states = <3300000 0>, <1800000 1>;
};
x1: x1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
/* 32.768kHz crystal */
x6: x6-clock {
compatible = "fixed-clock";
@ -277,16 +283,35 @@ raa215300: pmic@12 {
clocks = <&x6>;
clock-names = "xin";
};
versa3: clock-generator@69 {
compatible = "renesas,5l35023";
reg = <0x69>;
clocks = <&x1>;
#clock-cells = <1>;
assigned-clocks = <&versa3 0>, /* qextal_clk */
<&versa3 1>,
<&versa3 2>, /* rtxin_clk */
<&versa3 3>,
<&versa3 4>,
<&versa3 5>;
assigned-clock-rates = <24000000>,
<24576000>,
<32768>,
<22579200>,
<100000000>,
<100000000>;
};
};
&mdio0 {
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1640";
reg = <0>;
rxc-skew-psec = <0>;
txc-skew-psec = <0>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
@ -300,12 +325,12 @@ phy0: ethernet-phy@0 {
&mdio1 {
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1640";
reg = <0>;
rxc-skew-psec = <0>;
txc-skew-psec = <0>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;

39
arch/arm64/boot/dts/renesas/r9a09g057h48-kakip-pixpaper.dtso Normal file
View File

@ -0,0 +1,39 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Overlay for Mayqueen (Open-EP Community) pixpaper display
* support on Renesas RZ/V2H platform (KAKIP board).
*
* Copyright (C) 2026 Wig Cheng <onlywig@gmail.com>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
#include <dt-bindings/gpio/gpio.h>
&pinctrl {
rspi0_pins: rspi0 {
pinmux = <RZV2H_PORT_PINMUX(9, 0, 1)>, /* SPI0 MOSI */
<RZV2H_PORT_PINMUX(9, 1, 1)>, /* SPI0 MISO */
<RZV2H_PORT_PINMUX(9, 2, 1)>, /* SPI0 CLK */
<RZV2H_PORT_PINMUX(9, 3, 1)>; /* SPI0 CE0 */
};
};
&rspi0 {
pinctrl-0 = <&rspi0_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
display@0 {
compatible = "mayqueen,pixpaper";
reg = <0>;
spi-max-frequency = <1000000>;
reset-gpios = <&pinctrl RZV2H_GPIO(A, 7) GPIO_ACTIVE_HIGH>;
busy-gpios = <&pinctrl RZV2H_GPIO(B, 3) GPIO_ACTIVE_HIGH>;
dc-gpios = <&pinctrl RZV2H_GPIO(7, 4) GPIO_ACTIVE_HIGH>;
};
};

18
arch/arm64/boot/dts/renesas/r9a09g077.dtsi
View File

@ -8,6 +8,24 @@
#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/* The IRQ_NS lines start at offset 16 in the ICU interrupt space */
#define RZT2H_IRQ0 16
#define RZT2H_IRQ1 17
#define RZT2H_IRQ2 18
#define RZT2H_IRQ3 19
#define RZT2H_IRQ4 20
#define RZT2H_IRQ5 21
#define RZT2H_IRQ6 22
#define RZT2H_IRQ7 23
#define RZT2H_IRQ8 24
#define RZT2H_IRQ9 25
#define RZT2H_IRQ10 26
#define RZT2H_IRQ11 27
#define RZT2H_IRQ12 28
#define RZT2H_IRQ13 29
#define RZT2H_IRQ14 30
#define RZT2H_IRQ15 31
/ {
compatible = "renesas,r9a09g077";
#address-cells = <2>;

71
arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
View File

@ -14,12 +14,15 @@
/*
* SD0 can be connected to either eMMC (IC49) or SD card slot CN31
* Lets by default enable the eMMC, note we need the below SW settings
* for eMMC.
* for eMMC. Also ensure that CN78 pins 5 and 6 are connected with a jumper
* to provide the SD0 power supply when using eMMC.
* SW2[1] = ON; SW2[2] = ON
*
* To enable SD card and disable eMMC on SDHI0 disable the below macro
* and set the below switch setting:
* SW2[1] = OFF; SW2[2] = ON
* and set the switch as follows. Also ensure that CN78 pins 3 and 4 are connected
* with a jumper to provide the SD0 power supply when using an SD card.
*
* SW2[1] = OFF; SW2[2] = ON.
*/
#define SD0_EMMC 1
#define SD0_SD (!SD0_EMMC)
@ -224,10 +227,12 @@ &i2c1 {
};
&mdio1_phy {
interrupts-extended = <&icu RZT2H_IRQ3 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&pinctrl RZT2H_GPIO(32, 3) GPIO_ACTIVE_LOW>;
};
&mdio2_phy {
interrupts-extended = <&icu RZT2H_IRQ13 IRQ_TYPE_EDGE_FALLING>;
/*
* PHY2 Reset Configuration:
*
@ -248,6 +253,35 @@ can0_pins: can0-pins {
<RZT2H_PORT_PINMUX(24, 4, 0x19)>; /* CANTX0 */
};
/*
* GMAC1 Pin Configuration:
*
* SW2[8] ON - use pins P33_2-P33_7, P34_0-P34_5, P34_7 and
* P35_0-P35_2 for Ethernet port 3
*/
gmac1_pins: gmac1-pins {
pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
<RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD0 */
<RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD1 */
<RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD2 */
<RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD3 */
<RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */
<RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
<RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD0 */
<RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD1 */
<RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD2 */
<RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD3 */
<RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
<RZT2H_PORT_PINMUX(34, 7, 0xf)>, /* ETH3_TXER */
<RZT2H_PORT_PINMUX(35, 0, 0xf)>, /* ETH3_RXER */
<RZT2H_PORT_PINMUX(35, 1, 0xf)>, /* ETH3_CRS */
<RZT2H_PORT_PINMUX(35, 2, 0xf)>, /* ETH3_COL */
<RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC */
<RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* GMAC1_MDIO */
<RZT2H_PORT_PINMUX(34, 6, 0x2)>, /* ETH3_REFCLK */
<RZT2H_PORT_PINMUX(27, 2, 0x0)>; /* IRQ3 */
};
/*
* GMAC2 Pin Configuration:
*
@ -274,35 +308,8 @@ gmac2_pins: gmac2-pins {
<RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
<RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* GMAC2_MDC */
<RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* GMAC2_MDIO */
<RZT2H_PORT_PINMUX(31, 0, 0x2)>; /* ETH2_REFCLK */
};
/*
* GMAC1 Pin Configuration:
*
* SW2[8] ON - use pins P33_2-P33_7, P34_0-P34_5, P34_7 and
* P35_0-P35_2 for Ethernet port 3
*/
gmac1_pins: gmac1-pins {
pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
<RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD0 */
<RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD1 */
<RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD2 */
<RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD3 */
<RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */
<RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
<RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD0 */
<RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD1 */
<RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD2 */
<RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD3 */
<RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
<RZT2H_PORT_PINMUX(34, 7, 0xf)>, /* ETH3_TXER */
<RZT2H_PORT_PINMUX(35, 0, 0xf)>, /* ETH3_RXER */
<RZT2H_PORT_PINMUX(35, 1, 0xf)>, /* ETH3_CRS */
<RZT2H_PORT_PINMUX(35, 2, 0xf)>, /* ETH3_COL */
<RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC */
<RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* GMAC1_MDIO */
<RZT2H_PORT_PINMUX(34, 6, 0x2)>; /* ETH3_REFCLK */
<RZT2H_PORT_PINMUX(31, 0, 0x2)>, /* ETH2_REFCLK */
<RZT2H_PORT_PINMUX(31, 1, 0x0)>; /* IRQ13 */
};
/*

18
arch/arm64/boot/dts/renesas/r9a09g087.dtsi
View File

@ -8,6 +8,24 @@
#include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/* The IRQ_NS lines start at offset 16 in the ICU interrupt space */
#define RZN2H_IRQ0 16
#define RZN2H_IRQ1 17
#define RZN2H_IRQ2 18
#define RZN2H_IRQ3 19
#define RZN2H_IRQ4 20
#define RZN2H_IRQ5 21
#define RZN2H_IRQ6 22
#define RZN2H_IRQ7 23
#define RZN2H_IRQ8 24
#define RZN2H_IRQ9 25
#define RZN2H_IRQ10 26
#define RZN2H_IRQ11 27
#define RZN2H_IRQ12 28
#define RZN2H_IRQ13 29
#define RZN2H_IRQ14 30
#define RZN2H_IRQ15 31
/ {
compatible = "renesas,r9a09g087";
#address-cells = <2>;

75
arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
View File

@ -14,12 +14,14 @@
/*
* SD0 can be connected to either eMMC (U33) or SD card slot CN21
* Lets by default enable the eMMC, note we need the below SW settings
* for eMMC.
* for eMMC. Also ensure that JP23 pins 5 and 6 are connected with a jumper
* to provide the SD0 power supply when using eMMC.
* DSW5[1] = ON; DSW5[2] = ON
* DSW17[5] = OFF; DSW17[6] = ON
*
* To enable SD card and disable eMMC on SDHI0 disable the below macro
* and set the below switch setting:
* and set the below switch settings. Also ensure that JP23 pins 3 and 4 are
* connected with a jumper to provide the SD0 power supply when using an SD card.
* DSW5[1] = OFF; DSW5[2] = ON
* P22_6 = SD0_WP; DSW15[1] = OFF; DSW15[2] = ON
* P22_5 = SD0_CD; DSW15[3] = OFF; DSW15[4] = ON
@ -303,6 +305,7 @@ &i2c1 {
};
&mdio1_phy {
interrupts-extended = <&icu RZN2H_IRQ15 IRQ_TYPE_EDGE_FALLING>;
/*
* PHY3 Reset Configuration:
*
@ -312,6 +315,7 @@ &mdio1_phy {
};
&mdio2_phy {
interrupts-extended = <&icu RZN2H_IRQ14 IRQ_TYPE_EDGE_FALLING>;
/*
* PHY2 Reset Configuration:
*
@ -333,37 +337,7 @@ can1_pins: can1-pins {
};
/*
* GMAC2 Pin Configuration:
*
* DSW5[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2
* DSW5[7] ON - use pins P29_1-P29_7, P30_0-P30_4, P30_7,
* P31_2, P31_4 and P31_5 are used for Ethernet port 2
*/
gmac2_pins: gmac2-pins {
pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
<RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD0 */
<RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD1 */
<RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD2 */
<RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD3 */
<RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */
<RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
<RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD0 */
<RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD1 */
<RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD2 */
<RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD3 */
<RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
<RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
<RZT2H_PORT_PINMUX(31, 1, 0xf)>, /* ETH2_RXER */
<RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
<RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
<RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* GMAC2_MDC */
<RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* GMAC2_MDIO */
<RZT2H_PORT_PINMUX(31, 0, 0x2)>; /* ETH2_REFCLK */
};
/*
* GMAC2 Pin Configuration:
* GMAC1 Pin Configuration:
*
* DSW5[8] ON - use pins P00_0-P00_2, P33_2-P33_7, P34_0-P34_6
* for Ethernet port 3
@ -388,7 +362,40 @@ gmac1_pins: gmac1-pins {
<RZT2H_PORT_PINMUX(0, 3, 0xf)>, /* ETH3_COL */
<RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC */
<RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* GMAC1_MDIO */
<RZT2H_PORT_PINMUX(34, 6, 0x2)>; /* ETH3_REFCLK */
<RZT2H_PORT_PINMUX(34, 6, 0x2)>, /* ETH3_REFCLK */
<RZT2H_PORT_PINMUX(17, 3, 0x0)>; /* IRQ15 */
};
/*
* GMAC2 Pin Configuration:
*
* DSW5[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2
* DSW5[7] ON - use pins P29_1-P29_7, P30_0-P30_4, P30_7,
* P31_2, P31_4 and P31_5 are used for Ethernet port 2
* DSW13[7] OFF; DSW13[8] ON - use pin P13_7 for IRQ14
*/
gmac2_pins: gmac2-pins {
pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
<RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD0 */
<RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD1 */
<RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD2 */
<RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD3 */
<RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */
<RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
<RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD0 */
<RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD1 */
<RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD2 */
<RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD3 */
<RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
<RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
<RZT2H_PORT_PINMUX(31, 1, 0xf)>, /* ETH2_RXER */
<RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
<RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
<RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* GMAC2_MDC */
<RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* GMAC2_MDIO */
<RZT2H_PORT_PINMUX(31, 0, 0x2)>, /* ETH2_REFCLK */
<RZT2H_PORT_PINMUX(13, 7, 0x0)>; /* IRQ14 */
};
/*

12
arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
View File

@ -96,6 +96,10 @@ &i2c0 {
clock-frequency = <400000>;
};
&pcie {
status = "okay";
};
&scif0 {
status = "okay";
};
@ -107,11 +111,3 @@ &sdhi1 {
status = "okay";
};
&usb3_phy {
status = "okay";
};
&xhci {
status = "okay";
};

6
arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
View File

@ -99,8 +99,7 @@ &eth0 {
status = "okay";
phy0: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1640";
reg = <7>;
interrupts-extended = <&irqc RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;
@ -126,8 +125,7 @@ &eth1 {
status = "okay";
phy1: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1640";
reg = <7>;
interrupts-extended = <&irqc RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;

3
arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
View File

@ -79,8 +79,7 @@ &eth0 {
status = "okay";
phy0: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1640";
reg = <7>;
interrupts-extended = <&irqc RZG2L_IRQ0 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;

6
arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
View File

@ -75,8 +75,7 @@ &eth0 {
status = "okay";
phy0: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1640";
reg = <7>;
interrupts-extended = <&irqc RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;
@ -103,8 +102,7 @@ &eth1 {
status = "okay";
phy1: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1640";
reg = <7>;
interrupts-extended = <&irqc RZG2L_IRQ7 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;

21
arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
View File

@ -43,6 +43,12 @@ memory@48000000 {
reg = <0x0 0x48000000 0x0 0xf8000000>;
};
pcie_refclk: pcie-ref-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
@ -136,14 +142,13 @@ &i3c {
&mdio0 {
phy0: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1640";
reg = <7>;
interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <1400>;
txc-skew-psec = <1400>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
@ -157,14 +162,13 @@ phy0: ethernet-phy@7 {
&mdio1 {
phy1: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1640";
reg = <7>;
interrupts-extended = <&icu 16 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <1400>;
txc-skew-psec = <1400>;
rxdv-skew-psec = <0>;
txdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
@ -176,6 +180,11 @@ phy1: ethernet-phy@7 {
};
};
&pcie_port0 {
clocks = <&pcie_refclk>;
clock-names = "ref";
};
&pinctrl {
eth0_pins: eth0 {
clk {

20
arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi Normal file
View File

@ -0,0 +1,20 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for R9A08G046L48 SMARC SoM board.
*
* Copyright (C) 2026 Renesas Electronics Corp.
*/
/ {
compatible = "renesas,rzg3l-smarcm", "renesas,r9a08g046l48", "renesas,r9a08g046";
memory@48000000 {
device_type = "memory";
/* First 128MiB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
};
&extal_clk {
clock-frequency = <24000000>;
};

342
include/dt-bindings/clock/renesas,r9a08g046-cpg.h Normal file
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@ -0,0 +1,342 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
*
* Copyright (C) 2026 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__
#define __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* R9A08G046 CPG Core Clocks */
#define R9A08G046_CLK_I 0
#define R9A08G046_CLK_IC0 1
#define R9A08G046_CLK_IC1 2
#define R9A08G046_CLK_IC2 3
#define R9A08G046_CLK_IC3 4
#define R9A08G046_CLK_P0 5
#define R9A08G046_CLK_P1 6
#define R9A08G046_CLK_P2 7
#define R9A08G046_CLK_P3 8
#define R9A08G046_CLK_P4 9
#define R9A08G046_CLK_P5 10
#define R9A08G046_CLK_P6 11
#define R9A08G046_CLK_P7 12
#define R9A08G046_CLK_P8 13
#define R9A08G046_CLK_P9 14
#define R9A08G046_CLK_P10 15
#define R9A08G046_CLK_P13 16
#define R9A08G046_CLK_P14 17
#define R9A08G046_CLK_P15 18
#define R9A08G046_CLK_P16 19
#define R9A08G046_CLK_P17 20
#define R9A08G046_CLK_P18 21
#define R9A08G046_CLK_P19 22
#define R9A08G046_CLK_P20 23
#define R9A08G046_CLK_M0 24
#define R9A08G046_CLK_M1 25
#define R9A08G046_CLK_M2 26
#define R9A08G046_CLK_M3 27
#define R9A08G046_CLK_M4 28
#define R9A08G046_CLK_M5 29
#define R9A08G046_CLK_M6 30
#define R9A08G046_CLK_AT 31
#define R9A08G046_CLK_B 32
#define R9A08G046_CLK_ETHTX01 33
#define R9A08G046_CLK_ETHTX02 34
#define R9A08G046_CLK_ETHRX01 35
#define R9A08G046_CLK_ETHRX02 36
#define R9A08G046_CLK_ETHRM0 37
#define R9A08G046_CLK_ETHTX11 38
#define R9A08G046_CLK_ETHTX12 39
#define R9A08G046_CLK_ETHRX11 40
#define R9A08G046_CLK_ETHRX12 41
#define R9A08G046_CLK_ETHRM1 42
#define R9A08G046_CLK_G 43
#define R9A08G046_CLK_HP 44
#define R9A08G046_CLK_SD0 45
#define R9A08G046_CLK_SD1 46
#define R9A08G046_CLK_SD2 47
#define R9A08G046_CLK_SPI0 48
#define R9A08G046_CLK_SPI1 49
#define R9A08G046_CLK_S0 50
#define R9A08G046_CLK_SWD 51
#define R9A08G046_OSCCLK 52
#define R9A08G046_OSCCLK2 53
#define R9A08G046_MIPI_DSI_PLLCLK 54
#define R9A08G046_USB_SCLK 55
/* R9A08G046 Module Clocks */
#define R9A08G046_CA55_SCLK 0
#define R9A08G046_CA55_PCLK 1
#define R9A08G046_CA55_ATCLK 2
#define R9A08G046_CA55_GICCLK 3
#define R9A08G046_CA55_PERICLK 4
#define R9A08G046_CA55_ACLK 5
#define R9A08G046_CA55_TSCLK 6
#define R9A08G046_CA55_CORECLK0 7
#define R9A08G046_CA55_CORECLK1 8
#define R9A08G046_CA55_CORECLK2 9
#define R9A08G046_CA55_CORECLK3 10
#define R9A08G046_SRAM_ACPU_ACLK0 11
#define R9A08G046_SRAM_ACPU_ACLK1 12
#define R9A08G046_SRAM_ACPU_ACLK2 13
#define R9A08G046_GIC600_GICCLK 14
#define R9A08G046_IA55_CLK 15
#define R9A08G046_IA55_PCLK 16
#define R9A08G046_MHU_PCLK 17
#define R9A08G046_SYC_CNT_CLK 18
#define R9A08G046_DMAC_ACLK 19
#define R9A08G046_DMAC_PCLK 20
#define R9A08G046_OSTM0_PCLK 21
#define R9A08G046_OSTM1_PCLK 22
#define R9A08G046_OSTM2_PCLK 23
#define R9A08G046_MTU_X_MCK_MTU3 24
#define R9A08G046_POE3_CLKM_POE 25
#define R9A08G046_GPT_PCLK 26
#define R9A08G046_POEG_A_CLKP 27
#define R9A08G046_POEG_B_CLKP 28
#define R9A08G046_POEG_C_CLKP 29
#define R9A08G046_POEG_D_CLKP 30
#define R9A08G046_WDT0_PCLK 31
#define R9A08G046_WDT0_CLK 32
#define R9A08G046_WDT1_PCLK 33
#define R9A08G046_WDT1_CLK 34
#define R9A08G046_WDT2_PCLK 35
#define R9A08G046_WDT2_CLK 36
#define R9A08G046_XSPI_HCLK 37
#define R9A08G046_XSPI_ACLK 38
#define R9A08G046_XSPI_CLK 39
#define R9A08G046_XSPI_CLKX2 40
#define R9A08G046_SDHI0_IMCLK 41
#define R9A08G046_SDHI0_IMCLK2 42
#define R9A08G046_SDHI0_CLK_HS 43
#define R9A08G046_SDHI0_IACLKS 44
#define R9A08G046_SDHI0_IACLKM 45
#define R9A08G046_SDHI1_IMCLK 46
#define R9A08G046_SDHI1_IMCLK2 47
#define R9A08G046_SDHI1_CLK_HS 48
#define R9A08G046_SDHI1_IACLKS 49
#define R9A08G046_SDHI1_IACLKM 50
#define R9A08G046_SDHI2_IMCLK 51
#define R9A08G046_SDHI2_IMCLK2 52
#define R9A08G046_SDHI2_CLK_HS 53
#define R9A08G046_SDHI2_IACLKS 54
#define R9A08G046_SDHI2_IACLKM 55
#define R9A08G046_GE3D_CLK 56
#define R9A08G046_GE3D_AXI_CLK 57
#define R9A08G046_GE3D_ACE_CLK 58
#define R9A08G046_ISU_ACLK 59
#define R9A08G046_ISU_PCLK 60
#define R9A08G046_H264_CLK_A 61
#define R9A08G046_H264_CLK_P 62
#define R9A08G046_CRU_SYSCLK 63
#define R9A08G046_CRU_VCLK 64
#define R9A08G046_CRU_PCLK 65
#define R9A08G046_CRU_ACLK 66
#define R9A08G046_MIPI_DSI_SYSCLK 67
#define R9A08G046_MIPI_DSI_ACLK 68
#define R9A08G046_MIPI_DSI_PCLK 69
#define R9A08G046_MIPI_DSI_VCLK 70
#define R9A08G046_MIPI_DSI_LPCLK 71
#define R9A08G046_LVDS_PLLCLK 72
#define R9A08G046_LVDS_CLK_DOT0 73
#define R9A08G046_LCDC_CLK_A 74
#define R9A08G046_LCDC_CLK_D 75
#define R9A08G046_LCDC_CLK_P 76
#define R9A08G046_SSI0_PCLK2 77
#define R9A08G046_SSI0_PCLK_SFR 78
#define R9A08G046_SSI1_PCLK2 79
#define R9A08G046_SSI1_PCLK_SFR 80
#define R9A08G046_SSI2_PCLK2 81
#define R9A08G046_SSI2_PCLK_SFR 82
#define R9A08G046_SSI3_PCLK2 83
#define R9A08G046_SSI3_PCLK_SFR 84
#define R9A08G046_USB_U2H0_HCLK 85
#define R9A08G046_USB_U2H1_HCLK 86
#define R9A08G046_USB_U2P0_EXR_CPUCLK 87
#define R9A08G046_USB_U2P1_EXR_CPUCLK 88
#define R9A08G046_USB_PCLK 89
#define R9A08G046_ETH0_CLK_AXI 90
#define R9A08G046_ETH0_CLK_CHI 91
#define R9A08G046_ETH0_CLK_TX_I 92
#define R9A08G046_ETH0_CLK_RX_I 93
#define R9A08G046_ETH0_CLK_TX_180_I 94
#define R9A08G046_ETH0_CLK_RX_180_I 95
#define R9A08G046_ETH0_CLK_RMII_I 96
#define R9A08G046_ETH0_CLK_PTP_REF_I 97
#define R9A08G046_ETH0_CLK_TX_I_RMII 98
#define R9A08G046_ETH0_CLK_RX_I_RMII 99
#define R9A08G046_ETH1_CLK_AXI 100
#define R9A08G046_ETH1_CLK_CHI 101
#define R9A08G046_ETH1_CLK_TX_I 102
#define R9A08G046_ETH1_CLK_RX_I 103
#define R9A08G046_ETH1_CLK_TX_180_I 104
#define R9A08G046_ETH1_CLK_RX_180_I 105
#define R9A08G046_ETH1_CLK_RMII_I 106
#define R9A08G046_ETH1_CLK_PTP_REF_I 107
#define R9A08G046_ETH1_CLK_TX_I_RMII 108
#define R9A08G046_ETH1_CLK_RX_I_RMII 109
#define R9A08G046_I2C0_PCLK 110
#define R9A08G046_I2C1_PCLK 111
#define R9A08G046_I2C2_PCLK 112
#define R9A08G046_I2C3_PCLK 113
#define R9A08G046_SCIF0_CLK_PCK 114
#define R9A08G046_SCIF1_CLK_PCK 115
#define R9A08G046_SCIF2_CLK_PCK 116
#define R9A08G046_SCIF3_CLK_PCK 117
#define R9A08G046_SCIF4_CLK_PCK 118
#define R9A08G046_SCIF5_CLK_PCK 119
#define R9A08G046_RSCI0_PCLK 120
#define R9A08G046_RSCI0_TCLK 121
#define R9A08G046_RSCI1_PCLK 122
#define R9A08G046_RSCI1_TCLK 123
#define R9A08G046_RSCI2_PCLK 124
#define R9A08G046_RSCI2_TCLK 125
#define R9A08G046_RSCI3_PCLK 126
#define R9A08G046_RSCI3_TCLK 127
#define R9A08G046_RSPI0_PCLK 128
#define R9A08G046_RSPI0_TCLK 129
#define R9A08G046_RSPI1_PCLK 130
#define R9A08G046_RSPI1_TCLK 131
#define R9A08G046_RSPI2_PCLK 132
#define R9A08G046_RSPI2_TCLK 133
#define R9A08G046_CANFD_PCLK 134
#define R9A08G046_CANFD_CLK_RAM 135
#define R9A08G046_GPIO_HCLK 136
#define R9A08G046_ADC0_ADCLK 137
#define R9A08G046_ADC0_PCLK 138
#define R9A08G046_ADC1_ADCLK 139
#define R9A08G046_ADC1_PCLK 140
#define R9A08G046_TSU_PCLK 141
#define R9A08G046_PDM_PCLK 142
#define R9A08G046_PDM_CCLK 143
#define R9A08G046_PCI_ACLK 144
#define R9A08G046_PCI_CLKL1PM 145
#define R9A08G046_PCI_CLK_PMU 146
#define R9A08G046_SPDIF_PCLK 147
#define R9A08G046_I3C_TCLK 148
#define R9A08G046_I3C_PCLK 149
#define R9A08G046_VBAT_BCLK 150
#define R9A08G046_BSC_X_BCK_BSC 151
/* R9A08G046 Resets */
#define R9A08G046_CA55_RST0_0 0
#define R9A08G046_CA55_RST0_1 1
#define R9A08G046_CA55_RST0_2 2
#define R9A08G046_CA55_RST0_3 3
#define R9A08G046_CA55_RST4_0 4
#define R9A08G046_CA55_RST4_1 5
#define R9A08G046_CA55_RST4_2 6
#define R9A08G046_CA55_RST4_3 7
#define R9A08G046_CA55_RST8 8
#define R9A08G046_CA55_RST9 9
#define R9A08G046_CA55_RST10 10
#define R9A08G046_CA55_RST11 11
#define R9A08G046_CA55_RST12 12
#define R9A08G046_CA55_RST13 13
#define R9A08G046_CA55_RST14 14
#define R9A08G046_CA55_RST15 15
#define R9A08G046_CA55_RST16 16
#define R9A08G046_SRAM_ACPU_ARESETN0 17
#define R9A08G046_SRAM_ACPU_ARESETN1 18
#define R9A08G046_SRAM_ACPU_ARESETN2 19
#define R9A08G046_GIC600_GICRESET_N 20
#define R9A08G046_GIC600_DBG_GICRESET_N 21
#define R9A08G046_IA55_RESETN 22
#define R9A08G046_MHU_RESETN 23
#define R9A08G046_SYC_RESETN 24
#define R9A08G046_DMAC_ARESETN 25
#define R9A08G046_DMAC_RST_ASYNC 26
#define R9A08G046_GTM0_PRESETZ 27
#define R9A08G046_GTM1_PRESETZ 28
#define R9A08G046_GTM2_PRESETZ 29
#define R9A08G046_MTU_X_PRESET_MTU3 30
#define R9A08G046_POE3_RST_M_REG 31
#define R9A08G046_GPT_RST_C 32
#define R9A08G046_POEG_A_RST 33
#define R9A08G046_POEG_B_RST 34
#define R9A08G046_POEG_C_RST 35
#define R9A08G046_POEG_D_RST 36
#define R9A08G046_WDT0_PRESETN 37
#define R9A08G046_WDT1_PRESETN 38
#define R9A08G046_WDT2_PRESETN 39
#define R9A08G046_XSPI_HRESETN 40
#define R9A08G046_XSPI_ARESETN 41
#define R9A08G046_SDHI0_IXRST 42
#define R9A08G046_SDHI1_IXRST 43
#define R9A08G046_SDHI2_IXRST 44
#define R9A08G046_SDHI0_IXRSTAXIM 45
#define R9A08G046_SDHI0_IXRSTAXIS 46
#define R9A08G046_SDHI1_IXRSTAXIM 47
#define R9A08G046_SDHI1_IXRSTAXIS 48
#define R9A08G046_SDHI2_IXRSTAXIM 49
#define R9A08G046_SDHI2_IXRSTAXIS 50
#define R9A08G046_GE3D_RESETN 51
#define R9A08G046_GE3D_AXI_RESETN 52
#define R9A08G046_GE3D_ACE_RESETN 53
#define R9A08G046_ISU_ARESETN 54
#define R9A08G046_ISU_PRESETN 55
#define R9A08G046_H264_X_RESET_VCP 56
#define R9A08G046_H264_CP_PRESET_P 57
#define R9A08G046_CRU_CMN_RSTB 58
#define R9A08G046_CRU_PRESETN 59
#define R9A08G046_CRU_ARESETN 60
#define R9A08G046_MIPI_DSI_CMN_RSTB 61
#define R9A08G046_MIPI_DSI_ARESET_N 62
#define R9A08G046_MIPI_DSI_PRESET_N 63
#define R9A08G046_LCDC_RESET_N 64
#define R9A08G046_SSI0_RST_M2_REG 65
#define R9A08G046_SSI1_RST_M2_REG 66
#define R9A08G046_SSI2_RST_M2_REG 67
#define R9A08G046_SSI3_RST_M2_REG 68
#define R9A08G046_USB_U2H0_HRESETN 69
#define R9A08G046_USB_U2H1_HRESETN 70
#define R9A08G046_USB_U2P0_EXL_SYSRST 71
#define R9A08G046_USB_PRESETN 72
#define R9A08G046_USB_U2P1_EXL_SYSRST 73
#define R9A08G046_ETH0_ARESET_N 74
#define R9A08G046_ETH1_ARESET_N 75
#define R9A08G046_I2C0_MRST 76
#define R9A08G046_I2C1_MRST 77
#define R9A08G046_I2C2_MRST 78
#define R9A08G046_I2C3_MRST 79
#define R9A08G046_SCIF0_RST_SYSTEM_N 80
#define R9A08G046_SCIF1_RST_SYSTEM_N 81
#define R9A08G046_SCIF2_RST_SYSTEM_N 82
#define R9A08G046_SCIF3_RST_SYSTEM_N 83
#define R9A08G046_SCIF4_RST_SYSTEM_N 84
#define R9A08G046_SCIF5_RST_SYSTEM_N 85
#define R9A08G046_RSPI0_PRESETN 86
#define R9A08G046_RSPI1_PRESETN 87
#define R9A08G046_RSPI2_PRESETN 88
#define R9A08G046_RSPI0_TRESETN 89
#define R9A08G046_RSPI1_TRESETN 90
#define R9A08G046_RSPI2_TRESETN 91
#define R9A08G046_CANFD_RSTP_N 92
#define R9A08G046_CANFD_RSTC_N 93
#define R9A08G046_GPIO_RSTN 94
#define R9A08G046_GPIO_PORT_RESETN 95
#define R9A08G046_GPIO_SPARE_RESETN 96
#define R9A08G046_ADC0_PRESETN 97
#define R9A08G046_ADC0_ADRST_N 98
#define R9A08G046_ADC1_PRESETN 99
#define R9A08G046_ADC1_ADRST_N 100
#define R9A08G046_TSU_PRESETN 101
#define R9A08G046_PDM_PRESETN 102
#define R9A08G046_PCI_ARESETN 103
#define R9A08G046_SPDIF_RST 104
#define R9A08G046_I3C_TRESETN 105
#define R9A08G046_I3C_PRESETN 106
#define R9A08G046_VBAT_BRESETN 107
#define R9A08G046_RSCI0_PRESETN 108
#define R9A08G046_RSCI1_PRESETN 109
#define R9A08G046_RSCI2_PRESETN 110
#define R9A08G046_RSCI3_PRESETN 111
#define R9A08G046_RSCI0_TRESETN 112
#define R9A08G046_RSCI1_TRESETN 113
#define R9A08G046_RSCI2_TRESETN 114
#define R9A08G046_RSCI3_TRESETN 115
#define R9A08G046_LVDS_RESET_N 116
#define R9A08G046_BSC_X_PRESET_BSC 117
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__ */