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Qualcomm Arm64 DeviceTree updates for v7.1

Browse Source 
Introduce the Eliza, Glymur, Mahua, and IPQ5210 Qualcomm SoCs.
 
 Introduce the Redmi 4A, Redmi Go, Arduino Monza (VENTUNO Q), Redmi Note
 8T, Purwa EVK, ECS Liva QCS710, additional variants of the DB820c,
 Ayaneo Pocket S2, Thundercomm AI Mini PC G1, Samsung Galaxy Core Prime
 LTE Verizon Wireless, Wiko Pulp 4G, the Purwa-variant of ASUS Vivobook
 S15, the Eliza MTP, and the Glymur and Mahua CRDs.
 
 Introduce UFS support and flatten the DWC3 node on Hamoa. Enable UFS,
 SDC, DisplayPort audio playback, and an EL2 overlay for the Hamoa IoT
 EVK. Enable DisplayPort audio on the Hamoa CRD and add HDMI support on
 the ASUS Zenbook A14. Reduce the duplication of thermal sensors across
 Purwa and Hamoa.
 
 Add the QPIC SPI NAND controller on IPQ5332 and IPQ9574. Describe and
 enable the eMMC controller on IPQ9574.
 
 Add display, audio/compute remoteprocs, QUP devices, thermal sensors,
 display, and CoreSight on the Kaanapali platform. Enable audio, compute
 display, PMIC, Bluetooth, and WiFi on the MTP. Describe PMIC, audio and
 compute remoteprocs on QRD.
 
 Add role-switching support for the tertiary USB controller on Lemans.
 Enable the tertiary USB controller and the GPIO expander on the Lemans
 EVK, and add an overlay for the IFP Mezzanine.
 
 Add UFS, camera control interface, audio GPR, and FastRPC support on
 Milos. Enable UFS, camera EEPROMs, and hall effect sensor on the
 Fairphone FP6.
 
 Add camera control interface and fix a variety of things on the Monaco
 platform, add missing FastRPC compute banks. Add eMMC support, describe
 the DisplayPort bridge and GPIO expander on the Monaco EVK. Add overlay
 for EVK camera and the IFP mezzanine.
 
 Add touchscreen to the Xiaomi Redmi 4A, 5A, and Go, and fix the board-id
 on the 4A.
 
 Add the ambient light and proximity sensor on the Asus ZenFone 2
 Laser/Selfie.
 
 On Kodiak-based boards, enable the ethernet and USB Type-A ports on the
 Rb3Gen2, correct the LT9611 routing on the RubikPi3, add Bluetooth on
 the IDP, and add front camera support on the Fairphone FP5.
 Introduce an overlay for the Rb3Gen2 Industrial Mezzanine.
 
 Describe DSI on the Monaco SoC and enable Bluetooth, WiFi and DSI/DP
 bridge on the Ride board.
 
 Describe the WiFi/BT combo chip properly on the QRB2210 RB1 and QRB4210.
 The describe the DSI/DP bringde on the Arduino UnoQ.
 
 01022af2d2 arm64: dts: qcom: sc7280-chrome-common: disable Venus
 
 Introduce DSI display support on SC8280XP.
 
 Add LLCC on SDM670 and another SPI controller on SDM630.
 
 Properly describe the WiFi/BT chip on a variety of SDM845-based
 devices. Introduce the "alert slider" on the OnePlus 6 and OnePlus 6T
 devices.
 
 Introduce the PRNG, describe the debug UART, and add the MDSS core reset
 on SM6125. Enable the debug UART and fix various issues on the Xiaomi
 Redmi Note 8. Describe the touchscreen on the Xiaomi Mi A3.
 
 Properly describe the WiFi/BT combo chip in SM8150 HDK.
 
 Improve the EAS properties on SM8550, in addition to various other
 fixes. Introduce a new overlay for the HDK display card.
 
 Introduce various smaller fixes across SM8450 and SM8650.
 
 Add display support on SM8750 and enable DSI and DisplayPort on the MTP.
 Also add tsens and thermal-zones.
 
 Add ETR devices, flatten the USB controller node, and mark USB
 controllers as wakeup-capable devices, on Talos.
 
 Properly describe the IPA IMEM slice on a variety of platforms.
 
 Drop redundant non-controllable regulator definitions from a variety of
 boards.
 
 Drop redundant VSYNC pin state definition from various platforms.
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Merge tag 'qcom-arm64-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Qualcomm Arm64 DeviceTree updates for v7.1

Introduce the Eliza, Glymur, Mahua, and IPQ5210 Qualcomm SoCs.

Introduce the Redmi 4A, Redmi Go, Arduino Monza (VENTUNO Q), Redmi Note
8T, Purwa EVK, ECS Liva QCS710, additional variants of the DB820c,
Ayaneo Pocket S2, Thundercomm AI Mini PC G1, Samsung Galaxy Core Prime
LTE Verizon Wireless, Wiko Pulp 4G, the Purwa-variant of ASUS Vivobook
S15, the Eliza MTP, and the Glymur and Mahua CRDs.

Introduce UFS support and flatten the DWC3 node on Hamoa. Enable UFS,
SDC, DisplayPort audio playback, and an EL2 overlay for the Hamoa IoT
EVK. Enable DisplayPort audio on the Hamoa CRD and add HDMI support on
the ASUS Zenbook A14. Reduce the duplication of thermal sensors across
Purwa and Hamoa.

Add the QPIC SPI NAND controller on IPQ5332 and IPQ9574. Describe and
enable the eMMC controller on IPQ9574.

Add display, audio/compute remoteprocs, QUP devices, thermal sensors,
display, and CoreSight on the Kaanapali platform. Enable audio, compute
display, PMIC, Bluetooth, and WiFi on the MTP. Describe PMIC, audio and
compute remoteprocs on QRD.

Add role-switching support for the tertiary USB controller on Lemans.
Enable the tertiary USB controller and the GPIO expander on the Lemans
EVK, and add an overlay for the IFP Mezzanine.

Add UFS, camera control interface, audio GPR, and FastRPC support on
Milos. Enable UFS, camera EEPROMs, and hall effect sensor on the
Fairphone FP6.

Add camera control interface and fix a variety of things on the Monaco
platform, add missing FastRPC compute banks. Add eMMC support, describe
the DisplayPort bridge and GPIO expander on the Monaco EVK. Add overlay
for EVK camera and the IFP mezzanine.

Add touchscreen to the Xiaomi Redmi 4A, 5A, and Go, and fix the board-id
on the 4A.

Add the ambient light and proximity sensor on the Asus ZenFone 2
Laser/Selfie.

On Kodiak-based boards, enable the ethernet and USB Type-A ports on the
Rb3Gen2, correct the LT9611 routing on the RubikPi3, add Bluetooth on
the IDP, and add front camera support on the Fairphone FP5.
Introduce an overlay for the Rb3Gen2 Industrial Mezzanine.

Describe DSI on the Monaco SoC and enable Bluetooth, WiFi and DSI/DP
bridge on the Ride board.

Describe the WiFi/BT combo chip properly on the QRB2210 RB1 and QRB4210.
The describe the DSI/DP bringde on the Arduino UnoQ.

01022af2d2 arm64: dts: qcom: sc7280-chrome-common: disable Venus

Introduce DSI display support on SC8280XP.

Add LLCC on SDM670 and another SPI controller on SDM630.

Properly describe the WiFi/BT chip on a variety of SDM845-based
devices. Introduce the "alert slider" on the OnePlus 6 and OnePlus 6T
devices.

Introduce the PRNG, describe the debug UART, and add the MDSS core reset
on SM6125. Enable the debug UART and fix various issues on the Xiaomi
Redmi Note 8. Describe the touchscreen on the Xiaomi Mi A3.

Properly describe the WiFi/BT combo chip in SM8150 HDK.

Improve the EAS properties on SM8550, in addition to various other
fixes. Introduce a new overlay for the HDK display card.

Introduce various smaller fixes across SM8450 and SM8650.

Add display support on SM8750 and enable DSI and DisplayPort on the MTP.
Also add tsens and thermal-zones.

Add ETR devices, flatten the USB controller node, and mark USB
controllers as wakeup-capable devices, on Talos.

Properly describe the IPA IMEM slice on a variety of platforms.

Drop redundant non-controllable regulator definitions from a variety of
boards.

Drop redundant VSYNC pin state definition from various platforms.

* tag 'qcom-arm64-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (254 commits)
  arm64: dts: qcom: sm8250: Add missing CPU7 3.09GHz OPP
  arm64: dts: qcom: sm8550-hdk: add support for the Display Card overlay
  arm64: dts: qcom: msm8916-samsung-coreprimeltevzw: add device tree
  dt-bindings: qcom: Document samsung,coreprimeltevzw
  arm64: dts: qcom: msm8916-samsung-fortuna: Move SM5504 from rossa and refactor MUIC
  arm64: dts: qcom: sdm670: add llcc
  arm64: dts: qcom: qcm6490-fairphone-fp5: Add front camera support
  arm64: dts: qcom: qcm6490-fairphone-fp5: Sort pinctrl nodes by pins
  arm64: dts: qcom: milos-fairphone-fp6: Add camera EEPROMs on CCI busses
  arm64: dts: qcom: milos: Add CCI busses
  arm64: dts: qcom: purwa-iot-evk: Enable UFS
  arm64: dts: qcom: eliza: Add thermal sensors
  arm64: dts: qcom: sc8280xp: Add dsi nodes on SC8280XP
  arm64: dts: qcom: sdm845-oneplus: Describe Wi-Fi/BT properly
  arm64: dts: qcom: sdm845-google: Describe Wi-Fi/BT properly
  arm64: dts: qcom: drop redundant zap-shader memory-region
  arm64: dts: qcom: fix remaining gpu_zap_shader labels
  arm64: dts: qcom: msm8996: fix indentation in sdhc2 node
  arm64: dts: qcom: monaco-evk: enable UART6 for robot expansion board
  arm64: dts: qcom: lemans-evk: enable UART0 for robot expansion board
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2026-04-03 00:08:34 +02:00
commit 8366b60cbe
178 changed files with 37167 additions and 5001 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
Documentation/devicetree/bindings/arm/cpus.yaml
View File

@ -218,6 +218,13 @@ properties:
- qcom,kryo685
- qcom,kryo780
- qcom,oryon
- qcom,oryon-1-1
- qcom,oryon-1-2
- qcom,oryon-1-3
- qcom,oryon-1-4
- qcom,oryon-2-1
- qcom,oryon-2-2
- qcom,oryon-2-3
- qcom,scorpion
- samsung,mongoose-m2
- samsung,mongoose-m3

45
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@ -61,6 +61,21 @@ properties:
- qcom,apq8084-sbc
- const: qcom,apq8084
- items:
- enum:
- qcom,eliza-mtp
- const: qcom,eliza
- items:
- enum:
- qcom,glymur-crd
- const: qcom,glymur
- items:
- enum:
- qcom,mahua-crd
- const: qcom,mahua
- items:
- enum:
- fairphone,fp6
@ -171,6 +186,7 @@ properties:
- qcom,msm8916-mtp
- samsung,a3u-eur
- samsung,a5u-eur
- samsung,coreprimeltevzw
- samsung,e5
- samsung,e7
- samsung,fortuna3g
@ -186,6 +202,7 @@ properties:
- samsung,serranove
- thwc,uf896
- thwc,ufi001c
- wiko,chuppito
- wingtech,wt86518
- wingtech,wt86528
- wingtech,wt88047
@ -195,6 +212,8 @@ properties:
- items:
- enum:
- xiaomi,riva
- xiaomi,rolex
- xiaomi,tiare
- const: qcom,msm8917
- items:
@ -243,6 +262,13 @@ properties:
- const: qcom,apq8096-sbc
- const: qcom,apq8096
- items:
- const: arrow,apq8096sg-db820c
- const: arrow,apq8096-db820c
- const: qcom,apq8096-sbc
- const: qcom,apq8096sg
- const: qcom,apq8096
- items:
- enum:
- oneplus,oneplus3
@ -297,6 +323,11 @@ properties:
- tplink,archer-ax55-v1
- const: qcom,ipq5018
- items:
- enum:
- qcom,ipq5210-rdp504
- const: qcom,ipq5210
- items:
- enum:
- qcom,ipq5332-ap-mi01.2
@ -326,8 +357,10 @@ properties:
- items:
- enum:
- qcom,ipq9574-ap-al02-c2
- qcom,ipq9574-ap-al02-c2-emmc
- qcom,ipq9574-ap-al02-c6
- qcom,ipq9574-ap-al02-c7
- qcom,ipq9574-ap-al02-c7-emmc
- qcom,ipq9574-ap-al02-c8
- qcom,ipq9574-ap-al02-c9
- const: qcom,ipq9574
@ -360,6 +393,7 @@ properties:
- qcom,qcs6490-rb3gen2
- radxa,dragon-q6a
- shift,otter
- thundercomm,minipc-g1iot
- thundercomm,rubikpi3
- const: qcom,qcm6490
@ -385,6 +419,7 @@ properties:
- items:
- enum:
- acer,aspire1
- ecs,liva-qc710
- qcom,sc7180-idp
- const: qcom,sc7180
@ -876,6 +911,7 @@ properties:
- items:
- enum:
- arduino,monza
- qcom,monaco-evk
- qcom,qcs8300-ride
- const: qcom,qcs8300
@ -966,6 +1002,7 @@ properties:
- sony,pdx201
- xiaomi,ginkgo
- xiaomi,laurel-sprout
- xiaomi,willow
- const: qcom,sm6125
- items:
@ -1057,6 +1094,7 @@ properties:
- items:
- enum:
- ayaneo,pocket-s2
- qcom,sm8650-hdk
- qcom,sm8650-mtp
- qcom,sm8650-qrd
@ -1122,6 +1160,12 @@ properties:
- const: microsoft,denali
- const: qcom,x1e80100
- items:
- enum:
- qcom,purwa-iot-evk
- const: qcom,purwa-iot-som
- const: qcom,x1p42100
- items:
- enum:
- asus,zenbook-a14-ux3407qa-lcd
@ -1131,6 +1175,7 @@ properties:
- items:
- enum:
- asus,vivobook-s15-x1p4
- hp,omnibook-x14-fe1
- lenovo,thinkbook-16
- qcom,x1p42100-crd

62
Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml Normal file
View File

@ -0,0 +1,62 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,ipq5210-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ5210
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ5210
See also:
include/dt-bindings/clock/qcom,ipq5210-gcc.h
include/dt-bindings/reset/qcom,ipq5210-gcc.h
properties:
compatible:
const: qcom,ipq5210-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: PCIE30 PHY0 pipe clock source
- description: PCIE30 PHY1 pipe clock source
- description: USB3 PHY pipe clock source
- description: NSS common clock source
'#power-domain-cells': false
'#interconnect-cells':
const: 1
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
clock-controller@1800000 {
compatible = "qcom,ipq5210-gcc";
reg = <0x01800000 0x40000>;
clocks = <&xo_board_clk>,
<&sleep_clk>,
<&pcie30_phy0_pipe_clk>,
<&pcie30_phy1_pipe_clk>,
<&usb3phy_0_cc_pipe_clk>,
<&nss_cmn_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
};
...

9
Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml
View File

@ -8,16 +8,21 @@ title: Qualcomm Global Clock & Reset Controller on Milos
maintainers:
- Luca Weiss <luca.weiss@fairphone.com>
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on Milos.
See also: include/dt-bindings/clock/qcom,milos-gcc.h
See also:
- include/dt-bindings/clock/qcom,eliza-gcc.h
- include/dt-bindings/clock/qcom,milos-gcc.h
properties:
compatible:
const: qcom,milos-gcc
enum:
- qcom,eliza-gcc
- qcom,milos-gcc
clocks:
items:

1
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
View File

@ -17,6 +17,7 @@ description: |
properties:
compatible:
enum:
- qcom,eliza-rpmh-clk
- qcom,glymur-rpmh-clk
- qcom,kaanapali-rpmh-clk
- qcom,milos-rpmh-clk

2
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
View File

@ -15,6 +15,7 @@ description: |
power domains on SM8550
See also:
- include/dt-bindings/clock/qcom,eliza-tcsr.h
- include/dt-bindings/clock/qcom,glymur-tcsr.h
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
@ -24,6 +25,7 @@ properties:
compatible:
items:
- enum:
- qcom,eliza-tcsr
- qcom,glymur-tcsr
- qcom,kaanapali-tcsr
- qcom,milos-tcsr

142
Documentation/devicetree/bindings/interconnect/qcom,eliza-rpmh.yaml Normal file
View File

@ -0,0 +1,142 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,eliza-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on Eliza SoC
maintainers:
- Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also: include/dt-bindings/interconnect/qcom,eliza-rpmh.h
properties:
compatible:
enum:
- qcom,eliza-aggre1-noc
- qcom,eliza-aggre2-noc
- qcom,eliza-clk-virt
- qcom,eliza-cnoc-cfg
- qcom,eliza-cnoc-main
- qcom,eliza-gem-noc
- qcom,eliza-lpass-ag-noc
- qcom,eliza-lpass-lpiaon-noc
- qcom,eliza-lpass-lpicx-noc
- qcom,eliza-mc-virt
- qcom,eliza-mmss-noc
- qcom,eliza-nsp-noc
- qcom,eliza-pcie-anoc
- qcom,eliza-system-noc
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,eliza-clk-virt
- qcom,eliza-mc-virt
then:
properties:
reg: false
else:
required:
- reg
- if:
properties:
compatible:
contains:
enum:
- qcom,eliza-aggre1-noc
then:
properties:
clocks:
items:
- description: aggre UFS PHY AXI clock
- description: aggre USB3 PRIM AXI clock
- if:
properties:
compatible:
contains:
enum:
- qcom,eliza-aggre2-noc
then:
properties:
clocks:
items:
- description: RPMH CC IPA clock
- if:
properties:
compatible:
contains:
enum:
- qcom,eliza-pcie-anoc
then:
properties:
clocks:
items:
- description: aggre-NOC PCIe AXI clock
- description: cfg-NOC PCIe a-NOC AHB clock
- if:
properties:
compatible:
contains:
enum:
- qcom,eliza-aggre1-noc
- qcom,eliza-aggre2-noc
- qcom,eliza-pcie-anoc
then:
required:
- clocks
else:
properties:
clocks: false
unevaluatedProperties: false
examples:
- |
gem_noc: interconnect@24100000 {
compatible = "qcom,eliza-gem-noc";
reg = <0x24100000 0x163080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect-2 {
compatible = "qcom,eliza-mc-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,eliza-aggre1-noc";
reg = <0x16e0000 0x16400>;
#interconnect-cells = <2>;
clocks = <&gcc_phy_axi_clk>, <&gcc_prim_axi_clk>;
qcom,bcm-voters = <&apps_bcm_voter>;
};

1
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
View File

@ -28,6 +28,7 @@ properties:
- const: qcom,osm-l3
- items:
- enum:
- qcom,eliza-epss-l3
- qcom,sa8775p-epss-l3
- qcom,sc7280-epss-l3
- qcom,sc8280xp-epss-l3

4
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -221,6 +221,8 @@ patternProperties:
description: Axiado Corporation
"^axis,.*":
description: Axis Communications AB
"^ayaneo,.*":
description: Anyun Intelligent Technology (Hong Kong) Co., Ltd
"^azoteq,.*":
description: Azoteq (Pty) Ltd
"^azw,.*":
@ -1827,6 +1829,8 @@ patternProperties:
description: Wi2Wi, Inc.
"^widora,.*":
description: Beijing Widora Technology Co., Ltd.
"^wiko,.*":
description: Wiko SAS
"^wiligear,.*":
description: Wiligear, Ltd.
"^willsemi,.*":

49
arch/arm64/boot/dts/qcom/Makefile
View File

@ -12,10 +12,18 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-schneider-hmibsc.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096sg-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
dtb-$(CONFIG_ARCH_QCOM) += eliza-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb
dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb
hamoa-iot-evk-el2-dtbs := hamoa-iot-evk.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5210-rdp504.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
@ -25,8 +33,8 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb ipq9574-rdp418-emmc.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb ipq9574-rdp433-emmc.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb
@ -43,8 +51,21 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera.dtb
lemans-evk-el2-dtbs := lemans-evk.dtb lemans-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-el2.dtb
lemans-evk-ifp-mezzanine-dtbs := lemans-evk.dtb lemans-evk-ifp-mezzanine.dtbo
dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-ifp-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += mahua-crd.dtb
dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb
dtb-$(CONFIG_ARCH_QCOM) += monaco-arduino-monza.dtb
dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb
monaco-evk-camera-imx577-dtbs := monaco-evk.dtb monaco-evk-camera-imx577.dtbo
dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camera-imx577.dtb
monaco-evk-el2-dtbs := monaco-evk.dtb monaco-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-el2.dtb
monaco-evk-ifp-mezzanine-dtbs := monaco-evk.dtb monaco-evk-ifp-mezzanine.dtbo
dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-ifp-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
@ -61,6 +82,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-motorola-surnia.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-coreprimeltevzw.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-e5.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-e7.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-gprimeltecan.dtb
@ -75,11 +97,14 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-rossa.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-wiko-chuppito.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt86518.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt86528.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8917-xiaomi-riva.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8917-xiaomi-rolex.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8917-xiaomi-tiare.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8929-wingtech-wt82918hd.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8937-xiaomi-land.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8939-asus-z00t.dtb
@ -130,6 +155,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-lilac.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb
dtb-$(CONFIG_ARCH_QCOM) += purwa-iot-evk.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcm6490-fairphone-fp5.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcm6490-particle-tachyon.dtb
@ -145,8 +171,13 @@ qcs6490-rb3gen2-industrial-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-minipc-g1iot.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-rubikpi3.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb
qcs8300-ride-el2-dtbs := qcs8300-ride.dtb monaco-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb
@ -178,6 +209,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride-r3.dtb
sc7180-acer-aspire1-el2-dtbs := sc7180-acer-aspire1.dtb sc7180-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += sc7180-acer-aspire1.dtb sc7180-acer-aspire1-el2.dtb
sc7180-ecs-liva-qc710-el2-dtbs := sc7180-ecs-liva-qc710.dtb sc7180-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += sc7180-ecs-liva-qc710.dtb sc7180-ecs-liva-qc710-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb
@ -294,8 +327,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-ginkgo.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-ginkgo.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-laurel-sprout.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-willow.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-curtana.dtb
@ -327,14 +361,19 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-samsung-r0q.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb
sm8550-hdk-display-card-dtbs := sm8550-hdk.dtb sm8550-hdk-display-card.dtbo
sm8550-hdk-display-card-rear-camera-card-dtbs := sm8550-hdk.dtb sm8550-hdk-display-card.dtbo sm8550-hdk-rear-camera-card.dtbo
sm8550-hdk-rear-camera-card-dtbs := sm8550-hdk.dtb sm8550-hdk-rear-camera-card.dtbo
dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk-display-card-rear-camera-card.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk-display-card.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk-rear-camera-card.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-samsung-q5q.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-sony-xperia-yodo-pdx234.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-ayaneo-pocket-s2.dtb
sm8650-hdk-display-card-dtbs := sm8650-hdk.dtb sm8650-hdk-display-card.dtbo
sm8650-hdk-display-card-rear-camera-card-dtbs := sm8650-hdk.dtb sm8650-hdk-display-card.dtbo sm8650-hdk-rear-camera-card.dtbo
@ -374,12 +413,16 @@ x1e80100-lenovo-yoga-slim7x-el2-dtbs := x1e80100-lenovo-yoga-slim7x.dtb x1-el2.d
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-lenovo-yoga-slim7x.dtb x1e80100-lenovo-yoga-slim7x-el2.dtb
x1e80100-medion-sprchrgd-14-s1-el2-dtbs := x1e80100-medion-sprchrgd-14-s1.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-medion-sprchrgd-14-s1.dtb x1e80100-medion-sprchrgd-14-s1-el2.dtb
x1e80100-microsoft-denali-oled-el2-dtbs := x1e80100-microsoft-denali-oled.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-denali-oled.dtb x1e80100-microsoft-denali-oled-el2.dtb
x1e80100-microsoft-romulus13-el2-dtbs := x1e80100-microsoft-romulus13.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus13.dtb x1e80100-microsoft-romulus13-el2.dtb
x1e80100-microsoft-romulus15-el2-dtbs := x1e80100-microsoft-romulus15.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus15.dtb x1e80100-microsoft-romulus15-el2.dtb
x1e80100-qcp-el2-dtbs := x1e80100-qcp.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-qcp.dtb x1e80100-qcp-el2.dtb
x1p42100-asus-vivobook-s15-el2-dtbs := x1p42100-asus-vivobook-s15.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1p42100-asus-vivobook-s15.dtb x1p42100-asus-vivobook-s15-el2.dtb
x1p42100-asus-zenbook-a14-el2-dtbs := x1p42100-asus-zenbook-a14.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += x1p42100-asus-zenbook-a14.dtb x1p42100-asus-zenbook-a14-el2.dtb
x1p42100-asus-zenbook-a14-lcd-el2-dtbs := x1p42100-asus-zenbook-a14-lcd.dtb x1-el2.dtbo

8
arch/arm64/boot/dts/qcom/agatti.dtsi
View File

@ -2839,9 +2839,9 @@ camera_crit: camera-crit {
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
};
};

1126
arch/arm64/boot/dts/qcom/apq8096-db820c.dts
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File diff suppressed because it is too large Load Diff

1133
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

15
arch/arm64/boot/dts/qcom/apq8096sg-db820c.dts Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/dts-v1/;
#include "msm8996pro.dtsi"
#include "apq8096-db820c.dtsi"
/ {
model = "Qualcomm Technologies, Inc. DB820c";
compatible = "arrow,apq8096sg-db820c", "arrow,apq8096-db820c",
"qcom,apq8096-sbc", "qcom,apq8096sg", "qcom,apq8096";
};

407
arch/arm64/boot/dts/qcom/eliza-mtp.dts Normal file
View File

@ -0,0 +1,407 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "eliza.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Eliza MTP";
compatible = "qcom,eliza-mtp", "qcom,eliza";
chassis-type = "handset";
aliases {
serial0 = &uart14;
};
chosen {
stdout-path = "serial0:115200n8";
};
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
clock-frequency = <76800000>;
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32764>;
#clock-cells = <0>;
};
bi_tcxo_div2: bi-tcxo-div2-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-mult = <1>;
clock-div = <2>;
};
bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&rpmhcc RPMH_CXO_CLK_A>;
clock-mult = <1>;
clock-div = <2>;
};
};
vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-boot-on;
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pm7550-rpmh-regulators";
vdd-l1-supply = <&vreg_s3b>;
vdd-l2-l3-supply = <&vreg_s3b>;
vdd-l4-l5-supply = <&vreg_s2b>;
vdd-l6-supply = <&vreg_s2b>;
vdd-l7-supply = <&vreg_s1b>;
vdd-l8-supply = <&vreg_s1b>;
vdd-l9-l10-supply = <&vreg_s1b>;
vdd-l11-supply = <&vreg_s1b>;
vdd-l12-l14-supply = <&vreg_bob>;
vdd-l13-l16-supply = <&vreg_bob>;
vdd-l15-l17-l18-l19-l20-l21-l22-l23-supply = <&vreg_bob>;
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-bob-supply = <&vph_pwr>;
qcom,pmic-id = "b";
vreg_s1b: smps1 {
regulator-name = "vreg_s1b";
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <2040000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s2b: smps2 {
regulator-name = "vreg_s2b";
regulator-min-microvolt = <375000>;
regulator-max-microvolt = <2744000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s3b: smps3 {
regulator-name = "vreg_s3b";
regulator-min-microvolt = <375000>;
regulator-max-microvolt = <2744000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s4b: smps4 {
regulator-name = "vreg_s4b";
regulator-min-microvolt = <2156000>;
regulator-max-microvolt = <2400000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2b: ldo2 {
regulator-name = "vreg_l2b";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3b: ldo3 {
regulator-name = "vreg_l3b";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4b: ldo4 {
regulator-name = "vreg_l4b";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6b: ldo6 {
regulator-name = "vreg_l6b";
regulator-min-microvolt = <866000>;
regulator-max-microvolt = <958000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7b: ldo7 {
regulator-name = "vreg_l7b";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8b: ldo8 {
regulator-name = "vreg_l8b";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9b: ldo9 {
regulator-name = "vreg_l9b";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10b: ldo10 {
regulator-name = "vreg_l10b";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11b: ldo11 {
regulator-name = "vreg_l11b";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12b: ldo12 {
regulator-name = "vreg_l12b";
/* Voltage range for UFS 3.x and above */
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13b: ldo13 {
regulator-name = "vreg_l13b";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l14b: ldo14 {
regulator-name = "vreg_l14b";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l15b: ldo15 {
regulator-name = "vreg_l15b";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l16b: ldo16 {
regulator-name = "vreg_l16b";
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l17b: ldo17 {
regulator-name = "vreg_l17b";
regulator-min-microvolt = <3104000>;
regulator-max-microvolt = <3104000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l18b: ldo18 {
regulator-name = "vreg_l18b";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l19b: ldo19 {
regulator-name = "vreg_l19b";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l20b: ldo20 {
regulator-name = "vreg_l20b";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l21b: ldo21 {
regulator-name = "vreg_l21b";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l22b: ldo22 {
regulator-name = "vreg_l22b";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l23b: ldo23 {
regulator-name = "vreg_l23b";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_bob: bob {
regulator-name = "vreg_bob";
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-1 {
compatible = "qcom,pm8550vs-rpmh-regulators";
vdd-l1-supply = <&vreg_s2b>;
qcom,pmic-id = "d";
vreg_l1d: ldo1 {
regulator-name = "vreg_l1d";
regulator-min-microvolt = <1140000>;
regulator-max-microvolt = <1260000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-2 {
compatible = "qcom,pm8550vs-rpmh-regulators";
vdd-l1-supply = <&vreg_s2b>;
vdd-l3-supply = <&vreg_s2b>;
qcom,pmic-id = "g";
vreg_l1g: ldo1 {
regulator-name = "vreg_l1g";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1260000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3g: ldo3 {
regulator-name = "vreg_l3g";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1260000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-3 {
compatible = "qcom,pmr735d-rpmh-regulators";
vdd-l1-l2-l5-supply = <&vreg_s3b>;
vdd-l3-l4-supply = <&vreg_s2b>;
vdd-l6-supply = <&vreg_s1b>;
vdd-l7-supply = <&vreg_s3b>;
qcom,pmic-id = "k";
vreg_l1k: ldo1 {
regulator-name = "vreg_l1k";
regulator-min-microvolt = <488000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2k: ldo2 {
regulator-name = "vreg_l2k";
regulator-min-microvolt = <920000>;
regulator-max-microvolt = <969000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3k: ldo3 {
regulator-name = "vreg_l3k";
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1350000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4k: ldo4 {
regulator-name = "vreg_l4k";
regulator-min-microvolt = <960000>;
regulator-max-microvolt = <1980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5k: ldo5 {
regulator-name = "vreg_l5k";
regulator-min-microvolt = <866000>;
regulator-max-microvolt = <931000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6k: ldo6 {
regulator-name = "vreg_l6k";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7k: ldo7 {
regulator-name = "vreg_l7k";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <958000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
};
&tlmm {
gpio-reserved-ranges = <20 4>, /* NFC SPI */
<111 2>, /* WCN UART1 */
<118 1>; /* NFC Secure I/O */
};
&uart14 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};
&ufs_mem_hc {
reset-gpios = <&tlmm 185 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l12b>;
vcc-max-microamp = <1300000>;
vccq-supply = <&vreg_l1d>;
vccq-max-microamp = <1200000>;
status = "okay";
};
&ufs_mem_phy {
vdda-phy-supply = <&vreg_l6b>;
vdda-pll-supply = <&vreg_l4b>;
status = "okay";
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/dts-v1/;
#include "glymur.dtsi"
#include "glymur-crd.dtsi"
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
model = "Qualcomm Technologies, Inc. Glymur CRD";
compatible = "qcom,glymur-crd", "qcom,glymur";
pmic-glink {
compatible = "qcom,glymur-pmic-glink",
"qcom,pmic-glink";
#address-cells = <1>;
#size-cells = <0>;
connector@0 {
compatible = "usb-c-connector";
reg = <0>;
power-role = "dual";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
pmic_glink_hs_in: endpoint {
remote-endpoint = <&usb_0_dwc3_hs>;
};
};
port@1 {
reg = <1>;
pmic_glink_ss_in: endpoint {
remote-endpoint = <&usb_0_qmpphy_out>;
};
};
};
};
connector@1 {
compatible = "usb-c-connector";
reg = <1>;
power-role = "dual";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
pmic_glink_hs_in1: endpoint {
remote-endpoint = <&usb_1_dwc3_hs>;
};
};
port@1 {
reg = <1>;
pmic_glink_ss_in1: endpoint {
remote-endpoint = <&usb_1_qmpphy_out>;
};
};
};
};
};
vreg_edp_3p3: regulator-edp-3p3 {
compatible = "regulator-fixed";
regulator-name = "VREG_EDP_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&edp_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_misc_3p3: regulator-misc-3p3 {
compatible = "regulator-fixed";
regulator-name = "VREG_MISC_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pmh0110_f_e0_gpios 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&misc_3p3_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
touchpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
hid-descr-addr = <0x20>;
interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
vddl-supply = <&vreg_l15b_e0_1p8>;
pinctrl-0 = <&tpad_default>;
pinctrl-names = "default";
wakeup-source;
};
keyboard@3a {
compatible = "hid-over-i2c";
reg = <0x3a>;
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
vddl-supply = <&vreg_l15b_e0_1p8>;
pinctrl-0 = <&kybd_default>;
pinctrl-names = "default";
wakeup-source;
};
};
&i2c8 {
clock-frequency = <400000>;
status = "okay";
touchscreen@38 {
compatible = "hid-over-i2c";
reg = <0x38>;
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
vddl-supply = <&vreg_l15b_e0_1p8>;
pinctrl-0 = <&ts0_default>;
pinctrl-names = "default";
};
};
&i2c5 {
clock-frequency = <400000>;
status = "okay";
ptn3222_0: redriver@43 {
compatible = "nxp,ptn3222";
reg = <0x43>;
reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
vdd3v3-supply = <&vreg_l8b_e0_1p50>;
vdd1v8-supply = <&vreg_l15b_e0_1p8>;
#phy-cells = <0>;
};
ptn3222_1: redriver@47 {
compatible = "nxp,ptn3222";
reg = <0x47>;
reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
vdd3v3-supply = <&vreg_l8b_e0_1p50>;
vdd1v8-supply = <&vreg_l15b_e0_1p8>;
#phy-cells = <0>;
};
};
&mdss {
status = "okay";
};
&mdss_dp3 {
/delete-property/ #sound-dai-cells;
status = "okay";
aux-bus {
panel {
compatible = "samsung,atna60cl08", "samsung,atna33xc20";
enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
power-supply = <&vreg_edp_3p3>;
pinctrl-0 = <&edp_bl_en>;
pinctrl-names = "default";
port {
edp_panel_in: endpoint {
remote-endpoint = <&mdss_dp3_out>;
};
};
};
};
};
&mdss_dp3_out {
data-lanes = <0 1 2 3>;
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
remote-endpoint = <&edp_panel_in>;
};
&mdss_dp3_phy {
vdda-phy-supply = <&vreg_l2f_e1_0p83>;
vdda-pll-supply = <&vreg_l4f_e1_1p08>;
status = "okay";
};
&pmh0110_f_e0_gpios {
misc_3p3_reg_en: misc-3p3-reg-en-state {
pins = "gpio6";
function = "normal";
bias-disable;
input-disable;
output-enable;
drive-push-pull;
power-source = <1>; /* 1.8 V */
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
};
};
&smb2370_j_e2_eusb2_repeater {
vdd18-supply = <&vreg_l15b_e0_1p8>;
vdd3-supply = <&vreg_l7b_e0_2p79>;
};
&smb2370_k_e2_eusb2_repeater {
vdd18-supply = <&vreg_l15b_e0_1p8>;
vdd3-supply = <&vreg_l7b_e0_2p79>;
};
&tlmm {
edp_bl_en: edp-bl-en-state {
pins = "gpio18";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
edp_reg_en: edp-reg-en-state {
pins = "gpio70";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
kybd_default: kybd-default-state {
pins = "gpio67";
function = "gpio";
bias-disable;
};
tpad_default: tpad-default-state {
pins = "gpio3";
function = "gpio";
bias-disable;
};
ts0_default: ts0-default-state {
int-n-pins {
pins = "gpio51";
function = "gpio";
bias-disable;
};
reset-n-pins {
pins = "gpio48";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
};
};
&usb_0 {
dr_mode = "host";
status = "okay";
};
&usb_0_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};
&usb_0_hsphy {
vdd-supply = <&vreg_l3f_e0_0p72>;
vdda12-supply = <&vreg_l4h_e0_1p2>;
phys = <&smb2370_j_e2_eusb2_repeater>;
status = "okay";
};
&usb_0_qmpphy {
vdda-phy-supply = <&vreg_l4h_e0_1p2>;
vdda-pll-supply = <&vreg_l3f_e0_0p72>;
refgen-supply = <&vreg_l2f_e0_0p82>;
status = "okay";
};
&usb_0_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in>;
};
&usb_1 {
dr_mode = "host";
status = "okay";
};
&usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in1>;
};
&usb_1_hsphy {
vdd-supply = <&vreg_l3f_e0_0p72>;
vdda12-supply = <&vreg_l4h_e0_1p2>;
phys = <&smb2370_k_e2_eusb2_repeater>;
status = "okay";
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l4h_e0_1p2>;
vdda-pll-supply = <&vreg_l1h_e0_0p89>;
refgen-supply = <&vreg_l2f_e0_0p82>;
status = "okay";
};
&usb_1_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in1>;
};
&usb_hs {
status = "okay";
};
&usb_hs_phy {
vdd-supply = <&vreg_l2h_e0_0p72>;
vdda12-supply = <&vreg_l4h_e0_1p2>;
phys = <&ptn3222_1>;
status = "okay";
};
&usb_mp {
status = "okay";
};
&usb_mp_hsphy0 {
vdd-supply = <&vreg_l2h_e0_0p72>;
vdda12-supply = <&vreg_l4h_e0_1p2>;
phys = <&ptn3222_0>;
status = "okay";
};
&usb_mp_hsphy1 {
vdd-supply = <&vreg_l2h_e0_0p72>;
vdda12-supply = <&vreg_l4h_e0_1p2>;
status = "okay";
};
&usb_mp_qmpphy0 {
vdda-phy-supply = <&vreg_l4h_e0_1p2>;
vdda-pll-supply = <&vreg_l2h_e0_0p72>;
refgen-supply = <&vreg_l4f_e1_1p08>;
status = "okay";
};
&usb_mp_qmpphy1 {
vdda-phy-supply = <&vreg_l4h_e0_1p2>;
vdda-pll-supply = <&vreg_l2h_e0_0p72>;
refgen-supply = <&vreg_l4f_e1_1p08>;
status = "okay";
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */
#include "pmh0101.dtsi" /* SPMI0: SID-1 */
#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */
#include "pmh0104-glymur.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */
#include "pmk8850.dtsi" /* SPMI0: SID-0 */
#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */
/ {
model = "Qualcomm Technologies, Inc. Glymur CRD";
compatible = "qcom,glymur-crd", "qcom,glymur";
aliases {
serial0 = &uart21;
serial1 = &uart14;
i2c0 = &i2c0;
i2c1 = &i2c4;
i2c2 = &i2c5;
spi0 = &spi18;
};
chosen {
stdout-path = "serial0:115200n8";
};
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
clock-frequency = <38400000>;
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
#clock-cells = <0>;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&key_vol_up_default>;
pinctrl-names = "default";
key-volume-up {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
gpios = <&pmh0101_gpios 6 GPIO_ACTIVE_LOW>;
debounce-interval = <15>;
linux,can-disable;
wakeup-source;
};
};
vreg_nvme: regulator-nvme {
compatible = "regulator-fixed";
regulator-name = "VREG_NVME_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&nvme_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_nvmesec: regulator-nvmesec {
compatible = "regulator-fixed";
regulator-name = "VREG_NVME_SEC_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pmh0110_f_e1_gpios 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&nvme_sec_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_wcn_0p95: regulator-wcn-0p95 {
compatible = "regulator-fixed";
regulator-name = "VREG_WCN_0P95";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <950000>;
vin-supply = <&vreg_wcn_3p3>;
};
vreg_wcn_3p3: regulator-wcn-3p3 {
compatible = "regulator-fixed";
regulator-name = "VREG_WCN_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 94 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&wcn_sw_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_wwan: regulator-wwan {
compatible = "regulator-fixed";
regulator-name = "VREG_WWAN_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 246 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&wwan_reg_en>;
pinctrl-names = "default";
};
wcn7850-pmu {
compatible = "qcom,wcn7850-pmu";
vdd-supply = <&vreg_wcn_0p95>;
vddio-supply = <&vreg_l15b_e0_1p8>;
vddaon-supply = <&vreg_l15b_e0_1p8>;
vdddig-supply = <&vreg_l15b_e0_1p8>;
vddrfa1p2-supply = <&vreg_l15b_e0_1p8>;
vddrfa1p8-supply = <&vreg_l15b_e0_1p8>;
wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>;
bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&wcn_wlan_bt_en>;
pinctrl-names = "default";
regulators {
vreg_pmu_rfa_cmn: ldo0 {
regulator-name = "vreg_pmu_rfa_cmn";
};
vreg_pmu_aon_0p59: ldo1 {
regulator-name = "vreg_pmu_aon_0p59";
};
vreg_pmu_wlcx_0p8: ldo2 {
regulator-name = "vreg_pmu_wlcx_0p8";
};
vreg_pmu_wlmx_0p85: ldo3 {
regulator-name = "vreg_pmu_wlmx_0p85";
};
vreg_pmu_btcmx_0p85: ldo4 {
regulator-name = "vreg_pmu_btcmx_0p85";
};
vreg_pmu_rfa_0p8: ldo5 {
regulator-name = "vreg_pmu_rfa_0p8";
};
vreg_pmu_rfa_1p2: ldo6 {
regulator-name = "vreg_pmu_rfa_1p2";
};
vreg_pmu_rfa_1p8: ldo7 {
regulator-name = "vreg_pmu_rfa_1p8";
};
vreg_pmu_pcie_0p9: ldo8 {
regulator-name = "vreg_pmu_pcie_0p9";
};
vreg_pmu_pcie_1p8: ldo9 {
regulator-name = "vreg_pmu_pcie_1p8";
};
};
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pmh0101-rpmh-regulators";
qcom,pmic-id = "B_E0";
vreg_bob1_e0: bob1 {
regulator-name = "vreg_bob1_e0";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <4224000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
};
vreg_bob2_e0: bob2 {
regulator-name = "vreg_bob2_e0";
regulator-min-microvolt = <2540000>;
regulator-max-microvolt = <3600000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
};
vreg_l1b_e0_1p8: ldo1 {
regulator-name = "vreg_l1b_e0_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2b_e0_2p9: ldo2 {
regulator-name = "vreg_l2b_e0_2p9";
regulator-min-microvolt = <2904000>;
regulator-max-microvolt = <2904000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7b_e0_2p79: ldo7 {
regulator-name = "vreg_l7b_e0_2p79";
regulator-min-microvolt = <2790000>;
regulator-max-microvolt = <2792000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8b_e0_1p50: ldo8 {
regulator-name = "vreg_l8b_e0_1p50";
regulator-min-microvolt = <1504000>;
regulator-max-microvolt = <1504000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9b_e0_2p7: ldo9 {
regulator-name = "vreg_l9b_e0_2p7";
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2704000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10b_e0_1p8: ldo10 {
regulator-name = "vreg_l10b_e0_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11b_e0_1p2: ldo11 {
regulator-name = "vreg_l11b_e0_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12b_e0_1p14: ldo12 {
regulator-name = "vreg_l12b_e0_1p14";
regulator-min-microvolt = <1144000>;
regulator-max-microvolt = <1144000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l15b_e0_1p8: ldo15 {
regulator-name = "vreg_l15b_e0_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l17b_e0_2p4: ldo17 {
regulator-name = "vreg_l17b_e0_2p4";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <2700000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l18b_e0_1p2: ldo18 {
regulator-name = "vreg_l18b_e0_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-1 {
compatible = "qcom,pmcx0102-rpmh-regulators";
qcom,pmic-id = "C_E1";
vreg_l1c_e1_0p82: ldo1 {
regulator-name = "vreg_l1c_e1_0p82";
regulator-min-microvolt = <832000>;
regulator-max-microvolt = <832000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2c_e1_1p14: ldo2 {
regulator-name = "vreg_l2c_e1_1p14";
regulator-min-microvolt = <1144000>;
regulator-max-microvolt = <1144000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3c_e1_0p89: ldo3 {
regulator-name = "vreg_l3c_e1_0p89";
regulator-min-microvolt = <890000>;
regulator-max-microvolt = <980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c_e1_0p72: ldo4 {
regulator-name = "vreg_l4c_e1_0p72";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <720000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-2 {
compatible = "qcom,pmh0110-rpmh-regulators";
qcom,pmic-id = "F_E0";
vreg_s7f_e0_1p32: smps7 {
regulator-name = "vreg_s7f_e0_1p32";
regulator-min-microvolt = <1320000>;
regulator-max-microvolt = <1352000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s8f_e0_0p95: smps8 {
regulator-name = "vreg_s8f_e0_0p95";
regulator-min-microvolt = <952000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s9f_e0_1p9: smps9 {
regulator-name = "vreg_s9f_e0_1p9";
regulator-min-microvolt = <1900000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2f_e0_0p82: ldo2 {
regulator-name = "vreg_l2f_e0_0p82";
regulator-min-microvolt = <832000>;
regulator-max-microvolt = <832000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3f_e0_0p72: ldo3 {
regulator-name = "vreg_l3f_e0_0p72";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <720000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4f_e0_0p3: ldo4 {
regulator-name = "vreg_l4f_e0_0p3";
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-3 {
compatible = "qcom,pmh0110-rpmh-regulators";
qcom,pmic-id = "F_E1";
vreg_s7f_e1_0p3: smps7 {
regulator-name = "vreg_s7f_e1_0p3";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1f_e1_0p82: ldo1 {
regulator-name = "vreg_l1f_e1_0p82";
regulator-min-microvolt = <832000>;
regulator-max-microvolt = <832000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2f_e1_0p83: ldo2 {
regulator-name = "vreg_l2f_e1_0p83";
regulator-min-microvolt = <832000>;
regulator-max-microvolt = <832000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4f_e1_1p08: ldo4 {
regulator-name = "vreg_l4f_e1_1p08";
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1320000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-4 {
compatible = "qcom,pmh0110-rpmh-regulators";
qcom,pmic-id = "H_E0";
vreg_l1h_e0_0p89: ldo1 {
regulator-name = "vreg_l1h_e0_0p89";
regulator-min-microvolt = <832000>;
regulator-max-microvolt = <832000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2h_e0_0p72: ldo2 {
regulator-name = "vreg_l2h_e0_0p72";
regulator-min-microvolt = <832000>;
regulator-max-microvolt = <832000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3h_e0_0p32: ldo3 {
regulator-name = "vreg_l3h_e0_0p32";
regulator-min-microvolt = <320000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4h_e0_1p2: ldo4 {
regulator-name = "vreg_l4h_e0_1p2";
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1320000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
};
&pcie3b {
vddpe-3v3-supply = <&vreg_nvmesec>;
pinctrl-0 = <&pcie3b_default>;
pinctrl-names = "default";
};
&pcie3b_phy {
vdda-phy-supply = <&vreg_l3c_e1_0p89>;
vdda-pll-supply = <&vreg_l2c_e1_1p14>;
};
&pcie3b_port0 {
reset-gpios = <&tlmm 155 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 157 GPIO_ACTIVE_LOW>;
};
&pcie4 {
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
status = "okay";
};
&pcie4_phy {
vdda-phy-supply = <&vreg_l1c_e1_0p82>;
vdda-pll-supply = <&vreg_l4f_e1_1p08>;
status = "okay";
};
&pcie4_port0 {
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
vddaon-supply = <&vreg_pmu_aon_0p59>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
};
};
&pcie5 {
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie5_default>;
pinctrl-names = "default";
status = "okay";
};
&pcie5_phy {
vdda-phy-supply = <&vreg_l2f_e0_0p82>;
vdda-pll-supply = <&vreg_l4h_e0_1p2>;
status = "okay";
};
&pcie5_port0 {
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
};
&pcie6 {
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-0 = <&pcie6_default>;
pinctrl-names = "default";
status = "okay";
};
&pcie6_phy {
vdda-phy-supply = <&vreg_l1c_e1_0p82>;
vdda-pll-supply = <&vreg_l4f_e1_1p08>;
status = "okay";
};
&pcie6_port0 {
reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
};
&pmh0101_gpios {
nvme_reg_en: nvme-reg-en-state {
pins = "gpio14";
function = "normal";
bias-disable;
};
};
&pmh0110_f_e1_gpios {
nvme_sec_reg_en: nvme-reg-en-state {
pins = "gpio14";
function = "normal";
bias-disable;
};
};
&pmh0101_gpios {
key_vol_up_default: key-vol-up-default-state {
pins = "gpio6";
function = "normal";
output-disable;
bias-pull-up;
};
};
&pmk8850_rtc {
qcom,no-alarm;
};
&pon_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */
<10 2>, /* OOB UART */
<44 4>; /* Security SPI (TPM) */
pcie4_default: pcie4-default-state {
clkreq-n-pins {
pins = "gpio147";
function = "pcie4_clk_req_n";
drive-strength = <2>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio146";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wake-n-pins {
pins = "gpio148";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie5_default: pcie5-default-state {
clkreq-n-pins {
pins = "gpio153";
function = "pcie5_clk_req_n";
drive-strength = <2>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio152";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wake-n-pins {
pins = "gpio154";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie6_default: pcie6-default-state {
clkreq-n-pins {
pins = "gpio150";
function = "pcie6_clk_req_n";
drive-strength = <2>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio149";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wake-n-pins {
pins = "gpio151";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie3b_default: pcie3b-default-state {
clkreq-n-pins {
pins = "gpio156";
function = "pcie3b_clk";
drive-strength = <2>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio155";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wake-n-pins {
pins = "gpio157";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
wcn_wlan_bt_en: wcn-wlan-bt-en-state {
pins = "gpio116", "gpio117";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wcn_sw_en: wcn-sw-en-state {
pins = "gpio94";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wwan_reg_en: wwan-reg-en-state {
pins = "gpio246";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
&uart14 {
status = "okay";
bluetooth {
compatible = "qcom,wcn7850-bt";
max-speed = <3200000>;
vddaon-supply = <&vreg_pmu_aon_0p59>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
};
};

7135
arch/arm64/boot/dts/qcom/glymur.dtsi Normal file
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File diff suppressed because it is too large Load Diff

141
arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
View File

@ -616,6 +616,38 @@ platform {
sound-dai = <&q6apm>;
};
};
dp0-dai-link {
link-name = "DP0 Playback";
codec {
sound-dai = <&mdss_dp0>;
};
cpu {
sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>;
};
platform {
sound-dai = <&q6apm>;
};
};
dp1-dai-link {
link-name = "DP1 Playback";
codec {
sound-dai = <&mdss_dp1>;
};
cpu {
sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>;
};
platform {
sound-dai = <&q6apm>;
};
};
};
usb-1-ss0-sbu-mux {
@ -1102,9 +1134,7 @@ edp_bl_reg_en: edp-bl-reg-en-state {
pins = "gpio10";
function = "normal";
};
};
&pmc8380_3_gpios {
pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state {
pins = "gpio8";
function = "normal";
@ -1144,6 +1174,22 @@ &pmk8550_pwm {
status = "okay";
};
&sdhc_2 {
cd-gpios = <&tlmm 71 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vreg_l9b_2p9>;
vqmmc-supply = <&vreg_l6b_1p8>;
no-sdio;
no-mmc;
pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
pinctrl-names = "default", "sleep";
status = "okay";
};
&smb2360_0 {
status = "okay";
};
@ -1326,6 +1372,13 @@ rtmr2_default: rtmr2-reset-n-active-state {
bias-disable;
};
sdc2_card_det_n: sd-card-det-n-state {
pins = "gpio71";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state {
pins = "gpio188";
function = "gpio";
@ -1461,6 +1514,24 @@ &uart21 {
status = "okay";
};
&ufs_mem_phy {
vdda-phy-supply = <&vreg_l3i_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&ufs_mem_hc {
reset-gpios = <&tlmm 238 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l17b_2p5>;
vcc-max-microamp = <1300000>;
vccq-supply = <&vreg_l2i_1p2>;
vccq-max-microamp = <1200000>;
status = "okay";
};
&usb_1_ss0_dwc3_hs {
remote-endpoint = <&pmic_glink_ss0_hs_in>;
};
@ -1511,3 +1582,69 @@ &usb_mp_hsphy0 {
&usb_mp_hsphy1 {
phys = <&eusb6_repeater>;
};
&thermal_zones {
gpuss-0-thermal {
trips {
trip-point0 {
temperature = <105000>;
};
};
};
gpuss-1-thermal {
trips {
trip-point0 {
temperature = <105000>;
};
};
};
gpuss-2-thermal {
trips {
trip-point0 {
temperature = <105000>;
};
};
};
gpuss-3-thermal {
trips {
trip-point0 {
temperature = <105000>;
};
};
};
gpuss-4-thermal {
trips {
trip-point0 {
temperature = <105000>;
};
};
};
gpuss-5-thermal {
trips {
trip-point0 {
temperature = <105000>;
};
};
};
gpuss-6-thermal {
trips {
trip-point0 {
temperature = <105000>;
};
};
};
gpuss-7-thermal {
trips {
trip-point0 {
temperature = <105000>;
};
};
};
};

30
arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi
View File

@ -447,14 +447,20 @@ &pcie6a_phy {
};
&qupv3_0 {
firmware-name = "qcom/x1e80100/qupv3fw.elf";
status = "okay";
};
&qupv3_1 {
firmware-name = "qcom/x1e80100/qupv3fw.elf";
status = "okay";
};
&qupv3_2 {
firmware-name = "qcom/x1e80100/qupv3fw.elf";
status = "okay";
};
@ -570,12 +576,10 @@ wake-n-pins {
};
&usb_1_ss0 {
status = "okay";
};
&usb_1_ss0_dwc3 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
&usb_1_ss0_hsphy {
@ -593,12 +597,10 @@ &usb_1_ss0_qmpphy {
};
&usb_1_ss1 {
status = "okay";
};
&usb_1_ss1_dwc3 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
&usb_1_ss1_hsphy {
@ -616,12 +618,10 @@ &usb_1_ss1_qmpphy {
};
&usb_1_ss2 {
status = "okay";
};
&usb_1_ss2_dwc3 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
&usb_1_ss2_hsphy {
@ -639,11 +639,9 @@ &usb_1_ss2_qmpphy {
};
&usb_2 {
status = "okay";
};
&usb_2_dwc3 {
dr_mode = "host";
status = "okay";
};
&usb_2_hsphy {

524
arch/arm64/boot/dts/qcom/hamoa.dtsi
View File

@ -75,6 +75,7 @@ cpu0: cpu@0 {
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
l2_0: l2-cache {
compatible = "cache";
@ -91,6 +92,7 @@ cpu1: cpu@100 {
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu2: cpu@200 {
@ -101,6 +103,7 @@ cpu2: cpu@200 {
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd2>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu3: cpu@300 {
@ -111,6 +114,7 @@ cpu3: cpu@300 {
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd3>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu4: cpu@10000 {
@ -121,6 +125,7 @@ cpu4: cpu@10000 {
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd4>, <&scmi_dvfs 1>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
l2_1: l2-cache {
compatible = "cache";
@ -137,6 +142,7 @@ cpu5: cpu@10100 {
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd5>, <&scmi_dvfs 1>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu6: cpu@10200 {
@ -147,6 +153,7 @@ cpu6: cpu@10200 {
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd6>, <&scmi_dvfs 1>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu7: cpu@10300 {
@ -157,6 +164,7 @@ cpu7: cpu@10300 {
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd7>, <&scmi_dvfs 1>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu8: cpu@20000 {
@ -167,6 +175,7 @@ cpu8: cpu@20000 {
next-level-cache = <&l2_2>;
power-domains = <&cpu_pd8>, <&scmi_dvfs 2>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
l2_2: l2-cache {
compatible = "cache";
@ -183,6 +192,7 @@ cpu9: cpu@20100 {
next-level-cache = <&l2_2>;
power-domains = <&cpu_pd9>, <&scmi_dvfs 2>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu10: cpu@20200 {
@ -193,6 +203,7 @@ cpu10: cpu@20200 {
next-level-cache = <&l2_2>;
power-domains = <&cpu_pd10>, <&scmi_dvfs 2>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu11: cpu@20300 {
@ -203,6 +214,7 @@ cpu11: cpu@20300 {
next-level-cache = <&l2_2>;
power-domains = <&cpu_pd11>, <&scmi_dvfs 2>;
power-domain-names = "psci", "perf";
#cooling-cells = <2>;
};
cpu-map {
@ -835,9 +847,9 @@ gcc: clock-controller@100000 {
<0>,
<0>,
<0>,
<0>,
<0>,
<0>;
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
@ -3869,6 +3881,122 @@ pcie4_phy: phy@1c0e000 {
status = "disabled";
};
ufs_mem_phy: phy@1d80000 {
compatible = "qcom,x1e80100-qmp-ufs-phy",
"qcom,sm8550-qmp-ufs-phy";
reg = <0x0 0x01d80000 0x0 0x2000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&tcsr TCSR_UFS_PHY_CLKREF_EN>;
clock-names = "ref",
"ref_aux",
"qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
#clock-cells = <1>;
#phy-cells = <0>;
status = "disabled";
};
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,x1e80100-ufshc",
"qcom,sm8550-ufshc",
"qcom,ufshc";
reg = <0x0 0x01d84000 0x0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&rpmhcc RPMH_LN_BB_CLK3>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
clock-names = "core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
operating-points-v2 = <&ufs_opp_table>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "ufs-ddr",
"cpu-ufs";
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
iommus = <&apps_smmu 0x1a0 0>;
dma-coherent;
lanes-per-direction = <2>;
phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
#reset-cells = <1>;
status = "disabled";
ufs_opp_table: opp-table {
compatible = "operating-points-v2";
opp-75000000 {
opp-hz = /bits/ 64 <75000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <75000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-150000000 {
opp-hz = /bits/ 64 <150000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <150000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <300000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x0 0x01dc4000 0x0 0x28000>;
@ -4714,7 +4842,7 @@ sdhc_2: mmc@8804000 {
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
<&bi_tcxo_div2>;
clock-names = "iface", "core", "xo";
iommus = <&apps_smmu 0x520 0>;
qcom,dll-config = <0x0007642c>;
@ -4767,7 +4895,7 @@ sdhc_4: mmc@8844000 {
clocks = <&gcc GCC_SDCC4_AHB_CLK>,
<&gcc GCC_SDCC4_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
<&bi_tcxo_div2>;
clock-names = "iface", "core", "xo";
iommus = <&apps_smmu 0x160 0>;
qcom,dll-config = <0x0007642c>;
@ -4908,9 +5036,9 @@ usb_mp_qmpphy1: phy@88e5000 {
status = "disabled";
};
usb_1_ss2: usb@a0f8800 {
compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
reg = <0 0x0a0f8800 0 0x400>;
usb_1_ss2: usb@a000000 {
compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3";
reg = <0 0x0a000000 0 0xfc100>;
clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>,
<&gcc GCC_USB30_TERT_MASTER_CLK>,
@ -4936,11 +5064,13 @@ usb_1_ss2: usb@a0f8800 {
assigned-clock-rates = <19200000>,
<200000000>;
interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 58 IRQ_TYPE_EDGE_BOTH>,
<&pdc 57 IRQ_TYPE_EDGE_BOTH>,
<&pdc 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
interrupt-names = "dwc_usb3",
"pwr_event",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
@ -4959,61 +5089,47 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
wakeup-source;
#address-cells = <2>;
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x14a0 0x0>;
phys = <&usb_1_ss2_hsphy>,
<&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy",
"usb3-phy";
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,usb3_lpm_capable;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
dma-coherent;
status = "disabled";
usb_1_ss2_dwc3: usb@a000000 {
compatible = "snps,dwc3";
reg = <0 0x0a000000 0 0xcd00>;
ports {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
port@0 {
reg = <0>;
iommus = <&apps_smmu 0x14a0 0x0>;
phys = <&usb_1_ss2_hsphy>,
<&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy",
"usb3-phy";
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,usb3_lpm_capable;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
dma-coherent;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_1_ss2_dwc3_hs: endpoint {
};
usb_1_ss2_dwc3_hs: endpoint {
};
};
port@1 {
reg = <1>;
port@1 {
reg = <1>;
usb_1_ss2_dwc3_ss: endpoint {
remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
};
usb_1_ss2_dwc3_ss: endpoint {
remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
};
};
};
};
usb_2: usb@a2f8800 {
compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
reg = <0 0x0a2f8800 0 0x400>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
usb_2: usb@a200000 {
compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3";
reg = <0 0x0a200000 0 0xfc100>;
clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
<&gcc GCC_USB20_MASTER_CLK>,
@ -5038,10 +5154,12 @@ usb_2: usb@a2f8800 {
<&gcc GCC_USB20_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 50 IRQ_TYPE_EDGE_BOTH>,
<&pdc 49 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "pwr_event",
interrupt-names = "dwc_usb3",
"pwr_event",
"dp_hs_phy_irq",
"dm_hs_phy_irq";
@ -5060,31 +5178,26 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
qcom,select-utmi-as-pipe-clk;
wakeup-source;
iommus = <&apps_smmu 0x14e0 0x0>;
phys = <&usb_2_hsphy>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
dma-coherent;
status = "disabled";
usb_2_dwc3: usb@a200000 {
compatible = "snps,dwc3";
reg = <0 0x0a200000 0 0xcd00>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0x14e0 0x0>;
phys = <&usb_2_hsphy>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
dma-coherent;
port {
usb_2_dwc3_hs: endpoint {
};
port {
usb_2_dwc3_hs: endpoint {
};
};
};
usb_mp: usb@a4f8800 {
compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3";
reg = <0 0x0a4f8800 0 0x400>;
usb_mp: usb@a400000 {
compatible = "qcom,x1e80100-dwc3-mp", "qcom,snps-dwc3";
reg = <0 0x0a400000 0 0xfc100>;
clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
<&gcc GCC_USB30_MP_MASTER_CLK>,
@ -5110,7 +5223,8 @@ usb_mp: usb@a4f8800 {
assigned-clock-rates = <19200000>,
<200000000>;
interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
@ -5120,7 +5234,8 @@ usb_mp: usb@a4f8800 {
<&pdc 53 IRQ_TYPE_EDGE_BOTH>,
<&pdc 55 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 56 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event_1", "pwr_event_2",
interrupt-names = "dwc_usb3",
"pwr_event_1", "pwr_event_2",
"hs_phy_1", "hs_phy_2",
"dp_hs_phy_1", "dm_hs_phy_1",
"dp_hs_phy_2", "dm_hs_phy_2",
@ -5140,39 +5255,28 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
wakeup-source;
#address-cells = <2>;
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x1400 0x0>;
phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>,
<&usb_mp_hsphy1>, <&usb_mp_qmpphy1>;
phy-names = "usb2-0", "usb3-0",
"usb2-1", "usb3-1";
dr_mode = "host";
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,usb3_lpm_capable;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
dma-coherent;
status = "disabled";
usb_mp_dwc3: usb@a400000 {
compatible = "snps,dwc3";
reg = <0 0x0a400000 0 0xcd00>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0x1400 0x0>;
phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>,
<&usb_mp_hsphy1>, <&usb_mp_qmpphy1>;
phy-names = "usb2-0", "usb3-0",
"usb2-1", "usb3-1";
dr_mode = "host";
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,usb3_lpm_capable;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
dma-coherent;
};
};
usb_1_ss0: usb@a6f8800 {
compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
usb_1_ss0: usb@a600000 {
compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3";
reg = <0 0x0a600000 0 0xfc100>;
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
@ -5198,11 +5302,13 @@ usb_1_ss0: usb@a6f8800 {
assigned-clock-rates = <19200000>,
<200000000>;
interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 61 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
interrupt-names = "dwc_usb3",
"pwr_event",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
@ -5214,58 +5320,47 @@ usb_1_ss0: usb@a6f8800 {
wakeup-source;
#address-cells = <2>;
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x1420 0x0>;
phys = <&usb_1_ss0_hsphy>,
<&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy",
"usb3-phy";
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,usb3_lpm_capable;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
dma-coherent;
status = "disabled";
usb_1_ss0_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
ports {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
port@0 {
reg = <0>;
iommus = <&apps_smmu 0x1420 0x0>;
phys = <&usb_1_ss0_hsphy>,
<&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy",
"usb3-phy";
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,usb3_lpm_capable;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
dma-coherent;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_1_ss0_dwc3_hs: endpoint {
};
usb_1_ss0_dwc3_hs: endpoint {
};
};
port@1 {
reg = <1>;
port@1 {
reg = <1>;
usb_1_ss0_dwc3_ss: endpoint {
remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
};
usb_1_ss0_dwc3_ss: endpoint {
remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
};
};
};
};
usb_1_ss1: usb@a8f8800 {
compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
reg = <0 0x0a8f8800 0 0x400>;
usb_1_ss1: usb@a800000 {
compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3";
reg = <0 0x0a800000 0 0xfc100>;
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_MASTER_CLK>,
@ -5291,11 +5386,13 @@ usb_1_ss1: usb@a8f8800 {
assigned-clock-rates = <19200000>,
<200000000>;
interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 60 IRQ_TYPE_EDGE_BOTH>,
<&pdc 11 IRQ_TYPE_EDGE_BOTH>,
<&pdc 47 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
interrupt-names = "dwc_usb3",
"pwr_event",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
@ -5314,50 +5411,39 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
wakeup-source;
#address-cells = <2>;
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x1460 0x0>;
phys = <&usb_1_ss1_hsphy>,
<&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy",
"usb3-phy";
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,usb3_lpm_capable;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
dma-coherent;
status = "disabled";
usb_1_ss1_dwc3: usb@a800000 {
compatible = "snps,dwc3";
reg = <0 0x0a800000 0 0xcd00>;
ports {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
port@0 {
reg = <0>;
iommus = <&apps_smmu 0x1460 0x0>;
phys = <&usb_1_ss1_hsphy>,
<&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy",
"usb3-phy";
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,usb3_lpm_capable;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
dma-coherent;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_1_ss1_dwc3_hs: endpoint {
};
usb_1_ss1_dwc3_hs: endpoint {
};
};
port@1 {
reg = <1>;
port@1 {
reg = <1>;
usb_1_ss1_dwc3_ss: endpoint {
remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
};
usb_1_ss1_dwc3_ss: endpoint {
remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
};
};
};
@ -5432,19 +5518,19 @@ opp-338000000 {
opp-366000000 {
opp-hz = /bits/ 64 <366000000>;
required-opps = <&rpmhpd_opp_svs_l1>,
required-opps = <&rpmhpd_opp_svs>,
<&rpmhpd_opp_svs_l1>;
};
opp-444000000 {
opp-hz = /bits/ 64 <444000000>;
required-opps = <&rpmhpd_opp_nom>,
required-opps = <&rpmhpd_opp_svs_l1>,
<&rpmhpd_opp_nom>;
};
opp-481000000 {
opp-hz = /bits/ 64 <481000000>;
required-opps = <&rpmhpd_opp_turbo>,
required-opps = <&rpmhpd_opp_svs_l1>,
<&rpmhpd_opp_turbo>;
};
};
@ -5658,8 +5744,8 @@ mdss_dp0_out: endpoint {
mdss_dp0_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-162000000 {
opp-hz = /bits/ 64 <162000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
@ -5747,8 +5833,8 @@ mdss_dp1_out: endpoint {
mdss_dp1_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-162000000 {
opp-hz = /bits/ 64 <162000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
@ -5835,8 +5921,8 @@ mdss_dp2_out: endpoint {
mdss_dp2_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-162000000 {
opp-hz = /bits/ 64 <162000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
@ -5918,8 +6004,8 @@ mdss_dp3_out: endpoint {
mdss_dp3_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-162000000 {
opp-hz = /bits/ 64 <162000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
@ -9230,7 +9316,7 @@ aoss0-critical {
};
};
cpu2-0-top-thermal {
thermal_cpu2_0_top: cpu2-0-top-thermal {
thermal-sensors = <&tsens2 1>;
trips {
@ -9242,7 +9328,7 @@ cpu-critical {
};
};
cpu2-0-btm-thermal {
thermal_cpu2_0_btm: cpu2-0-btm-thermal {
thermal-sensors = <&tsens2 2>;
trips {
@ -9254,7 +9340,7 @@ cpu-critical {
};
};
cpu2-1-top-thermal {
thermal_cpu2_1_top: cpu2-1-top-thermal {
thermal-sensors = <&tsens2 3>;
trips {
@ -9266,7 +9352,7 @@ cpu-critical {
};
};
cpu2-1-btm-thermal {
thermal_cpu2_1_btm: cpu2-1-btm-thermal {
thermal-sensors = <&tsens2 4>;
trips {
@ -9278,7 +9364,7 @@ cpu-critical {
};
};
cpu2-2-top-thermal {
thermal_cpu2_2_top: cpu2-2-top-thermal {
thermal-sensors = <&tsens2 5>;
trips {
@ -9290,7 +9376,7 @@ cpu-critical {
};
};
cpu2-2-btm-thermal {
thermal_cpu2_2_btm: cpu2-2-btm-thermal {
thermal-sensors = <&tsens2 6>;
trips {
@ -9302,7 +9388,7 @@ cpu-critical {
};
};
cpu2-3-top-thermal {
thermal_cpu2_3_top: cpu2-3-top-thermal {
thermal-sensors = <&tsens2 7>;
trips {
@ -9314,7 +9400,7 @@ cpu-critical {
};
};
cpu2-3-btm-thermal {
thermal_cpu2_3_btm: cpu2-3-btm-thermal {
thermal-sensors = <&tsens2 8>;
trips {
@ -9326,7 +9412,7 @@ cpu-critical {
};
};
cpuss2-top-thermal {
thermal_cpuss2_top: cpuss2-top-thermal {
thermal-sensors = <&tsens2 9>;
trips {
@ -9338,7 +9424,7 @@ cpuss2-critical {
};
};
cpuss2-btm-thermal {
thermal_cpuss2_btm: cpuss2-btm-thermal {
thermal-sensors = <&tsens2 10>;
trips {
@ -9350,7 +9436,7 @@ cpuss2-critical {
};
};
aoss3-thermal {
thermal_aoss3: aoss3-thermal {
thermal-sensors = <&tsens3 0>;
trips {
@ -9368,7 +9454,7 @@ aoss0-critical {
};
};
nsp0-thermal {
thermal_nsp0: nsp0-thermal {
thermal-sensors = <&tsens3 1>;
trips {
@ -9386,7 +9472,7 @@ nsp0-critical {
};
};
nsp1-thermal {
thermal_nsp1: nsp1-thermal {
thermal-sensors = <&tsens3 2>;
trips {
@ -9404,7 +9490,7 @@ nsp1-critical {
};
};
nsp2-thermal {
thermal_nsp2: nsp2-thermal {
thermal-sensors = <&tsens3 3>;
trips {
@ -9422,7 +9508,7 @@ nsp2-critical {
};
};
nsp3-thermal {
thermal_nsp3: nsp3-thermal {
thermal-sensors = <&tsens3 4>;
trips {
@ -9440,7 +9526,7 @@ nsp3-critical {
};
};
gpuss-0-thermal {
thermal_gpuss_0: gpuss-0-thermal {
polling-delay-passive = <200>;
thermal-sensors = <&tsens3 5>;
@ -9467,7 +9553,7 @@ gpu-critical {
};
};
gpuss-1-thermal {
thermal_gpuss_1: gpuss-1-thermal {
polling-delay-passive = <200>;
thermal-sensors = <&tsens3 6>;
@ -9494,7 +9580,7 @@ gpu-critical {
};
};
gpuss-2-thermal {
thermal_gpuss_2: gpuss-2-thermal {
polling-delay-passive = <200>;
thermal-sensors = <&tsens3 7>;
@ -9521,7 +9607,7 @@ gpu-critical {
};
};
gpuss-3-thermal {
thermal_gpuss_3: gpuss-3-thermal {
polling-delay-passive = <200>;
thermal-sensors = <&tsens3 8>;
@ -9548,7 +9634,7 @@ gpu-critical {
};
};
gpuss-4-thermal {
thermal_gpuss_4: gpuss-4-thermal {
polling-delay-passive = <200>;
thermal-sensors = <&tsens3 9>;
@ -9575,7 +9661,7 @@ gpu-critical {
};
};
gpuss-5-thermal {
thermal_gpuss_5: gpuss-5-thermal {
polling-delay-passive = <200>;
thermal-sensors = <&tsens3 10>;
@ -9602,7 +9688,7 @@ gpu-critical {
};
};
gpuss-6-thermal {
thermal_gpuss_6: gpuss-6-thermal {
polling-delay-passive = <200>;
thermal-sensors = <&tsens3 11>;
@ -9629,7 +9715,7 @@ gpu-critical {
};
};
gpuss-7-thermal {
thermal_gpuss_7: gpuss-7-thermal {
polling-delay-passive = <200>;
thermal-sensors = <&tsens3 12>;
@ -9656,7 +9742,7 @@ gpu-critical {
};
};
camera0-thermal {
thermal_camera0: camera0-thermal {
thermal-sensors = <&tsens3 13>;
trips {
@ -9674,7 +9760,7 @@ camera0-critical {
};
};
camera1-thermal {
thermal_camera1: camera1-thermal {
thermal-sensors = <&tsens3 14>;
trips {

79
arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts Normal file
View File

@ -0,0 +1,79 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/dts-v1/;
#include "ipq5210.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ5210 RDP504";
compatible = "qcom,ipq5210-rdp504", "qcom,ipq5210";
aliases {
serial0 = &uart1;
};
chosen {
stdout-path = "serial0";
};
};
&sdhc {
max-frequency = <192000000>;
bus-width = <4>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
pinctrl-0 = <&sdhc_default_state>;
pinctrl-names = "default";
status = "okay";
};
&sleep_clk {
clock-frequency = <32000>;
};
&tlmm {
qup_uart1_default_state: qup-uart1-default-state {
pins = "gpio38", "gpio39";
function = "qup_se1";
drive-strength = <6>;
bias-pull-down;
};
sdhc_default_state: sdhc-default-state {
clk-pins {
pins = "gpio5";
function = "sdc_clk";
drive-strength = <8>;
bias-disable;
};
cmd-pins {
pins = "gpio4";
function = "sdc_cmd";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "sdc_data";
drive-strength = <8>;
bias-pull-up;
};
};
};
&uart1 {
pinctrl-0 = <&qup_uart1_default_state>;
pinctrl-names = "default";
status = "okay";
};
&xo_board {
clock-frequency = <24000000>;
};

311
arch/arm64/boot/dts/qcom/ipq5210.dtsi Normal file
View File

@ -0,0 +1,311 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,ipq5210-gcc.h>
#include <dt-bindings/reset/qcom,ipq5210-gcc.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&intc>;
clocks {
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
xo_board: xo-board-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&l2_0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&l2_0>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
enable-method = "psci";
next-level-cache = <&l2_0>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
enable-method = "psci";
next-level-cache = <&l2_0>;
};
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
scm {
compatible = "qcom,scm-ipq5210", "qcom,scm";
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0x0 0x80000000 0x0 0x0>;
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bootloader@87800000 {
reg = <0x0 0x87800000 0x0 0x400000>;
no-map;
};
smem@87c00000 {
compatible = "qcom,smem";
reg = <0x0 0x87c00000 0x0 0x40000>;
no-map;
hwlocks = <&tcsr_mutex 3>;
};
tfa@87d00000 {
reg = <0x0 0x87d00000 0x0 0x80000>;
no-map;
};
optee@87d80000 {
reg = <0x0 0x87d80000 0x0 0x280000>;
no-map;
};
};
soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges = <0 0 0 0 0x10 0>;
ranges = <0 0 0 0 0x10 0>;
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5210-tlmm";
reg = <0x0 0x01000000 0x0 0x300000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 54>;
interrupt-controller;
#interrupt-cells = <2>;
};
gcc: clock-controller@1800000 {
compatible = "qcom,ipq5210-gcc";
reg = <0x0 0x01800000 0x0 0x40000>;
clocks = <&xo_board>,
<&sleep_clk>,
<0>,
<0>,
<0>,
<0>;
#clock-cells = <1>;
#reset-cells = <1>;
};
tcsr_mutex: hwlock@1905000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01905000 0x0 0x20000>;
#hwlock-cells = <1>;
};
qupv3: geniqup@1ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x01ac0000 0x0 0x2000>;
clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
<&gcc GCC_QUPV3_AHB_SLV_CLK>;
clock-names = "m-ahb", "s-ahb";
ranges;
#address-cells = <2>;
#size-cells = <2>;
uart1: serial@1a84000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x01a84000 0x0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP_SE1_CLK>;
clock-names = "se";
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
sdhc: mmc@7804000 {
compatible = "qcom,ipq5210-sdhci", "qcom,sdhci-msm-v5";
reg = <0x0 0x07804000 0x0 0x1000>,
<0x0 0x07805000 0x0 0x1000>;
reg-names = "hc",
"cqhci";
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq",
"pwr_irq";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board>;
clock-names = "iface",
"core",
"xo";
non-removable;
status = "disabled";
};
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x0 0xb000000 0x0 0x1000>,
<0x0 0xb002000 0x0 0x1000>,
<0x0 0xb001000 0x0 0x1000>,
<0x0 0xb004000 0x0 0x1000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0x0b00c000 0 0x3000>;
v2m0: v2m@0 {
compatible = "arm,gic-v2m-frame";
reg = <0x0 0x0 0x0 0xffd>;
msi-controller;
};
v2m1: v2m@1000 {
compatible = "arm,gic-v2m-frame";
reg = <0x0 0x00001000 0x0 0xffd>;
msi-controller;
};
v2m2: v2m@2000 {
compatible = "arm,gic-v2m-frame";
reg = <0x0 0x00002000 0x0 0xffd>;
msi-controller;
};
};
timer@b120000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x0b120000 0x0 0x1000>;
ranges = <0 0 0 0x10000000>;
#address-cells = <1>;
#size-cells = <1>;
frame@b121000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b121000 0x1000>,
<0x0b122000 0x1000>;
};
frame@b123000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b123000 0x1000>;
status = "disabled";
};
frame@b124000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b124000 0x1000>;
status = "disabled";
};
frame@b125000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b125000 0x1000>;
status = "disabled";
};
frame@b126000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b126000 0x1000>;
status = "disabled";
};
frame@b127000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b127000 0x1000>;
status = "disabled";
};
frame@b128000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b128000 0x1000>;
status = "disabled";
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};

44
arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi
View File

@ -78,4 +78,48 @@ gpio_leds_default: gpio-leds-default-state {
drive-strength = <8>;
bias-pull-down;
};
qpic_snand_default_state: qpic-snand-default-state {
clock-pins {
pins = "gpio13";
function = "qspi_clk";
drive-strength = <8>;
bias-disable;
};
cs-pins {
pins = "gpio12";
function = "qspi_cs";
drive-strength = <8>;
bias-disable;
};
data-pins {
pins = "gpio8", "gpio9", "gpio10", "gpio11";
function = "qspi_data";
drive-strength = <8>;
bias-disable;
};
};
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
pinctrl-0 = <&qpic_snand_default_state>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
nand-ecc-engine = <&qpic_nand>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
};
};

34
arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts
View File

@ -35,17 +35,6 @@ flash@0 {
};
};
&sdhc {
bus-width = <4>;
max-frequency = <192000000>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";
status = "okay";
};
&tlmm {
i2c_1_pins: i2c-1-state {
pins = "gpio29", "gpio30";
@ -54,29 +43,6 @@ i2c_1_pins: i2c-1-state {
bias-pull-up;
};
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio13";
function = "sdc_clk";
drive-strength = <8>;
bias-disable;
};
cmd-pins {
pins = "gpio12";
function = "sdc_cmd";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "gpio8", "gpio9", "gpio10", "gpio11";
function = "sdc_data";
drive-strength = <8>;
bias-pull-up;
};
};
spi_0_data_clk_pins: spi-0-data-clk-state {
pins = "gpio14", "gpio15", "gpio16";
function = "blsp0_spi";

33
arch/arm64/boot/dts/qcom/ipq5332.dtsi
View File

@ -423,6 +423,39 @@ blsp1_spi2: spi@78b7000 {
status = "disabled";
};
qpic_bam: dma-controller@7984000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x07984000 0x1c000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QPIC_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
status = "disabled";
};
qpic_nand: spi@79b0000 {
compatible = "qcom,ipq5332-snand", "qcom,ipq9574-snand";
reg = <0x079b0000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gcc GCC_QPIC_CLK>,
<&gcc GCC_QPIC_AHB_CLK>,
<&gcc GCC_QPIC_IO_MACRO_CLK>;
clock-names = "core",
"aon",
"iom";
dmas = <&qpic_bam 0>,
<&qpic_bam 1>,
<&qpic_bam 2>;
dma-names = "tx",
"rx",
"cmd";
status = "disabled";
};
usb: usb@8af8800 {
compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
reg = <0x08af8800 0x400>;

44
arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
View File

@ -124,13 +124,6 @@ &qusb_phy_1 {
status = "okay";
};
&sdhc {
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";
status = "okay";
};
&sleep_clk {
clock-frequency = <32000>;
};
@ -201,26 +194,26 @@ mosi-pins {
};
};
sdc_default_state: sdc-default-state {
clk-pins {
qpic_snand_default_state: qpic-snand-default-state {
clock-pins {
pins = "gpio5";
function = "sdc_clk";
function = "qspi_clk";
drive-strength = <8>;
bias-disable;
bias-pull-down;
};
cmd-pins {
cs-pins {
pins = "gpio4";
function = "sdc_cmd";
function = "qspi_cs";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "sdc_data";
function = "qspi_data";
drive-strength = <8>;
bias-pull-up;
bias-pull-down;
};
};
@ -246,6 +239,27 @@ pcie3_default_state: pcie3-default-state {
};
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
pinctrl-0 = <&qpic_snand_default_state>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
nand-ecc-engine = <&qpic_nand>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
};
};
&uart0 {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";

33
arch/arm64/boot/dts/qcom/ipq5424.dtsi
View File

@ -572,6 +572,39 @@ sdhc: mmc@7804000 {
status = "disabled";
};
qpic_bam: dma-controller@7984000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x0 0x07984000 0x0 0x1c000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QPIC_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
status = "disabled";
};
qpic_nand: spi@79b0000 {
compatible = "qcom,ipq5424-snand", "qcom,ipq9574-snand";
reg = <0x0 0x079b0000 0x0 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gcc GCC_QPIC_CLK>,
<&gcc GCC_QPIC_AHB_CLK>,
<&gcc GCC_QPIC_IO_MACRO_CLK>;
clock-names = "core",
"aon",
"iom";
dmas = <&qpic_bam 0>,
<&qpic_bam 1>,
<&qpic_bam 2>;
dma-names = "tx",
"rx",
"cmd";
status = "disabled";
};
intc: interrupt-controller@f200000 {
compatible = "arm,gic-v3";
reg = <0 0xf200000 0 0x10000>, /* GICD */

66
arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
View File

@ -22,6 +22,15 @@ chosen {
stdout-path = "serial0:115200n8";
};
regulator_fixed_1p8: s1800 {
compatible = "regulator-fixed";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-name = "fixed_1p8";
};
regulator_fixed_3p3: s3300 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
@ -88,11 +97,27 @@ &blsp1_uart2 {
status = "okay";
};
&cpu0 {
cpu-supply = <&mp5496_s1>;
};
&cpu1 {
cpu-supply = <&mp5496_s1>;
};
&cpu2 {
cpu-supply = <&mp5496_s1>;
};
&cpu3 {
cpu-supply = <&mp5496_s1>;
};
&rpm_requests {
regulators {
compatible = "qcom,rpm-mp5496-regulators";
ipq9574_s1: s1 {
mp5496_s1: s1 {
/*
* During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
* During regulator registration, kernel not knowing the initial voltage,
@ -121,6 +146,11 @@ mp5496_l5: l5 {
};
};
&sdhc_1 {
vmmc-supply = <&regulator_fixed_3p3>;
vqmmc-supply = <&regulator_fixed_1p8>;
};
&sleep_clk {
clock-frequency = <32000>;
};
@ -169,6 +199,38 @@ data-pins {
bias-disable;
};
};
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio5";
function = "sdc_clk";
drive-strength = <8>;
bias-disable;
};
cmd-pins {
pins = "gpio4";
function = "sdc_cmd";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "gpio0", "gpio1", "gpio2",
"gpio3", "gpio6", "gpio7",
"gpio8", "gpio9";
function = "sdc_data";
drive-strength = <8>;
bias-pull-up;
};
rclk-pins {
pins = "gpio10";
function = "sdc_rclk";
drive-strength = <8>;
bias-pull-down;
};
};
};
&qpic_bam {
@ -179,8 +241,6 @@ &qpic_nand {
pinctrl-0 = <&qpic_snand_default_state>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;

20
arch/arm64/boot/dts/qcom/ipq9574-rdp418-emmc.dts Normal file
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@ -0,0 +1,20 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* IPQ9574 RDP418 (eMMC variant) board device tree source
*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/dts-v1/;
#include "ipq9574-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2 (eMMC)";
compatible = "qcom,ipq9574-ap-al02-c2-emmc", "qcom,ipq9574";
};
&sdhc_1 {
status = "okay";
};

44
arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts
View File

@ -16,48 +16,6 @@ / {
};
&sdhc_1 {
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
max-frequency = <384000000>;
bus-width = <8>;
&qpic_nand {
status = "okay";
};
&tlmm {
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio5";
function = "sdc_clk";
drive-strength = <8>;
bias-disable;
};
cmd-pins {
pins = "gpio4";
function = "sdc_cmd";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "gpio0", "gpio1", "gpio2",
"gpio3", "gpio6", "gpio7",
"gpio8", "gpio9";
function = "sdc_data";
drive-strength = <8>;
bias-pull-up;
};
rclk-pins {
pins = "gpio10";
function = "sdc_rclk";
drive-strength = <8>;
bias-pull-down;
};
};
};

121
arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi Normal file
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@ -0,0 +1,121 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* IPQ9574 RDP433 board device tree source
*
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&pcie1_phy {
status = "okay";
};
&pcie1 {
pinctrl-0 = <&pcie1_default>;
pinctrl-names = "default";
perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcie2_phy {
status = "okay";
};
&pcie2 {
pinctrl-0 = <&pcie2_default>;
pinctrl-names = "default";
perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcie3_phy {
status = "okay";
};
&pcie3 {
pinctrl-0 = <&pcie3_default>;
pinctrl-names = "default";
perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
status = "okay";
};
&tlmm {
pcie1_default: pcie1-default-state {
clkreq-n-pins {
pins = "gpio25";
function = "pcie1_clk";
drive-strength = <6>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio26";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
output-low;
};
wake-n-pins {
pins = "gpio27";
function = "pcie1_wake";
drive-strength = <6>;
bias-pull-up;
};
};
pcie2_default: pcie2-default-state {
clkreq-n-pins {
pins = "gpio28";
function = "pcie2_clk";
drive-strength = <6>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio29";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
output-low;
};
wake-n-pins {
pins = "gpio30";
function = "pcie2_wake";
drive-strength = <6>;
bias-pull-up;
};
};
pcie3_default: pcie3-default-state {
clkreq-n-pins {
pins = "gpio31";
function = "pcie3_clk";
drive-strength = <6>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio32";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
output-low;
};
wake-n-pins {
pins = "gpio33";
function = "pcie3_wake";
drive-strength = <6>;
bias-pull-up;
};
};
};

20
arch/arm64/boot/dts/qcom/ipq9574-rdp433-emmc.dts Normal file
View File

@ -0,0 +1,20 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* IPQ9574 RDP433 (eMMC variant) board device tree source
*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/dts-v1/;
#include "ipq9574-rdp-common.dtsi"
#include "ipq9574-rdp433-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7 (eMMC)";
compatible = "qcom,ipq9574-ap-al02-c7-emmc", "qcom,ipq9574";
};
&sdhc_1 {
status = "okay";
};

114
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
View File

@ -8,124 +8,14 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "ipq9574-rdp-common.dtsi"
#include "ipq9574-rdp433-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
};
&pcie1_phy {
&qpic_nand {
status = "okay";
};
&pcie1 {
pinctrl-0 = <&pcie1_default>;
pinctrl-names = "default";
perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcie2_phy {
status = "okay";
};
&pcie2 {
pinctrl-0 = <&pcie2_default>;
pinctrl-names = "default";
perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcie3_phy {
status = "okay";
};
&pcie3 {
pinctrl-0 = <&pcie3_default>;
pinctrl-names = "default";
perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
status = "okay";
};
&tlmm {
pcie1_default: pcie1-default-state {
clkreq-n-pins {
pins = "gpio25";
function = "pcie1_clk";
drive-strength = <6>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio26";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
output-low;
};
wake-n-pins {
pins = "gpio27";
function = "pcie1_wake";
drive-strength = <6>;
bias-pull-up;
};
};
pcie2_default: pcie2-default-state {
clkreq-n-pins {
pins = "gpio28";
function = "pcie2_clk";
drive-strength = <6>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio29";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
output-low;
};
wake-n-pins {
pins = "gpio30";
function = "pcie2_wake";
drive-strength = <6>;
bias-pull-up;
};
};
pcie3_default: pcie3-default-state {
clkreq-n-pins {
pins = "gpio31";
function = "pcie3_clk";
drive-strength = <6>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio32";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
output-low;
};
wake-n-pins {
pins = "gpio33";
function = "pcie3_wake";
drive-strength = <6>;
bias-pull-up;
};
};
};

4
arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts
View File

@ -15,3 +15,7 @@ / {
compatible = "qcom,ipq9574-ap-al02-c6", "qcom,ipq9574";
};
&qpic_nand {
status = "okay";
};

4
arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts
View File

@ -15,3 +15,7 @@ / {
compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574";
};
&qpic_nand {
status = "okay";
};

4
arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
View File

@ -14,3 +14,7 @@ / {
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9";
compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574";
};
&qpic_nand {
status = "okay";
};

13
arch/arm64/boot/dts/qcom/ipq9574.dtsi
View File

@ -56,7 +56,6 @@ cpu0: cpu@0 {
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
#cooling-cells = <2>;
};
@ -69,7 +68,6 @@ cpu1: cpu@1 {
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
#cooling-cells = <2>;
};
@ -82,7 +80,6 @@ cpu2: cpu@2 {
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
#cooling-cells = <2>;
};
@ -95,7 +92,6 @@ cpu3: cpu@3 {
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
#cooling-cells = <2>;
};
@ -467,6 +463,15 @@ sdhc_1: mmc@7804000 {
clock-names = "iface", "core", "xo", "ice";
non-removable;
supports-cqe;
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
max-frequency = <384000000>;
bus-width = <8>;
status = "disabled";
};

571
arch/arm64/boot/dts/qcom/kaanapali-mtp.dts
View File

@ -5,9 +5,21 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "kaanapali.dtsi"
#include "pm8010-kaanapali.dtsi" /* SPMI1: SID-12/13 */
#include "pmd8028-kaanapali.dtsi" /* SPMI1: SID-4 */
#include "pmh0101.dtsi" /* SPMI0: SID-1 */
#include "pmh0104-kaanapali.dtsi" /* SPMI1: SID-9 */
#include "pmh0110-kaanapali.dtsi" /* SPMI0: SID-3/5/6/8 */
#include "pmih0108-kaanapali.dtsi" /* SPMI1: SID-7 */
#include "pmk8850.dtsi" /* SPMI0: SID-0 */
#include "pmr735d-kaanapali.dtsi" /* SPMI1: SID-10 */
/ {
model = "Qualcomm Technologies, Inc. Kaanapali MTP";
compatible = "qcom,kaanapali-mtp", "qcom,kaanapali";
@ -15,6 +27,7 @@ / {
aliases {
serial0 = &uart7;
serial1 = &uart18;
};
chosen {
@ -52,6 +65,193 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
clock-div = <2>;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&key_vol_up_default>;
pinctrl-names = "default";
key-volume-up {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
debounce-interval = <15>;
linux,can-disable;
wakeup-source;
};
};
sound {
compatible = "qcom,kaanapali-sndcard", "qcom,sm8450-sndcard";
model = "Kaanapali-MTP";
audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
"SpkrRight IN", "WSA_SPK2 OUT",
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"AMIC2", "MIC BIAS2",
"VA DMIC0", "MIC BIAS1",
"VA DMIC1", "MIC BIAS1",
"VA DMIC2", "MIC BIAS3",
"VA DMIC3", "MIC BIAS3",
"TX SWR_INPUT1", "ADC2_OUTPUT";
va-dai-link {
link-name = "VA Capture";
codec {
sound-dai = <&lpass_vamacro 0>;
};
cpu {
sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
};
platform {
sound-dai = <&q6apm>;
};
};
wcd-capture-dai-link {
link-name = "WCD Capture";
codec {
sound-dai = <&wcd939x 1>, <&swr2 0>, <&lpass_txmacro 0>;
};
cpu {
sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
};
platform {
sound-dai = <&q6apm>;
};
};
wcd-playback-dai-link {
link-name = "WCD Playback";
codec {
sound-dai = <&wcd939x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
};
cpu {
sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
};
platform {
sound-dai = <&q6apm>;
};
};
wsa-dai-link {
link-name = "WSA Playback";
codec {
sound-dai = <&north_spkr>, <&south_spkr>, <&swr0 0>,
<&lpass_wsamacro 0>;
};
cpu {
sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
};
platform {
sound-dai = <&q6apm>;
};
};
};
wcd939x: audio-codec {
compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec";
pinctrl-0 = <&wcd_default>;
pinctrl-names = "default";
qcom,micbias1-microvolt = <1800000>;
qcom,micbias2-microvolt = <1800000>;
qcom,micbias3-microvolt = <1800000>;
qcom,micbias4-microvolt = <1800000>;
qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000
500000 500000 500000 500000>;
qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
qcom,rx-device = <&wcd_rx>;
qcom,tx-device = <&wcd_tx>;
reset-gpios = <&tlmm 161 GPIO_ACTIVE_LOW>;
vdd-buck-supply = <&vreg_l15b_1p8>;
vdd-rxtx-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l15b_1p8>;
vdd-mic-bias-supply = <&vreg_bob1>;
vdd-px-supply = <&vreg_l1g_1p2>;
#sound-dai-cells = <1>;
};
wcn7850-pmu {
compatible = "qcom,wcn7850-pmu";
pinctrl-0 = <&bt_default>, <&sw_ctrl_default>, <&wlan_en>;
pinctrl-names = "default";
bt-enable-gpios = <&pmh0104_j_e1_gpios 5 GPIO_ACTIVE_HIGH>;
wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
vdd-supply = <&vreg_s2j_0p8>;
vddio-supply = <&vreg_l2g_1p8>;
vddio1p2-supply = <&vreg_l3g_1p2>;
vddaon-supply = <&vreg_s7g_0p9>;
vdddig-supply = <&vreg_s1j_0p8>;
vddrfa1p2-supply = <&vreg_s7f_1p2>;
vddrfa1p8-supply = <&vreg_s8f_1p8>;
clocks = <&rpmhcc RPMH_RF_CLK1>;
regulators {
vreg_pmu_rfa_cmn: ldo0 {
regulator-name = "vreg_pmu_rfa_cmn";
};
vreg_pmu_aon_0p59: ldo1 {
regulator-name = "vreg_pmu_aon_0p59";
};
vreg_pmu_wlcx_0p8: ldo2 {
regulator-name = "vreg_pmu_wlcx_0p8";
};
vreg_pmu_wlmx_0p85: ldo3 {
regulator-name = "vreg_pmu_wlmx_0p85";
};
vreg_pmu_btcmx_0p85: ldo4 {
regulator-name = "vreg_pmu_btcmx_0p85";
};
vreg_pmu_rfa_0p8: ldo5 {
regulator-name = "vreg_pmu_rfa_0p8";
};
vreg_pmu_rfa_1p2: ldo6 {
regulator-name = "vreg_pmu_rfa_1p2";
};
vreg_pmu_rfa_1p8: ldo7 {
regulator-name = "vreg_pmu_rfa_1p8";
};
vreg_pmu_pcie_0p9: ldo8 {
regulator-name = "vreg_pmu_pcie_0p9";
};
vreg_pmu_pcie_1p8: ldo9 {
regulator-name = "vreg_pmu_pcie_1p8";
};
};
};
};
&apps_rsc {
@ -175,7 +375,7 @@ vreg_l11b_1p0: ldo11 {
vreg_l12b_1p8: ldo12 {
regulator-name = "vreg_l12b_1p8";
regulator-min-microvolt = <1200000>;
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
regulator-allow-set-load;
@ -665,6 +865,59 @@ vreg_l7n_3p3: ldo7 {
};
};
&lpass_vamacro {
pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
pinctrl-names = "default";
vdd-micb-supply = <&vreg_l10b_1p8>;
qcom,dmic-sample-rate = <4800000>;
};
&mdss {
status = "okay";
};
&mdss_dsi0 {
vdda-supply = <&vreg_l1d_1p2>;
status = "okay";
panel@0 {
compatible = "novatek,nt37801";
reg = <0>;
pinctrl-0 = <&sde_dsi_active &sde_te_active &sde_esync0_suspend
&sde_mdp_vsync_p_1p2_active &sde_mdp_vsync_p_1p8_active
&sde_disp0_rst_1p2_active &sde_disp0_rst_1p8_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend &sde_esync0_suspend
&sde_mdp_vsync_p_1p2_active &sde_mdp_vsync_p_1p8_active
&sde_disp0_rst_1p2_active &sde_disp0_rst_1p8_active>;
pinctrl-names = "default", "sleep";
vci-supply = <&vreg_l13b_3p0>;
vdd-supply = <&vreg_l11b_1p0>;
vddio-supply = <&vreg_l12b_1p8>;
reset-gpios = <&tlmm 98 GPIO_ACTIVE_LOW>;
port {
panel0_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
&mdss_dsi0_out {
remote-endpoint = <&panel0_in>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi0_phy {
vdds-supply = <&vreg_l3d_0p8>;
status = "okay";
};
&pcie0 {
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@ -682,6 +935,140 @@ &pcie0_phy {
&pcie_port0 {
wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
vddaon-supply = <&vreg_pmu_aon_0p59>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
};
};
&pmh0101_flash {
status = "okay";
led-0 {
function = LED_FUNCTION_FLASH;
function-enumerator = <0>;
color = <LED_COLOR_ID_YELLOW>;
led-sources = <1>, <4>;
led-max-microamp = <500000>;
flash-max-microamp = <2000000>;
flash-max-timeout-us = <1280000>;
};
led-1 {
function = LED_FUNCTION_FLASH;
function-enumerator = <1>;
color = <LED_COLOR_ID_WHITE>;
led-sources = <2>, <3>;
led-max-microamp = <500000>;
flash-max-microamp = <2000000>;
flash-max-timeout-us = <1280000>;
};
};
&pmh0101_pwm {
status = "okay";
multi-led {
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_STATUS;
#address-cells = <1>;
#size-cells = <0>;
led@1 {
reg = <1>;
color = <LED_COLOR_ID_RED>;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_GREEN>;
};
led@3 {
reg = <3>;
color = <LED_COLOR_ID_BLUE>;
};
};
};
&pmh0104_j_e1_gpios {
bt_default: bt-default-state {
pins = "gpio5";
function = "normal";
input-disable;
output-enable;
output-low;
bias-disable;
power-source = <1>;
};
};
&pmh0110_d_e0_gpios {
sde_mdp_vsync_p_1p2_active: sde-mdp-vsync-p-1p2-active-state {
pins = "gpio9";
function = "paired";
input-disable;
output-enable;
power-source = <2>; /* 1.2v */
};
sde_mdp_vsync_p_1p8_active: sde-mdp-vsync-p-1p8-active-state {
pins = "gpio10";
function = "paired";
input-enable;
output-disable;
power-source = <1>; /* 1.8v */
};
};
&pmh0110_f_e0_gpios {
sde_disp0_rst_1p2_active: sde-disp0-rst-1p2-active-state {
pins = "gpio9";
function = "paired";
input-enable;
output-disable;
power-source = <2>; /* 1.2v */
};
sde_disp0_rst_1p8_active: sde-disp0-rst-1p8-active-state {
pins = "gpio10";
function = "paired";
input-disable;
output-enable;
power-source = <1>; /* 1.8v */
};
};
&pon_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&remoteproc_adsp {
firmware-name = "qcom/kaanapali/adsp.mbn",
"qcom/kaanapali/adsp_dtb.mbn";
status = "okay";
};
&remoteproc_cdsp {
firmware-name = "qcom/kaanapali/cdsp.mbn",
"qcom/kaanapali/cdsp_dtb.mbn";
status = "okay";
};
&sdhc_2 {
@ -701,12 +1088,169 @@ &sdhc_2 {
status = "okay";
};
&swr0 {
status = "okay";
/* WSA8845, Speaker North */
north_spkr: speaker@0,0 {
compatible = "sdw20217020400";
reg = <0 0>;
pinctrl-0 = <&spkr_0_sd_n_active>;
pinctrl-names = "default";
powerdown-gpios = <&tlmm 76 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
sound-name-prefix = "SpkrLeft";
vdd-1p8-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l2i_1p2>;
/*
* WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L)
* WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP)
* WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST)
* WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
* WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI)
* WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
*/
qcom,port-mapping = <1 2 3 7 10 13>;
};
/* WSA8845, Speaker South */
south_spkr: speaker@0,1 {
compatible = "sdw20217020400";
reg = <0 1>;
pinctrl-0 = <&spkr_1_sd_n_active>;
pinctrl-names = "default";
powerdown-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
sound-name-prefix = "SpkrRight";
vdd-1p8-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l2i_1p2>;
/*
* WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R)
* WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP)
* WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST)
* WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
* WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI)
* WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
*/
qcom,port-mapping = <4 5 6 7 11 13>;
};
};
&swr1 {
status = "okay";
/* WCD9395 RX */
wcd_rx: codec@0,4 {
compatible = "sdw20217010e00";
reg = <0 4>;
/*
* WCD9395 RX Port 1 (HPH_L/R) <=> SWR1 Port 1 (HPH_L/R)
* WCD9395 RX Port 2 (CLSH) <=> SWR1 Port 2 (CLSH)
* WCD9395 RX Port 3 (COMP_L/R) <=> SWR1 Port 3 (COMP_L/R)
* WCD9395 RX Port 4 (LO) <=> SWR1 Port 4 (LO)
* WCD9395 RX Port 5 (DSD_L/R) <=> SWR1 Port 5 (DSD_L/R)
* WCD9395 RX Port 6 (HIFI_PCM_L/R) <=> SWR1 Port 9 (HIFI_PCM_L/R)
*/
qcom,rx-port-mapping = <1 2 3 4 5 9>;
};
};
&swr2 {
status = "okay";
/* WCD9395 TX */
wcd_tx: codec@0,3 {
compatible = "sdw20217010e00";
reg = <0 3>;
/*
* WCD9395 TX Port 1 (ADC1,2,3,4) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3)
* WCD9395 TX Port 2 (ADC3,4 & DMIC0,1) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3)
* WCD9395 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 (TX SWR_INPUT 4,5,6,7)
* WCD9395 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 (TX SWR_INPUT 8,9,10,11)
*/
qcom,tx-port-mapping = <2 2 3 4>;
};
};
&tlmm {
gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */
<74 1>, /* eSE */
<119 2>, /* SoCCP */
<144 4>; /* CXM UART */
wlan_en: wlan-en-state {
pins = "gpio16";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
sw_ctrl_default: sw-ctrl-default-state {
pins = "gpio18";
function = "gpio";
bias-pull-down;
};
spkr_0_sd_n_active: spkr-0-sd-n-active-state {
pins = "gpio76";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
spkr_1_sd_n_active: spkr-1-sd-n-active-state {
pins = "gpio77";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
sde_te_active: sde-te-active-state {
pins = "gpio86";
function = "mdp_vsync";
drive-strength = <2>;
bias-pull-down;
};
sde_te_suspend: sde-te-suspend-state {
pins = "gpio86";
function = "mdp_vsync";
drive-strength = <2>;
bias-pull-down;
};
sde_esync0_suspend: sde-esync0-suspend-state {
pins = "gpio88";
function = "mdp_esync0_out";
drive-strength = <2>;
bias-pull-down;
};
sde_dsi_active: sde-dsi-active-state {
pins = "gpio98";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
sde_dsi_suspend: sde-dsi-suspend-state {
pins = "gpio98";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
key_vol_up_default: key-vol-up-default-state {
pins = "gpio101";
function = "gpio";
output-disable;
bias-pull-up;
};
pcie0_default_state: pcie0-default-state {
perst-n-pins {
pins = "gpio102";
@ -729,12 +1273,37 @@ wake-n-pins {
bias-pull-up;
};
};
wcd_default: wcd-reset-n-active-state {
pins = "gpio161";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
};
&uart7 {
status = "okay";
};
&uart18 {
status = "okay";
bluetooth {
compatible = "qcom,wcn7850-bt";
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
vddaon-supply = <&vreg_pmu_aon_0p59>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
max-speed = <3200000>;
};
};
&ufs_mem_hc {
reset-gpios = <&tlmm 217 GPIO_ACTIVE_LOW>;

106
arch/arm64/boot/dts/qcom/kaanapali-qrd.dts
View File

@ -5,9 +5,21 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "kaanapali.dtsi"
#include "pm8010-kaanapali.dtsi" /* SPMI1: SID-12/13 */
#include "pmd8028-kaanapali.dtsi" /* SPMI1: SID-4 */
#include "pmh0101.dtsi" /* SPMI0: SID-1 */
#include "pmh0104-kaanapali.dtsi" /* SPMI1: SID-9 */
#include "pmh0110-kaanapali.dtsi" /* SPMI0: SID-3/5/6/8 */
#include "pmih0108-kaanapali.dtsi" /* SPMI1: SID-7 */
#include "pmk8850.dtsi" /* SPMI0: SID-0 */
#include "pmr735d-kaanapali.dtsi" /* SPMI1: SID-10 */
/ {
model = "Qualcomm Technologies, Inc. Kaanapali QRD";
compatible = "qcom,kaanapali-qrd", "qcom,kaanapali";
@ -52,6 +64,22 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
clock-div = <2>;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&key_vol_up_default>;
pinctrl-names = "default";
key-volume-up {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
debounce-interval = <15>;
linux,can-disable;
wakeup-source;
};
};
};
&apps_rsc {
@ -665,6 +693,63 @@ vreg_l7n_3p3: ldo7 {
};
};
&pmh0101_flash {
status = "okay";
led-0 {
function = LED_FUNCTION_FLASH;
function-enumerator = <0>;
color = <LED_COLOR_ID_YELLOW>;
led-sources = <1>, <4>;
led-max-microamp = <500000>;
flash-max-microamp = <2000000>;
flash-max-timeout-us = <1280000>;
};
led-1 {
function = LED_FUNCTION_FLASH;
function-enumerator = <1>;
color = <LED_COLOR_ID_WHITE>;
led-sources = <2>, <3>;
led-max-microamp = <500000>;
flash-max-microamp = <2000000>;
flash-max-timeout-us = <1280000>;
};
};
&pmh0101_pwm {
status = "okay";
multi-led {
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_STATUS;
#address-cells = <1>;
#size-cells = <0>;
led@1 {
reg = <1>;
color = <LED_COLOR_ID_RED>;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_GREEN>;
};
led@3 {
reg = <3>;
color = <LED_COLOR_ID_BLUE>;
};
};
};
&pon_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&sdhc_2 {
cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
@ -682,11 +767,32 @@ &sdhc_2 {
status = "okay";
};
&remoteproc_adsp {
firmware-name = "qcom/kaanapali/adsp.mbn",
"qcom/kaanapali/adsp_dtb.mbn";
status = "okay";
};
&remoteproc_cdsp {
firmware-name = "qcom/kaanapali/cdsp.mbn",
"qcom/kaanapali/cdsp_dtb.mbn";
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */
<74 1>, /* eSE */
<119 2>, /* SoCCP */
<144 4>; /* CXM UART */
key_vol_up_default: key-vol-up-default-state {
pins = "gpio101";
function = "gpio";
output-disable;
bias-pull-up;
};
};
&uart7 {

5410
arch/arm64/boot/dts/qcom/kaanapali.dtsi
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128
arch/arm64/boot/dts/qcom/kodiak.dtsi
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@ -2445,7 +2445,7 @@ pcie1_phy: phy@1c0e000 {
reg = <0 0x01c0e000 0 0x1000>;
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_EN>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "aux",
@ -2642,6 +2642,8 @@ ipa: ipa@1e40000 {
qcom,smem-state-names = "ipa-clock-enabled-valid",
"ipa-clock-enabled";
sram = <&ipa_modem_tables>;
status = "disabled";
};
@ -3036,6 +3038,110 @@ lpass_dmic23_data: dmic23-data-state {
bias-pull-down;
};
lpass_i2s1_active: i2s1-active-state {
clk-pins {
pins = "gpio6";
function = "i2s1_clk";
drive-strength = <8>;
bias-disable;
output-high;
};
ws-pins {
pins = "gpio7";
function = "i2s1_ws";
drive-strength = <8>;
bias-disable;
output-high;
};
data-pins {
pins = "gpio8", "gpio9";
function = "i2s1_data";
drive-strength = <8>;
bias-disable;
output-high;
};
};
lpass_i2s1_sleep: i2s1-sleep-state {
clk-pins {
pins = "gpio6";
function = "i2s1_clk";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
ws-pins {
pins = "gpio7";
function = "i2s1_ws";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
data-pins {
pins = "gpio8", "gpio9";
function = "i2s1_data";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
};
lpass_i2s2_active: i2s2-active-state {
clk-pins {
pins = "gpio10";
function = "i2s2_clk";
drive-strength = <8>;
bias-disable;
output-high;
};
ws-pins {
pins = "gpio11";
function = "i2s2_ws";
drive-strength = <8>;
bias-disable;
output-high;
};
data-pins {
pins = "gpio12", "gpio13";
function = "i2s2_data";
drive-strength = <8>;
bias-disable;
output-high;
};
};
lpass_i2s2_sleep: i2s2-sleep-state {
clk-pins {
pins = "gpio10";
function = "i2s2_clk";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
ws-pins {
pins = "gpio11";
function = "i2s2_ws";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
data-pins {
pins = "gpio12", "gpio13";
function = "i2s2_data";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
};
lpass_rx_swr_clk: rx-swr-clk-state {
pins = "gpio3";
function = "swr_rx_clk";
@ -4849,6 +4955,7 @@ usb_1: usb@a600000 {
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
maximum-speed = "super-speed";
usb-role-switch;
ports {
#address-cells = <1>;
@ -5505,8 +5612,8 @@ port@1 {
edp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-162000000 {
opp-hz = /bits/ 64 <162000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
@ -5604,8 +5711,8 @@ mdss_dp_out: endpoint {
dp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-162000000 {
opp-hz = /bits/ 64 <162000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
@ -5721,6 +5828,13 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
cam_mclk3_default: cam-mclk3-default-state {
pins = "gpio67";
function = "cam_mclk";
drive-strength = <2>;
bias-disable;
};
cci0_default: cci0-default-state {
pins = "gpio69", "gpio70";
function = "cci_i2c";
@ -6577,6 +6691,10 @@ sram@146a5000 {
ranges = <0 0 0x146a5000 0x6000>;
ipa_modem_tables: modem-tables@3000 {
reg = <0x3000 0x2000>;
};
pil-reloc@594c {
compatible = "qcom,pil-reloc-info";
reg = <0x594c 0xc8>;

4
arch/arm64/boot/dts/qcom/lemans-el2.dtso
View File

@ -10,6 +10,10 @@
/dts-v1/;
/plugin/;
&gpu_zap_shader {
status = "disabled";
};
&iris {
status = "disabled";
};

263
arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso Normal file
View File

@ -0,0 +1,263 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
&{/} {
model = "Qualcomm Technologies, Inc. Lemans-evk IFP Mezzanine";
vreg_0p9: regulator-0v9 {
compatible = "regulator-fixed";
regulator-name = "VREG_0P9";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
};
vreg_1p8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "VREG_1P8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
};
&ethernet1 {
phy-handle = <&hsgmii_phy1>;
phy-mode = "2500base-x";
pinctrl-0 = <&ethernet1_default>;
pinctrl-names = "default";
snps,mtl-rx-config = <&mtl_rx_setup1>;
snps,mtl-tx-config = <&mtl_tx_setup1>;
nvmem-cells = <&mac_addr1>;
nvmem-cell-names = "mac-address";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
hsgmii_phy1: ethernet-phy@18 {
compatible = "ethernet-phy-id004d.d101";
reg = <0x18>;
reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
};
mtl_rx_setup1: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,route-ptp;
};
queue2 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,route-avcp;
};
queue3 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x3>;
snps,priority = <0xc>;
};
};
mtl_tx_setup1: tx-queues-config {
snps,tx-queues-to-use = <4>;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
queue3 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
};
};
&i2c18 {
#address-cells = <1>;
#size-cells = <0>;
eeprom@52 {
compatible = "giantec,gt24c256c", "atmel,24c256";
reg = <0x52>;
pagesize = <64>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
mac_addr1: mac-addr@0 {
reg = <0x0 0x6>;
};
};
};
};
&pcie0 {
iommu-map = <0x0 &pcie_smmu 0x0 0x1>,
<0x100 &pcie_smmu 0x1 0x1>,
<0x208 &pcie_smmu 0x2 0x1>,
<0x210 &pcie_smmu 0x3 0x1>,
<0x218 &pcie_smmu 0x4 0x1>,
<0x300 &pcie_smmu 0x5 0x1>,
<0x400 &pcie_smmu 0x6 0x1>,
<0x500 &pcie_smmu 0x7 0x1>,
<0x501 &pcie_smmu 0x8 0x1>;
};
&pcieport0 {
#address-cells = <3>;
#size-cells = <2>;
pcie@0,0 {
compatible = "pci1179,0623";
reg = <0x10000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
bus-range = <0x2 0xff>;
vddc-supply = <&vreg_0p9>;
vdd18-supply = <&vreg_1p8>;
vdd09-supply = <&vreg_0p9>;
vddio1-supply = <&vreg_1p8>;
vddio2-supply = <&vreg_1p8>;
vddio18-supply = <&vreg_1p8>;
i2c-parent = <&i2c18 0x77>;
resx-gpios = <&tlmm 140 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&tc9563_resx_n>;
pinctrl-names = "default";
pcie@1,0 {
reg = <0x20800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
bus-range = <0x3 0xff>;
};
pcie@2,0 {
reg = <0x21000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
bus-range = <0x4 0xff>;
};
pcie@3,0 {
reg = <0x21800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
bus-range = <0x5 0xff>;
pci@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
};
pci@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
};
};
};
};
&serdes1 {
phy-supply = <&vreg_l5a>;
status = "okay";
};
&tlmm {
ethernet1_default: ethernet1-default-state {
ethernet1-mdc-pins {
pins = "gpio20";
function = "emac1_mdc";
drive-strength = <16>;
bias-pull-up;
};
ethernet1-mdio-pins {
pins = "gpio21";
function = "emac1_mdio";
drive-strength = <16>;
bias-pull-up;
};
};
tc9563_resx_n: tc9563-resx-state {
pins = "gpio140";
function = "gpio";
bias-disable;
/* Reset pin of tc9563 is active low hence set default
* state of this pin to output-high.
*/
output-high;
};
};

107
arch/arm64/boot/dts/qcom/lemans-evk.dts
View File

@ -21,6 +21,7 @@ aliases {
ethernet0 = &ethernet0;
mmc1 = &sdhc;
serial0 = &uart10;
serial2 = &uart0;
};
dmic: audio-codec-0 {
@ -44,7 +45,7 @@ connector-0 {
data-role = "dual";
power-role = "dual";
vbus-supply = <&vbus_supply_regulator_0>;
vbus-supply = <&usb0_vbus>;
ports {
#address-cells = <1>;
@ -68,6 +69,25 @@ usb0_con_ss_ep: endpoint {
};
};
connector-2 {
compatible = "gpio-usb-b-connector", "usb-b-connector";
label = "micro-USB";
type = "micro";
id-gpios = <&pmm8654au_2_gpios 11 GPIO_ACTIVE_HIGH>;
vbus-gpios = <&expander3 3 GPIO_ACTIVE_HIGH>;
vbus-supply = <&usb2_vbus>;
pinctrl-0 = <&usb2_id>;
pinctrl-names = "default";
port {
usb2_con_hs_ep: endpoint {
remote-endpoint = <&usb_2_dwc3_hs>;
};
};
};
edp0-connector {
compatible = "dp-connector";
label = "EDP0";
@ -132,15 +152,24 @@ platform {
};
};
vbus_supply_regulator_0: regulator-vbus-supply-0 {
usb0_vbus: regulator-usb0-vbus {
compatible = "regulator-fixed";
regulator-name = "vbus_supply_0";
regulator-name = "usb0_vbus";
gpio = <&expander1 2 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
};
usb2_vbus: regulator-usb2-vbus {
compatible = "regulator-fixed";
regulator-name = "usb2_vbus";
gpio = <&pmm8654au_1_gpios 9 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
};
vmmc_sdc: regulator-vmmc-sdc {
compatible = "regulator-fixed";
@ -546,6 +575,11 @@ expander0: gpio@38 {
reg = <0x38>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
interrupts-extended = <&tlmm 138 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&expander0_int>;
pinctrl-names = "default";
};
expander1: gpio@39 {
@ -553,6 +587,11 @@ expander1: gpio@39 {
reg = <0x39>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
interrupts-extended = <&tlmm 19 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&expander1_int>;
pinctrl-names = "default";
};
expander2: gpio@3a {
@ -560,6 +599,11 @@ expander2: gpio@3a {
reg = <0x3a>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
interrupts-extended = <&tlmm 139 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&expander2_int>;
pinctrl-names = "default";
};
expander3: gpio@3b {
@ -567,6 +611,11 @@ expander3: gpio@3b {
reg = <0x3b>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
interrupts-extended = <&tlmm 39 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&expander3_int>;
pinctrl-names = "default";
};
eeprom@50 {
@ -699,6 +748,14 @@ usb0_intr_state: usb0-intr-state {
bias-pull-up;
power-source = <0>;
};
usb2_id: usb2-id-state {
pins = "gpio11";
function = "normal";
input-enable;
bias-pull-up;
power-source = <0>;
};
};
&qup_i2c19_default {
@ -804,6 +861,30 @@ ethernet0_mdio: ethernet0-mdio-pins {
};
};
expander0_int: expander0-int-state {
pins = "gpio138";
function = "gpio";
bias-pull-up;
};
expander1_int: expander1-int-state {
pins = "gpio19";
function = "gpio";
bias-pull-up;
};
expander2_int: expander2-int-state {
pins = "gpio139";
function = "gpio";
bias-pull-up;
};
expander3_int: expander3-int-state {
pins = "gpio39";
function = "gpio";
bias-pull-up;
};
pcie0_default_state: pcie0-default-state {
clkreq-pins {
pins = "gpio1";
@ -870,6 +951,10 @@ usb_id: usb-id-state {
};
};
&uart0 {
status = "okay";
};
&uart10 {
compatible = "qcom,geni-debug-uart";
pinctrl-0 = <&qup_uart10_default>;
@ -922,6 +1007,22 @@ &usb_0_qmpphy {
status = "okay";
};
&usb_2 {
status = "okay";
};
&usb_2_dwc3_hs {
remote-endpoint = <&usb2_con_hs_ep>;
};
&usb_2_hsphy {
vdda-pll-supply = <&vreg_l7a>;
vdda18-supply = <&vreg_l6c>;
vdda33-supply = <&vreg_l9a>;
status = "okay";
};
&xo_board_clk {
clock-frequency = <38400000>;
};

26
arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
View File

@ -21,28 +21,6 @@ chosen {
stdout-path = "serial0:115200n8";
};
vreg_12p0: vreg-12p0-regulator {
compatible = "regulator-fixed";
regulator-name = "VREG_12P0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vreg_5p0: vreg-5p0-regulator {
compatible = "regulator-fixed";
regulator-name = "VREG_5P0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vreg_12p0>;
};
vreg_1p8: vreg-1p8-regulator {
compatible = "regulator-fixed";
regulator-name = "VREG_1P8";
@ -51,8 +29,6 @@ vreg_1p8: vreg-1p8-regulator {
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vreg_5p0>;
};
vreg_1p0: vreg-1p0-regulator {
@ -75,8 +51,6 @@ vreg_3p0: vreg-3p0-regulator {
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
vin-supply = <&vreg_12p0>;
};
vreg_conn_1p8: vreg_conn_1p8 {

37
arch/arm64/boot/dts/qcom/lemans.dtsi
View File

@ -1512,7 +1512,7 @@ i2c20: i2c@898000 {
reg = <0x0 0x898000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_i2c20_default>;
@ -1539,7 +1539,7 @@ spi20: spi@898000 {
reg = <0x0 0x898000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_spi20_default>;
@ -1564,7 +1564,7 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
uart20: serial@898000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00898000 0x0 0x4000>;
interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_uart20_default>;
@ -2510,7 +2510,7 @@ i2c13: i2c@a98000 {
reg = <0x0 0xa98000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_i2c13_default>;
@ -4270,7 +4270,14 @@ usb_2: usb@a400000 {
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
usb-role-switch;
status = "disabled";
port {
usb_2_dwc3_hs: endpoint {
};
};
};
tcsr_mutex: hwlock@1f40000 {
@ -4625,19 +4632,19 @@ opp-366000000 {
opp-444000000 {
opp-hz = /bits/ 64 <444000000>;
required-opps = <&rpmhpd_opp_nom>,
required-opps = <&rpmhpd_opp_svs_l1>,
<&rpmhpd_opp_nom>;
};
opp-533000000 {
opp-hz = /bits/ 64 <533000000>;
required-opps = <&rpmhpd_opp_turbo>,
required-opps = <&rpmhpd_opp_nom>,
<&rpmhpd_opp_turbo>;
};
opp-560000000 {
opp-hz = /bits/ 64 <560000000>;
required-opps = <&rpmhpd_opp_turbo_l1>,
required-opps = <&rpmhpd_opp_nom>,
<&rpmhpd_opp_turbo_l1>;
};
};
@ -5404,8 +5411,8 @@ port@1 {
dp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-162000000 {
opp-hz = /bits/ 64 <162000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
@ -5492,8 +5499,8 @@ port@1 {
dp1_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-162000000 {
opp-hz = /bits/ 64 <162000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
@ -8575,10 +8582,10 @@ trip-point1 {
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
turing-llm-tpdm {

21
arch/arm64/boot/dts/qcom/mahua-crd.dts Normal file
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/dts-v1/;
#include "mahua.dtsi"
#include "glymur-crd.dtsi"
/delete-node/ &pmcx0102_d_e0;
/delete-node/ &pmcx0102_d0_thermal;
/delete-node/ &pmh0104_i_e0;
/delete-node/ &pmh0104_i0_thermal;
/delete-node/ &pmh0104_j_e0;
/delete-node/ &pmh0104_j0_thermal;
/ {
model = "Qualcomm Technologies, Inc. Mahua CRD";
compatible = "qcom,mahua-crd", "qcom,mahua";
};

299
arch/arm64/boot/dts/qcom/mahua.dtsi Normal file
View File

@ -0,0 +1,299 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/* Mahua is heavily based on Glymur, with some meaningful differences */
#include "glymur.dtsi"
/delete-node/ &bwmon_cluster2;
/delete-node/ &cluster2_pd;
/delete-node/ &cpu_map_cluster2;
/delete-node/ &cpu12;
/delete-node/ &cpu13;
/delete-node/ &cpu14;
/delete-node/ &cpu15;
/delete-node/ &cpu16;
/delete-node/ &cpu17;
/delete-node/ &cpu_pd12;
/delete-node/ &cpu_pd13;
/delete-node/ &cpu_pd14;
/delete-node/ &cpu_pd15;
/delete-node/ &cpu_pd16;
/delete-node/ &cpu_pd17;
/delete-node/ &thermal_aoss_6;
/delete-node/ &thermal_aoss_7;
/delete-node/ &thermal_cpu_2_0_0;
/delete-node/ &thermal_cpu_2_0_1;
/delete-node/ &thermal_cpu_2_1_0;
/delete-node/ &thermal_cpu_2_1_1;
/delete-node/ &thermal_cpu_2_2_0;
/delete-node/ &thermal_cpu_2_2_1;
/delete-node/ &thermal_cpu_2_3_0;
/delete-node/ &thermal_cpu_2_3_1;
/delete-node/ &thermal_cpu_2_4_0;
/delete-node/ &thermal_cpu_2_4_1;
/delete-node/ &thermal_cpu_2_5_0;
/delete-node/ &thermal_cpu_2_5_1;
/delete-node/ &thermal_cpuillc_2_1;
/delete-node/ &thermal_cpullc_2_0;
/delete-node/ &thermal_ddr_2;
/delete-node/ &thermal_gpu_3_0;
/delete-node/ &thermal_gpu_3_1;
/delete-node/ &thermal_gpu_3_2;
/delete-node/ &thermal_qmx_2_0;
/delete-node/ &thermal_qmx_2_1;
/delete-node/ &thermal_qmx_2_2;
/delete-node/ &thermal_qmx_2_3;
/delete-node/ &thermal_qmx_2_4;
/delete-node/ &thermal_video_1;
/delete-node/ &tsens6;
/delete-node/ &tsens7;
&aggre1_noc {
compatible = "qcom,mahua-aggre1-noc", "qcom,glymur-aggre1-noc";
};
&aggre2_noc {
compatible = "qcom,mahua-aggre2-noc", "qcom,glymur-aggre2-noc";
};
&aggre3_noc {
compatible = "qcom,mahua-aggre3-noc", "qcom,glymur-aggre3-noc";
};
&aggre4_noc {
compatible = "qcom,mahua-aggre4-noc", "qcom,glymur-aggre4-noc";
};
&clk_virt {
compatible = "qcom,mahua-clk-virt", "qcom,glymur-clk-virt";
};
&cnoc_main {
compatible = "qcom,mahua-cnoc-main", "qcom,glymur-cnoc-main";
};
&config_noc {
compatible = "qcom,mahua-cnoc-cfg";
};
&hsc_noc {
compatible = "qcom,mahua-hscnoc";
};
&lpass_ag_noc {
compatible = "qcom,mahua-lpass-ag-noc", "qcom,glymur-lpass-ag-noc";
};
&lpass_lpiaon_noc {
compatible = "qcom,mahua-lpass-lpiaon-noc", "qcom,glymur-lpass-lpiaon-noc";
};
&lpass_lpicx_noc {
compatible = "qcom,mahua-lpass-lpicx-noc", "qcom,glymur-lpass-lpicx-noc";
};
&mc_virt {
compatible = "qcom,mahua-mc-virt";
};
&mmss_noc {
compatible = "qcom,mahua-mmss-noc", "qcom,glymur-mmss-noc";
};
&nsi_noc {
compatible = "qcom,mahua-nsinoc", "qcom,glymur-nsinoc";
};
&nsp_noc {
compatible = "qcom,mahua-nsp-noc", "qcom,glymur-nsp-noc";
};
&oobm_ss_noc {
compatible = "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc";
};
&pcie_east_anoc {
compatible = "qcom,mahua-pcie-east-anoc", "qcom,glymur-pcie-east-anoc";
};
&pcie_east_slv_noc {
compatible = "qcom,mahua-pcie-east-slv-noc", "qcom,glymur-pcie-east-slv-noc";
};
&pcie_west_anoc {
compatible = "qcom,mahua-pcie-west-anoc";
clocks = <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>;
};
&pcie_west_slv_noc {
compatible = "qcom,mahua-pcie-west-slv-noc";
};
&system_noc {
compatible = "qcom,mahua-system-noc", "qcom,glymur-system-noc";
};
&thermal_camera_0 {
thermal-sensors = <&tsens4 9>;
};
&thermal_camera_1 {
thermal-sensors = <&tsens4 10>;
};
&thermal_ddr_1 {
thermal-sensors = <&tsens1 7>;
};
&thermal_gpu_0_0 {
thermal-sensors = <&tsens5 1>;
};
&thermal_gpu_0_1 {
thermal-sensors = <&tsens5 2>;
};
&thermal_gpu_0_2 {
thermal-sensors = <&tsens5 3>;
};
&thermal_gpu_1_0 {
thermal-sensors = <&tsens5 4>;
};
&thermal_gpu_1_1 {
thermal-sensors = <&tsens5 5>;
};
&thermal_gpu_1_2 {
thermal-sensors = <&tsens5 6>;
};
&thermal_gpu_2_0 {
thermal-sensors = <&tsens5 7>;
};
&thermal_gpu_2_1 {
thermal-sensors = <&tsens5 8>;
};
&thermal_gpu_2_2 {
thermal-sensors = <&tsens5 9>;
};
&thermal_gpuss_0 {
thermal-sensors = <&tsens5 10>;
};
&thermal_gpuss_1 {
thermal-sensors = <&tsens5 11>;
};
&thermal_nsphmx_0 {
thermal-sensors = <&tsens4 5>;
};
&thermal_nsphmx_1 {
thermal-sensors = <&tsens4 6>;
};
&thermal_nsphmx_2 {
thermal-sensors = <&tsens4 7>;
};
&thermal_nsphmx_3 {
thermal-sensors = <&tsens4 8>;
};
&thermal_nsphvx_0 {
thermal-sensors = <&tsens4 1>;
};
&thermal_nsphvx_1 {
thermal-sensors = <&tsens4 2>;
};
&thermal_nsphvx_2 {
thermal-sensors = <&tsens4 3>;
};
&thermal_nsphvx_3 {
thermal-sensors = <&tsens4 4>;
};
&thermal_video_0 {
thermal-sensors = <&tsens1 8>;
};
&thermal_zones {
gpuss-2-thermal {
thermal-sensors = <&tsens5 12>;
trips {
trip-point0 {
temperature = <90000>;
hysteresis = <5000>;
type = "hot";
};
gpuss-2-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
gpuss-3-thermal {
thermal-sensors = <&tsens5 13>;
trips {
trip-point0 {
temperature = <90000>;
hysteresis = <5000>;
type = "hot";
};
gpuss-3-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
gpuss-4-thermal {
thermal-sensors = <&tsens5 14>;
trips {
trip-point0 {
temperature = <90000>;
hysteresis = <5000>;
type = "hot";
};
gpuss-4-critical {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
};
&tlmm {
compatible = "qcom,mahua-tlmm";
};
&tsens4 {
#qcom,sensors = <11>;
};
&tsens5 {
#qcom,sensors = <15>;
};

89
arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
View File

@ -29,9 +29,19 @@ aliases {
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&volume_up_default>;
pinctrl-0 = <&volume_up_default>, <&hall_sensor_default>;
pinctrl-names = "default";
/* Powered by the always-on vreg_l10b */
event-hall-sensor {
label = "Hall Effect Sensor";
gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
linux,can-disable;
wakeup-source;
};
key-volume-up {
label = "Volume Up";
gpios = <&pm7550_gpios 6 GPIO_ACTIVE_LOW>;
@ -316,6 +326,8 @@ vreg_l10b: ldo10 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
/* Hall sensor VDD */
regulator-always-on;
};
vreg_l11b: ldo11 {
@ -529,6 +541,56 @@ vreg_l11f: ldo11 {
};
};
&cci0 {
status = "okay";
};
&cci0_i2c0 {
/* Main cam: Sony IMX896 @ 0x1a */
eeprom@50 {
compatible = "puya,p24c128f", "atmel,24c128";
reg = <0x50>;
vcc-supply = <&vreg_l6p>;
read-only;
};
/* Dongwoon DW9784 VCM/OIS @ 0x72 */
};
&cci0_i2c1 {
/* Awinic AW86017 VCM @ 0x0c */
/* UW cam: OmniVision OV13B10 @ 0x36 */
eeprom@52 {
compatible = "puya,p24c128f", "atmel,24c128";
reg = <0x52>;
vcc-supply = <&vreg_l6p>;
read-only;
};
};
&cci1 {
/* cci1_i2c0 is not used for CCI */
pinctrl-0 = <&cci1_1_default>;
pinctrl-1 = <&cci1_1_sleep>;
status = "okay";
};
&cci1_i2c1 {
/* Awinic AW86016 VCM @ 0x0c */
/* Front cam: Samsung S5KKD1 @ 0x3d */
eeprom@51 {
compatible = "puya,p24c128f", "atmel,24c128";
reg = <0x51>;
vcc-supply = <&vreg_l6p>;
read-only;
};
};
&gcc {
protected-clocks = <GCC_PCIE_1_AUX_CLK>, <GCC_PCIE_1_AUX_CLK_SRC>,
<GCC_PCIE_1_CFG_AHB_CLK>, <GCC_PCIE_1_MSTR_AXI_CLK>,
@ -755,6 +817,13 @@ sdc2_card_det_n: sdc2-card-det-state {
bias-pull-up;
};
hall_sensor_default: hall-sensor-default-state {
pins = "gpio70";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
pm8008_int_default: pm8008-int-default-state {
pins = "gpio125";
function = "gpio";
@ -767,6 +836,24 @@ &uart5 {
status = "okay";
};
&ufs_mem_hc {
reset-gpios = <&tlmm 167 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l12b>;
vcc-max-microamp = <800000>;
vccq-supply = <&vreg_l5f>;
vccq-max-microamp = <750000>;
status = "okay";
};
&ufs_mem_phy {
vdda-phy-supply = <&vreg_l2b>;
vdda-pll-supply = <&vreg_l4b>;
status = "okay";
};
&usb_1 {
dr_mode = "otg";

669
arch/arm64/boot/dts/qcom/milos.dtsi
View File

@ -18,7 +18,9 @@
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
/ {
interrupt-parent = <&intc>;
@ -797,11 +799,13 @@ gcc: clock-controller@100000 {
<&sleep_clk>,
<0>, /* pcie_0_pipe_clk */
<0>, /* pcie_1_pipe_clk */
<0>, /* ufs_phy_rx_symbol_0_clk */
<0>, /* ufs_phy_rx_symbol_1_clk */
<0>, /* ufs_phy_tx_symbol_0_clk */
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
@ -1151,6 +1155,129 @@ aggre2_noc: interconnect@1700000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
ufs_mem_phy: phy@1d80000 {
compatible = "qcom,milos-qmp-ufs-phy";
reg = <0x0 0x01d80000 0x0 0x2000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&tcsr TCSR_UFS_CLKREF_EN>;
clock-names = "ref",
"ref_aux",
"qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
power-domains = <&gcc UFS_MEM_PHY_GDSC>;
#clock-cells = <1>;
#phy-cells = <0>;
status = "disabled";
};
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,milos-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&tcsr TCSR_UFS_PAD_CLKREF_EN>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
clock-names = "core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&cnoc_cfg SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "ufs-ddr",
"cpu-ufs";
power-domains = <&gcc UFS_PHY_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
operating-points-v2 = <&ufs_opp_table>;
iommus = <&apps_smmu 0x60 0>;
dma-coherent;
lanes-per-direction = <2>;
qcom,ice = <&ice>;
phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
#reset-cells = <1>;
status = "disabled";
ufs_opp_table: opp-table {
compatible = "operating-points-v2";
opp-75000000 {
opp-hz = /bits/ 64 <75000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <75000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-150000000 {
opp-hz = /bits/ 64 <150000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <150000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <300000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
ice: crypto@1d88000 {
compatible = "qcom,milos-inline-crypto-engine",
"qcom,inline-crypto-engine";
reg = <0x0 0x01d88000 0x0 0x18000>;
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x20000>;
@ -1214,6 +1341,197 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
label = "lpass";
qcom,remote-pid = <2>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x1003 0x0>,
<&apps_smmu 0x1063 0x0>;
dma-coherent;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x1004 0x0>,
<&apps_smmu 0x1064 0x0>;
dma-coherent;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x1005 0x0>,
<&apps_smmu 0x1065 0x0>;
dma-coherent;
};
compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
reg = <6>;
iommus = <&apps_smmu 0x1006 0x0>,
<&apps_smmu 0x1066 0x0>;
dma-coherent;
};
compute-cb@7 {
compatible = "qcom,fastrpc-compute-cb";
reg = <7>;
iommus = <&apps_smmu 0x1007 0x0>,
<&apps_smmu 0x1067 0x0>;
dma-coherent;
};
};
gpr {
compatible = "qcom,gpr";
qcom,glink-channels = "adsp_apps";
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
qcom,intents = <512 20>;
#address-cells = <1>;
#size-cells = <0>;
q6apm: service@1 {
compatible = "qcom,q6apm";
reg = <GPR_APM_MODULE_IID>;
#sound-dai-cells = <0>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6apmbedai: bedais {
compatible = "qcom,q6apm-lpass-dais";
#sound-dai-cells = <1>;
};
q6apmdai: dais {
compatible = "qcom,q6apm-dais";
iommus = <&apps_smmu 0x1001 0x0>,
<&apps_smmu 0x1061 0x0>;
};
};
q6prm: service@2 {
compatible = "qcom,q6prm";
reg = <GPR_PRM_MODULE_IID>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6prmcc: clock-controller {
compatible = "qcom,q6prm-lpass-clocks";
#clock-cells = <2>;
};
};
};
};
};
lpass_tlmm: pinctrl@3440000 {
compatible = "qcom,milos-lpass-lpi-pinctrl";
reg = <0x0 0x03440000 0x0 0x20000>,
<0x0 0x034d0000 0x0 0x10000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 23>;
clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core",
"audio";
tx_swr_active: tx-swr-active-state {
clk-pins {
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <4>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio1", "gpio2", "gpio14";
function = "swr_tx_data";
drive-strength = <4>;
slew-rate = <1>;
bias-bus-hold;
};
};
rx_swr_active: rx-swr-active-state {
clk-pins {
pins = "gpio3";
function = "swr_rx_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio4", "gpio5";
function = "swr_rx_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
lpi_i2s2_active: lpi-i2s2-active-state {
clk-pins {
pins = "gpio10";
function = "i2s2_clk";
drive-strength = <8>;
bias-disable;
output-high;
};
ws-pins {
pins = "gpio11";
function = "i2s2_ws";
drive-strength = <8>;
bias-disable;
output-high;
};
data-pins {
pins = "gpio12", "gpio13";
function = "i2s2_data";
drive-strength = <8>;
bias-disable;
output-high;
};
};
lpi_i2s2_sleep: lpi-i2s2-sleep-state {
clk-pins {
pins = "gpio10";
function = "i2s2_clk";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
ws-pins {
pins = "gpio11";
function = "i2s2_ws";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
data-pins {
pins = "gpio12", "gpio13";
function = "i2s2_data";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
};
};
@ -1531,6 +1849,72 @@ videocc: clock-controller@aaf0000 {
#power-domain-cells = <1>;
};
cci0: cci@ac15000 {
compatible = "qcom,milos-cci", "qcom,msm8996-cci";
reg = <0x0 0x0ac15000 0x0 0x1000>;
interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING 0>;
power-domains = <&camcc CAM_CC_CAMSS_TOP_GDSC>;
clocks = <&camcc CAM_CC_SOC_AHB_CLK>,
<&camcc CAM_CC_CPAS_AHB_CLK>,
<&camcc CAM_CC_CCI_0_CLK>;
clock-names = "soc_ahb",
"cpas_ahb",
"cci";
pinctrl-0 = <&cci0_0_default &cci0_1_default>;
pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
pinctrl-names = "default", "sleep";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
cci0_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci0_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
cci1: cci@ac16000 {
compatible = "qcom,milos-cci", "qcom,msm8996-cci";
reg = <0x0 0x0ac16000 0x0 0x1000>;
interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING 0>;
power-domains = <&camcc CAM_CC_CAMSS_TOP_GDSC>;
clocks = <&camcc CAM_CC_SOC_AHB_CLK>,
<&camcc CAM_CC_CPAS_AHB_CLK>,
<&camcc CAM_CC_CCI_1_CLK>;
clock-names = "soc_ahb",
"cpas_ahb",
"cci";
pinctrl-0 = <&cci1_0_default &cci1_1_default>;
pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
pinctrl-names = "default", "sleep";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
cci1_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci1_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
camcc: clock-controller@adb0000 {
compatible = "qcom,milos-camcc";
reg = <0x0 0x0adb0000 0x0 0x40000>;
@ -1667,6 +2051,21 @@ tlmm: pinctrl@f100000 {
wakeup-parent = <&pdc>;
qup_spi0_data_clk: qup-spi0-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio0", "gpio1", "gpio2";
function = "qup0_se0";
drive-strength = <6>;
bias-disable;
};
qup_spi0_cs: qup-spi0-cs-state {
pins = "gpio3";
function = "qup0_se0";
drive-strength = <6>;
bias-disable;
};
qup_i2c1_data_clk: qup-i2c1-data-clk-state {
/* SDA, SCL */
pins = "gpio4", "gpio5";
@ -1683,29 +2082,6 @@ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
bias-pull-up = <2200>;
};
qup_i2c7_data_clk: qup-i2c7-data-clk-state {
/* SDA, SCL */
pins = "gpio32", "gpio33";
function = "qup1_se0";
drive-strength = <2>;
bias-pull-up;
};
qup_spi0_cs: qup-spi0-cs-state {
pins = "gpio3";
function = "qup0_se0";
drive-strength = <6>;
bias-disable;
};
qup_spi0_data_clk: qup-spi0-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio0", "gpio1", "gpio2";
function = "qup0_se0";
drive-strength = <6>;
bias-disable;
};
qup_uart5_default: qup-uart5-default-state {
/* TX, RX */
pins = "gpio25", "gpio26";
@ -1714,10 +2090,10 @@ qup_uart5_default: qup-uart5-default-state {
bias-disable;
};
qup_uart11_default: qup-uart11-default-state {
/* TX, RX */
pins = "gpio50", "gpio51";
function = "qup1_se4";
qup_i2c7_data_clk: qup-i2c7-data-clk-state {
/* SDA, SCL */
pins = "gpio32", "gpio33";
function = "qup1_se0";
drive-strength = <2>;
bias-pull-up;
};
@ -1730,6 +2106,14 @@ qup_uart11_cts_rts: qup-uart11-cts-rts-state {
bias-pull-down;
};
qup_uart11_default: qup-uart11-default-state {
/* TX, RX */
pins = "gpio50", "gpio51";
function = "qup1_se4";
drive-strength = <2>;
bias-pull-up;
};
sdc2_default: sdc2-default-state {
clk-pins {
pins = "gpio62";
@ -1775,6 +2159,134 @@ data-pins {
bias-pull-up;
};
};
cci0_0_default: cci0-0-default-state {
sda-pins {
pins = "gpio88";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-up = <2200>;
};
scl-pins {
pins = "gpio89";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-up = <2200>;
};
};
cci0_0_sleep: cci0-0-sleep-state {
sda-pins {
pins = "gpio88";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-down;
};
scl-pins {
pins = "gpio89";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-down;
};
};
cci0_1_default: cci0-1-default-state {
sda-pins {
pins = "gpio90";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-up = <2200>;
};
scl-pins {
pins = "gpio91";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-up = <2200>;
};
};
cci0_1_sleep: cci0-1-sleep-state {
sda-pins {
pins = "gpio90";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-down;
};
scl-pins {
pins = "gpio91";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-down;
};
};
cci1_0_default: cci1-0-default-state {
sda-pins {
pins = "gpio92";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-up = <2200>;
};
scl-pins {
pins = "gpio93";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-up = <2200>;
};
};
cci1_0_sleep: cci1-0-sleep-state {
sda-pins {
pins = "gpio92";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-down;
};
scl-pins {
pins = "gpio93";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-down;
};
};
cci1_1_default: cci1-1-default-state {
sda-pins {
pins = "gpio94";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-up = <2200>;
};
scl-pins {
pins = "gpio95";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-up = <2200>;
};
};
cci1_1_sleep: cci1-1-sleep-state {
sda-pins {
pins = "gpio94";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-down;
};
scl-pins {
pins = "gpio95";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-down;
};
};
};
apps_smmu: iommu@15000000 {
@ -1911,7 +2423,7 @@ ppi_cluster1: interrupt-partition-1 {
gic_its: msi-controller@17140000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0x17140000 0x0 0x20000>;
reg = <0x0 0x17140000 0x0 0x40000>;
msi-controller;
#msi-cells = <1>;
@ -2164,6 +2676,101 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
label = "cdsp";
qcom,remote-pid = <5>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "cdsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@1 {
compatible = "qcom,fastrpc-compute-cb";
reg = <1>;
iommus = <&apps_smmu 0x0c01 0x0>;
dma-coherent;
};
compute-cb@2 {
compatible = "qcom,fastrpc-compute-cb";
reg = <2>;
iommus = <&apps_smmu 0x0c02 0x0>;
dma-coherent;
};
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x0c03 0x0>;
dma-coherent;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x0c04 0x0>;
dma-coherent;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x0c05 0x0>;
dma-coherent;
};
compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
reg = <6>;
iommus = <&apps_smmu 0x0c06 0x0>;
dma-coherent;
};
compute-cb@7 {
compatible = "qcom,fastrpc-compute-cb";
reg = <7>;
iommus = <&apps_smmu 0x0c07 0x0>;
dma-coherent;
};
compute-cb@8 {
compatible = "qcom,fastrpc-compute-cb";
reg = <8>;
iommus = <&apps_smmu 0x0c08 0x0>;
dma-coherent;
};
/* note: secure cb9 in downstream */
compute-cb@12 {
compatible = "qcom,fastrpc-compute-cb";
reg = <12>;
iommus = <&apps_smmu 0x0c0c 0x0>;
dma-coherent;
};
compute-cb@13 {
compatible = "qcom,fastrpc-compute-cb";
reg = <13>;
iommus = <&apps_smmu 0x0c0d 0x0>;
dma-coherent;
};
compute-cb@14 {
compatible = "qcom,fastrpc-compute-cb";
reg = <14>;
iommus = <&apps_smmu 0x0c0e 0x0>;
dma-coherent;
};
compute-cb@15 {
compatible = "qcom,fastrpc-compute-cb";
reg = <15>;
iommus = <&apps_smmu 0x0c0f 0x0>;
dma-coherent;
};
};
};
};
};

466
arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts Normal file
View File

@ -0,0 +1,466 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "monaco.dtsi"
#include "monaco-pmics.dtsi"
#include "monaco-monza-som.dtsi"
/ {
model = "Arduino VENTUNO Q";
compatible = "arduino,monza", "qcom,qcs8300";
aliases {
ethernet0 = &ethernet0;
i2c1 = &i2c1;
serial0 = &uart7;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&gpio_keys_default>;
pinctrl-names = "default";
button-home {
label = "Home Key";
linux,code = <KEY_HOMEPAGE>;
gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
hdmi-connector {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&adv7535_out>;
};
};
};
sound {
compatible = "qcom,qcs8275-sndcard";
model = "arduino-monza";
audio-routing = "IN12", "Headset Mic12",
"Headset Mic12", "MICBIAS",
"IN56", "Headset Mic56",
"Headset Mic56", "MICBIAS",
"MIC1", "MICBIAS",
"Headphone", "HPL",
"Headphone", "HPR",
"Receiver", "RCVL",
"Receiver", "RCVR",
"Speaker", "SPKL",
"Speaker", "SPKR";
pinctrl-0 = <&quad_mi2s_active>, <&quad_mclk_active>, <&lpi_i2s4_active>;
pinctrl-names = "default";
pri-i2s-playback-dai-link {
link-name = "Analog Playback";
codec {
sound-dai = <&max98091>;
};
cpu {
sound-dai = <&q6apmbedai 137>;
};
platform {
sound-dai = <&q6apm>;
};
};
pri-i2s-capture-dai-link {
link-name = "Analog Capture";
codec {
sound-dai = <&max98091>;
};
cpu {
sound-dai = <&q6apmbedai 138>;
};
platform {
sound-dai = <&q6apm>;
};
};
hdmi-mi2s-playback-dai-link {
link-name = "HDMI Playback";
codec {
sound-dai = <&adv7535>;
};
cpu {
sound-dai = <&q6apmbedai 145>;
};
platform {
sound-dai = <&q6apm>;
};
};
};
vdc_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "vdc_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdc_1v8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "vdc_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vdc_5v: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "vdc_5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
startup-delay-us = <20000>;
};
vreg_nvme: regulator-3p3-m2 {
compatible = "regulator-fixed";
regulator-name = "vreg_m2_3p3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <20000>;
};
};
&ethernet0 {
phy-mode = "2500base-x";
phy-handle = <&hsgmii_phy0>;
pinctrl-0 = <&ethernet0_default>;
pinctrl-names = "default";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
hsgmii_phy0: ethernet-phy@1c {
compatible = "ethernet-phy-id004d.d101";
reg = <0x1c>;
reset-gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,route-ptp;
};
queue2 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,route-avcp;
};
queue3 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x3>;
snps,priority = <0xc>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <4>;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
queue3 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
};
};
&i2c12 {
clock-frequency = <400000>;
status = "okay";
max98091: audio-codec@10 {
compatible = "maxim,max98091";
reg = <0x10>;
pinctrl-0 = <&max98091_default>;
pinctrl-names = "default";
interrupts-extended = <&tlmm 16 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_16 */
clocks = <&q6prmcc LPASS_CLK_ID_MCLK_3 LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "mclk";
#sound-dai-cells = <0>;
};
adv7535: bridge@3d {
compatible = "adi,adv7535";
reg = <0x3d>;
pinctrl-0 = <&adv7535_default>;
pinctrl-names = "default";
interrupts-extended = <&tlmm 93 IRQ_TYPE_EDGE_FALLING>;
avdd-supply = <&vdc_1v8>;
dvdd-supply = <&vdc_1v8>;
pvdd-supply = <&vdc_1v8>;
a2vdd-supply = <&vdc_1v8>;
v3p3-supply = <&vdc_3v3>;
v1p2-supply = <&vdc_1v8>;
adi,dsi-lanes = <4>;
#sound-dai-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7535_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
port@1 {
reg = <1>;
adv7535_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
};
&mdss {
status = "okay";
};
&mdss_dp0 {
status = "okay";
};
&mdss_dp0_out {
data-lanes = <0 1 2 3>;
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
};
&mdss_dp0_phy {
status = "okay";
};
&mdss_dsi0 {
status = "okay";
};
&mdss_dsi0_out {
remote-endpoint = <&adv7535_in>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi0_phy {
status = "okay";
};
&pcie0 {
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
vddpe-3v3-supply = <&vdc_3v3>;
};
&pcie1 {
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
vddpe-3v3-supply = <&vreg_nvme>;
};
&pcieport0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
pci@0,0 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x01 0xff>;
ranges;
reg = <0x010000 0x00 0x00 0x00 0x00>;
pci@2,0 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges;
reg = <0x021000 0x00 0x00 0x00 0x00>;
usb@0 {
compatible = "pci104c,8241";
reg = <0 0 0 0 0>;
ti,pwron-active-high;
};
};
};
};
&pcieport1 {
reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
};
&tlmm {
pcie0_default_state: pcie0-default-state {
wake-pins {
pins = "gpio0";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
clkreq-pins {
pins = "gpio1";
function = "pcie0_clkreq";
drive-strength = <2>;
bias-pull-up;
};
perst-pins {
pins = "gpio2";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
pins = "gpio5";
function = "emac0_mdc";
drive-strength = <16>;
bias-pull-up;
};
ethernet0_mdio: ethernet0-mdio-pins {
pins = "gpio6";
function = "emac0_mdio";
drive-strength = <16>;
bias-pull-up;
};
};
max98091_default: max98091-default-state {
pins = "gpio16";
function = "gpio";
bias-pull-up;
};
pcie1_default_state: pcie1-default-state {
wake-pins {
pins = "gpio21";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
clkreq-pins {
pins = "gpio22";
function = "pcie1_clkreq";
drive-strength = <2>;
bias-pull-up;
};
perst-pins {
pins = "gpio23";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
gpio_keys_default: gpio-keys-default-state {
pins = "gpio79";
function = "gpio";
bias-disable;
};
adv7535_default: adv7535-default-state {
pins = "gpio93";
function = "gpio";
bias-pull-up;
};
};
&uart7 {
status = "okay";
};
&usb_1 {
status = "okay";
};
/* Internally connected to the MCU (e.g. for DFU). */
&usb_2 {
dr_mode = "host";
status = "okay";
};

29
arch/arm64/boot/dts/qcom/monaco-el2.dtso Normal file
View File

@ -0,0 +1,29 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*
* Monaco specific modifications required to boot in EL2.
*/
/dts-v1/;
/plugin/;
&gpu_zap_shader {
status = "disabled";
};
&iris {
status = "disabled";
};
&remoteproc_adsp {
iommus = <&apps_smmu 0x2000 0x0>;
};
&remoteproc_cdsp {
iommus = <&apps_smmu 0x19c0 0x0400>;
};
&remoteproc_gpdsp {
iommus = <&apps_smmu 0x28a0 0x0>;
};

66
arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso Normal file
View File

@ -0,0 +1,66 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
#include <dt-bindings/gpio/gpio.h>
&camss {
vdda-phy-supply = <&vreg_l4a>;
vdda-pll-supply = <&vreg_l5a>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
csiphy1_ep: endpoint {
data-lanes = <0 1 2 3>;
remote-endpoint = <&imx577_ep1>;
};
};
};
};
&cci1 {
pinctrl-0 = <&cci1_0_default>;
pinctrl-1 = <&cci1_0_sleep>;
status = "okay";
};
&cci1_i2c0 {
#address-cells = <1>;
#size-cells = <0>;
camera@1a {
compatible = "sony,imx577";
reg = <0x1a>;
reset-gpios = <&expander2 1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&cam1_default>;
pinctrl-names = "default";
clocks = <&camcc CAM_CC_MCLK1_CLK>;
assigned-clocks = <&camcc CAM_CC_MCLK1_CLK>;
assigned-clock-rates = <24000000>;
avdd-supply = <&vreg_cam1_2p8>;
port {
imx577_ep1: endpoint {
link-frequencies = /bits/ 64 <600000000>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csiphy1_ep>;
};
};
};
};

149
arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso Normal file
View File

@ -0,0 +1,149 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
&{/} {
model = "Qualcomm Technologies, Inc. Monaco-EVK IFP Mezzanine";
vreg_0p9: regulator-0v9 {
compatible = "regulator-fixed";
regulator-name = "VREG_0P9";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
};
vreg_1p8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "VREG_1P8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
};
&i2c15 {
#address-cells = <1>;
#size-cells = <0>;
eeprom1: eeprom@52 {
compatible = "giantec,gt24c256c", "atmel,24c256";
reg = <0x52>;
pagesize = <64>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
};
};
};
&pcie0 {
iommu-map = <0x0 &pcie_smmu 0x0 0x1>,
<0x100 &pcie_smmu 0x1 0x1>,
<0x208 &pcie_smmu 0x2 0x1>,
<0x210 &pcie_smmu 0x3 0x1>,
<0x218 &pcie_smmu 0x4 0x1>,
<0x300 &pcie_smmu 0x5 0x1>,
<0x400 &pcie_smmu 0x6 0x1>,
<0x500 &pcie_smmu 0x7 0x1>,
<0x501 &pcie_smmu 0x8 0x1>;
};
&pcieport0 {
#address-cells = <3>;
#size-cells = <2>;
pcie@0,0 {
compatible = "pci1179,0623";
reg = <0x10000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
bus-range = <0x2 0xff>;
vddc-supply = <&vreg_0p9>;
vdd18-supply = <&vreg_1p8>;
vdd09-supply = <&vreg_0p9>;
vddio1-supply = <&vreg_1p8>;
vddio2-supply = <&vreg_1p8>;
vddio18-supply = <&vreg_1p8>;
i2c-parent = <&i2c15 0x77>;
resx-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&tc9563_resx_n>;
pinctrl-names = "default";
pcie@1,0 {
reg = <0x20800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
bus-range = <0x3 0xff>;
};
pcie@2,0 {
reg = <0x21000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
bus-range = <0x4 0xff>;
};
pcie@3,0 {
reg = <0x21800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
bus-range = <0x5 0xff>;
pci@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
};
pci@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
};
};
};
};
&tlmm {
tc9563_resx_n: tc9563-resx-state {
pins = "gpio124";
function = "gpio";
bias-disable;
/* Reset pin of tc9563 is active low hence set default
* state of this pin to output-high.
*/
output-high;
};
};

312
arch/arm64/boot/dts/qcom/monaco-evk.dts
View File

@ -21,12 +21,32 @@ aliases {
ethernet0 = &ethernet0;
i2c1 = &i2c1;
serial0 = &uart7;
serial2 = &uart6;
};
chosen {
stdout-path = "serial0:115200n8";
};
connector-2 {
compatible = "gpio-usb-b-connector", "usb-b-connector";
label = "micro-USB";
type = "micro";
id-gpios = <&pmm8620au_0_gpios 9 GPIO_ACTIVE_HIGH>;
vbus-gpios = <&expander6 7 GPIO_ACTIVE_HIGH>;
vbus-supply = <&usb2_vbus>;
pinctrl-0 = <&usb2_id>;
pinctrl-names = "default";
port {
usb2_con_hs_ep: endpoint {
remote-endpoint = <&usb_2_dwc3_hs>;
};
};
};
dmic: audio-codec-0 {
compatible = "dmic-codec";
#sound-dai-cells = <0>;
@ -38,6 +58,39 @@ max98357a: audio-codec-1 {
#sound-dai-cells = <0>;
};
dp-connector-0 {
compatible = "dp-connector";
label = "DP0";
type = "mini";
port {
dp0_connector_in: endpoint {
remote-endpoint = <&lt8713sx_dp0_out>;
};
};
};
dp-connector-1 {
compatible = "dp-connector";
label = "DP1";
type = "mini";
port {
dp1_connector_in: endpoint {
remote-endpoint = <&lt8713sx_dp1_out>;
};
};
};
usb2_vbus: regulator-usb2-vbus {
compatible = "regulator-fixed";
regulator-name = "usb2_vbus";
gpio = <&pmm8650au_1_gpios 7 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
};
sound {
compatible = "qcom,qcs8275-sndcard";
model = "MONACO-EVK";
@ -77,6 +130,57 @@ platform {
};
};
};
vreg_cam0_2p8: vreg-cam0-2p8 {
compatible = "regulator-fixed";
regulator-name = "vreg_cam0_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
startup-delay-us = <10000>;
gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&cam0_avdd_2v8_en_default>;
pinctrl-names = "default";
};
vreg_cam1_2p8: vreg-cam1-2p8 {
compatible = "regulator-fixed";
regulator-name = "vreg_cam1_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
startup-delay-us = <10000>;
gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&cam1_avdd_2v8_en_default>;
pinctrl-names = "default";
};
vreg_cam2_2p8: vreg-cam2-2p8 {
compatible = "regulator-fixed";
regulator-name = "vreg_cam2_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
startup-delay-us = <10000>;
gpio = <&tlmm 75 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&cam2_avdd_2v8_en_default>;
pinctrl-names = "default";
};
/* This comes from a PMIC handled within the SAIL domain */
vreg_s2s: vreg-s2s {
compatible = "regulator-fixed";
regulator-name = "vreg_s2s";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
&apps_rsc {
@ -318,6 +422,45 @@ &gpu_zap_shader {
firmware-name = "qcom/qcs8300/a623_zap.mbn";
};
&i2c0 {
status = "okay";
bridge@4f {
compatible = "lontium,lt8713sx";
reg = <0x4f>;
reset-gpios = <&expander5 6 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lt8713sx_dp_in: endpoint {
remote-endpoint = <&mdss_dp0_out>;
};
};
port@1 {
reg = <1>;
lt8713sx_dp0_out: endpoint {
remote-endpoint = <&dp0_connector_in>;
};
};
port@2 {
reg = <2>;
lt8713sx_dp1_out: endpoint {
remote-endpoint = <&dp1_connector_in>;
};
};
};
};
};
&i2c1 {
pinctrl-0 = <&qup_i2c1_default>;
pinctrl-names = "default";
@ -362,6 +505,11 @@ expander0: gpio@38 {
reg = <0x38>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
interrupts-extended = <&tlmm 56 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&expander0_int>;
pinctrl-names = "default";
};
expander1: gpio@39 {
@ -369,6 +517,11 @@ expander1: gpio@39 {
reg = <0x39>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
interrupts-extended = <&tlmm 16 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&expander1_int>;
pinctrl-names = "default";
};
expander2: gpio@3a {
@ -376,6 +529,11 @@ expander2: gpio@3a {
reg = <0x3a>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
interrupts-extended = <&tlmm 95 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&expander2_int>;
pinctrl-names = "default";
};
expander3: gpio@3b {
@ -383,6 +541,11 @@ expander3: gpio@3b {
reg = <0x3b>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
interrupts-extended = <&tlmm 24 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&expander3_int>;
pinctrl-names = "default";
};
expander4: gpio@3c {
@ -390,6 +553,11 @@ expander4: gpio@3c {
reg = <0x3c>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
interrupts-extended = <&tlmm 96 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&expander4_int>;
pinctrl-names = "default";
};
expander5: gpio@3d {
@ -397,6 +565,11 @@ expander5: gpio@3d {
reg = <0x3d>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&expander5_int>;
pinctrl-names = "default";
};
expander6: gpio@3e {
@ -404,6 +577,11 @@ expander6: gpio@3e {
reg = <0x3e>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
interrupts-extended = <&tlmm 52 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&expander6_int>;
pinctrl-names = "default";
};
};
@ -411,6 +589,30 @@ &iris {
status = "okay";
};
&mdss {
status = "okay";
};
&mdss_dp0 {
pinctrl-0 = <&dp_hot_plug_det>;
pinctrl-names = "default";
status = "okay";
};
&mdss_dp0_out {
data-lanes = <0 1 2 3>;
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
remote-endpoint = <&lt8713sx_dp_in>;
};
&mdss_dp0_phy {
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l4a>;
status = "okay";
};
&pcie0 {
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@ -449,6 +651,21 @@ &pcieport1 {
wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
};
&pmm8620au_0_gpios {
usb2_id: usb2-id-state {
pins = "gpio9";
function = "normal";
input-enable;
bias-pull-up;
power-source = <0>;
};
};
&qup_i2c0_data_clk {
drive-strength = <2>;
bias-pull-up;
};
&qupv3_id_0 {
firmware-name = "qcom/qcs8300/qupv3fw.elf";
status = "okay";
@ -477,6 +694,17 @@ &remoteproc_gpdsp {
status = "okay";
};
&sdhc_1 {
vmmc-supply = <&vreg_l8a>;
vqmmc-supply = <&vreg_s2s>;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&serdes0 {
phy-supply = <&vreg_l4a>;
@ -494,7 +722,6 @@ tpm@0 {
};
&tlmm {
pcie0_default_state: pcie0-default-state {
wake-pins {
pins = "gpio0";
@ -534,6 +761,18 @@ ethernet0_mdio: ethernet0-mdio-pins {
};
};
expander5_int: expander5-int-state {
pins = "gpio3";
function = "gpio";
bias-pull-up;
};
expander1_int: expander1-int-state {
pins = "gpio16";
function = "gpio";
bias-pull-up;
};
qup_i2c1_default: qup-i2c1-state {
pins = "gpio19", "gpio20";
function = "qup0_se1";
@ -564,12 +803,67 @@ perst-pins {
};
};
expander3_int: expander3-int-state {
pins = "gpio24";
function = "gpio";
bias-pull-up;
};
expander6_int: expander6-int-state {
pins = "gpio52";
function = "gpio";
bias-pull-up;
};
expander0_int: expander0-int-state {
pins = "gpio56";
function = "gpio";
bias-pull-up;
};
cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state {
pins = "gpio73";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
cam1_avdd_2v8_en_default: cam1-avdd-2v8-en-state {
pins = "gpio74";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
cam2_avdd_2v8_en_default: cam2-avdd-2v8-en-state {
pins = "gpio75";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
qup_i2c15_default: qup-i2c15-state {
pins = "gpio91", "gpio92";
function = "qup1_se7";
drive-strength = <2>;
bias-pull-up;
};
expander2_int: expander2-int-state {
pins = "gpio95";
function = "gpio";
bias-pull-up;
};
expander4_int: expander4-int-state {
pins = "gpio96";
function = "gpio";
bias-pull-up;
};
};
&uart6 {
status = "okay";
};
&uart7 {
@ -613,3 +907,19 @@ &usb_qmpphy {
status = "okay";
};
&usb_2 {
status = "okay";
};
&usb_2_dwc3_hs {
remote-endpoint = <&usb2_con_hs_ep>;
};
&usb_2_hsphy {
vdda-pll-supply = <&vreg_l7a>;
vdda18-supply = <&vreg_l7c>;
vdda33-supply = <&vreg_l9a>;
status = "okay";
};

323
arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi Normal file
View File

@ -0,0 +1,323 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "monaco.dtsi"
#include "monaco-pmics.dtsi"
/ {
/* This comes from a PMIC handled within the SAIL domain */
vreg_s2s: vreg-s2s {
compatible = "regulator-fixed";
regulator-name = "vreg_s2s";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "a";
vreg_l3a: ldo3 {
regulator-name = "vreg_l3a";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_l4a: ldo4 {
regulator-name = "vreg_l4a";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5a: ldo5 {
regulator-name = "vreg_l5a";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6a: ldo6 {
regulator-name = "vreg_l6a";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a: ldo7 {
regulator-name = "vreg_l7a";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8a: ldo8 {
regulator-name = "vreg_l8a";
regulator-min-microvolt = <2504000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9a: ldo9 {
regulator-name = "vreg_l9a";
regulator-min-microvolt = <2970000>;
regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-1 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "c";
vreg_s5c: smps5 { /* LPDDR VDD2H */
regulator-name = "vreg_s5c";
regulator-min-microvolt = <1104000>;
regulator-max-microvolt = <1104000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1c: ldo1 { /* LPDDR VDDQ */
regulator-name = "vreg_l1c";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <512000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2c: ldo2 { /* LPDDR VDD2L */
regulator-name = "vreg_l2c";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <904000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c: ldo4 {
regulator-name = "vreg_l4c";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c: ldo7 {
regulator-name = "vreg_l7c";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8c: ldo8 { /* LPDDR VDD1 */
regulator-name = "vreg_l8c";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9c: ldo9 { /* QFPROM */
regulator-name = "vreg_l9c";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>;
};
};
};
&mdss_dp0 {
pinctrl-0 = <&dp_hpd>;
pinctrl-names = "default";
};
&mdss_dp0_phy {
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l4a>;
};
&mdss_dsi0 {
vdda-supply = <&vreg_l5a>;
};
&mdss_dsi0_phy {
vdds-supply = <&vreg_l4a>;
};
&gpi_dma0 {
status = "okay";
};
&gpi_dma1 {
status = "okay";
};
&gpu {
status = "okay";
};
&gpu_zap_shader {
firmware-name = "qcom/qcs8300/a623_zap.mbn";
};
&iris {
status = "okay";
};
/* PCIe0 Gen4 x2 */
&pcie0 {
iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
<0x100 &pcie_smmu 0x0001 0x1>,
<0x200 &pcie_smmu 0x0007 0x1>,
<0x208 &pcie_smmu 0x0002 0x1>,
<0x210 &pcie_smmu 0x0003 0x1>,
<0x218 &pcie_smmu 0x0004 0x1>,
<0x300 &pcie_smmu 0x0005 0x1>,
<0x400 &pcie_smmu 0x0006 0x1>;
status = "okay";
};
&pcie0_phy {
vdda-phy-supply = <&vreg_l6a>;
vdda-pll-supply = <&vreg_l5a>;
status = "okay";
};
/* PCIe1 Gen4 x4 */
&pcie1 {
status = "okay";
};
&pcie1_phy {
vdda-phy-supply = <&vreg_l6a>;
vdda-pll-supply = <&vreg_l5a>;
status = "okay";
};
&qupv3_id_0 {
firmware-name = "qcom/qcs8300/qupv3fw.elf";
status = "okay";
};
&qupv3_id_1 {
firmware-name = "qcom/qcs8300/qupv3fw.elf";
status = "okay";
};
/* There is a HW/FW issue preventing proper REFGEN hardware voting
* for the USB2 HS PHY. As a workaround, we force REFGEN to stay
* always‑on in software, matching initial bootloader config.
*/
&refgen {
regulator-always-on;
};
&remoteproc_adsp {
firmware-name = "qcom/qcs8300/adsp.mbn";
status = "okay";
};
&remoteproc_cdsp {
firmware-name = "qcom/qcs8300/cdsp0.mbn";
status = "okay";
};
&remoteproc_gpdsp {
firmware-name = "qcom/qcs8300/gpdsp0.mbn";
status = "okay";
};
/* OnSom eMMC */
&sdhc_1 {
vmmc-supply = <&vreg_l8a>;
vqmmc-supply = <&vreg_s2s>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
/* Ethernet/SGMII */
&serdes0 {
phy-supply = <&vreg_l5a>;
status = "okay";
};
&tlmm {
dp_hpd: dp-hpd-state {
pins = "gpio94";
function = "edp0_hot";
bias-disable;
};
};
/* USB0 HS + SS */
&usb_1_hsphy {
vdda-pll-supply = <&vreg_l7a>;
vdda18-supply = <&vreg_l7c>;
vdda33-supply = <&vreg_l9a>;
status = "okay";
};
&usb_qmpphy {
vdda-phy-supply = <&vreg_l7a>;
vdda-pll-supply = <&vreg_l5a>;
status = "okay";
};
/* USB1 HS */
&usb_2_hsphy {
vdda-pll-supply = <&vreg_l7a>;
vdda18-supply = <&vreg_l7c>;
vdda33-supply = <&vreg_l9a>;
status = "okay";
};

617
arch/arm64/boot/dts/qcom/monaco.dtsi
View File

@ -3,6 +3,7 @@
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
@ -20,6 +21,7 @@
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@ -2234,6 +2236,10 @@ aggre1_noc: interconnect@16c0000 {
reg = <0x0 0x016c0000 0x0 0x17080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>,
<&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
};
aggre2_noc: interconnect@1700000 {
@ -2241,6 +2247,7 @@ aggre2_noc: interconnect@1700000 {
reg = <0x0 0x01700000 0x0 0x1a080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&rpmhcc RPMH_IPA_CLK>;
};
pcie_anoc: interconnect@1760000 {
@ -2866,6 +2873,75 @@ q6prmcc: clock-controller {
};
};
lpass_tlmm: pinctrl@3440000 {
compatible = "qcom,qcs8300-lpass-lpi-pinctrl", "qcom,sm8450-lpass-lpi-pinctrl";
reg = <0x0 0x03440000 0x0 0x20000>,
<0x0 0x034d0000 0x0 0x10000>;
clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 23>;
quad_mclk_active: quad-mclk-state {
clk-pins {
pins = "gpio5";
function = "ext_mclk1_c";
drive-strength = <8>;
bias-disable;
};
};
quad_mi2s_active: quad-active-state {
data-pins {
pins = "gpio2", "gpio3";
function = "qua_mi2s_data";
drive-strength = <8>;
bias-disable;
};
sclk-pins {
pins = "gpio0";
function = "qua_mi2s_sclk";
drive-strength = <8>;
bias-disable;
};
ws-pins {
pins = "gpio1";
function = "qua_mi2s_ws";
drive-strength = <8>;
bias-disable;
};
};
lpi_i2s4_active: lpi_i2s4-active-state {
data0-pins {
pins = "gpio17";
function = "i2s4_data";
drive-strength = <8>;
bias-disable;
};
clk-pins {
pins = "gpio12";
function = "i2s4_clk";
drive-strength = <8>;
bias-disable;
};
ws-pins {
pins = "gpio13";
function = "i2s4_ws";
drive-strength = <8>;
bias-disable;
};
};
};
lpass_ag_noc: interconnect@3c40000 {
compatible = "qcom,qcs8300-lpass-ag-noc";
reg = <0x0 0x03c40000 0x0 0x17200>;
@ -4740,11 +4816,21 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
interconnect-names = "sdhc-ddr",
"cpu-sdhc";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_state_on>;
pinctrl-1 = <&sdc1_state_off>;
qcom,dll-config = <0x000f64ee>;
qcom,ddr-config = <0x80040868>;
bus-width = <8>;
supports-cqe;
dma-coherent;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
status = "disabled";
sdhc1_opp_table: opp-table {
@ -5103,6 +5189,7 @@ gem_noc: interconnect@9100000 {
reg = <0x0 0x9100000 0x0 0xf7080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>;
};
llcc: system-cache-controller@9200000 {
@ -5171,9 +5258,29 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
usb-role-switch;
wakeup-source;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_1_dwc3_hs: endpoint {
};
};
port@1 {
reg = <1>;
usb_1_dwc3_ss: endpoint {
};
};
};
};
usb_2: usb@a400000 {
@ -5232,7 +5339,14 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
qcom,select-utmi-as-pipe-clk;
wakeup-source;
usb-role-switch;
status = "disabled";
port {
usb_2_dwc3_hs: endpoint {
};
};
};
iris: video-codec@aa00000 {
@ -5288,19 +5402,19 @@ opp-366000000 {
opp-444000000 {
opp-hz = /bits/ 64 <444000000>;
required-opps = <&rpmhpd_opp_nom>,
required-opps = <&rpmhpd_opp_svs_l1>,
<&rpmhpd_opp_nom>;
};
opp-533000000 {
opp-hz = /bits/ 64 <533000000>;
required-opps = <&rpmhpd_opp_turbo>,
required-opps = <&rpmhpd_opp_nom>,
<&rpmhpd_opp_turbo>;
};
opp-560000000 {
opp-hz = /bits/ 64 <560000000>;
required-opps = <&rpmhpd_opp_turbo_l1>,
required-opps = <&rpmhpd_opp_nom>,
<&rpmhpd_opp_turbo_l1>;
};
};
@ -5319,6 +5433,117 @@ videocc: clock-controller@abf0000 {
#power-domain-cells = <1>;
};
cci0: cci@ac13000 {
compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci";
reg = <0x0 0x0ac13000 0x0 0x1000>;
interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
clocks = <&camcc CAM_CC_CPAS_AHB_CLK>,
<&camcc CAM_CC_CCI_0_CLK>;
clock-names = "ahb",
"cci";
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
pinctrl-0 = <&cci0_0_default &cci0_1_default>;
pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
pinctrl-names = "default", "sleep";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
cci0_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci0_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
cci1: cci@ac14000 {
compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci";
reg = <0x0 0x0ac14000 0x0 0x1000>;
interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
clocks = <&camcc CAM_CC_CPAS_AHB_CLK>,
<&camcc CAM_CC_CCI_1_CLK>;
clock-names = "ahb",
"cci";
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
pinctrl-0 = <&cci1_0_default &cci1_1_default>;
pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
pinctrl-names = "default", "sleep";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
cci1_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci1_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
cci2: cci@ac15000 {
compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci";
reg = <0x0 0x0ac15000 0x0 0x1000>;
interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>;
clocks = <&camcc CAM_CC_CPAS_AHB_CLK>,
<&camcc CAM_CC_CCI_2_CLK>;
clock-names = "ahb",
"cci";
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
pinctrl-0 = <&cci2_0_default &cci2_1_default>;
pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
pinctrl-names = "default", "sleep";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
cci2_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci2_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
camss: isp@ac78000 {
compatible = "qcom,qcs8300-camss";
@ -5573,9 +5798,19 @@ port@0 {
reg = <0>;
dpu_intf0_out: endpoint {
remote-endpoint = <&mdss_dp0_in>;
};
};
port@1 {
reg = <1>;
dpu_intf1_out: endpoint {
remote-endpoint = <&mdss_dsi0_in>;
};
};
};
mdp_opp_table: opp-table {
@ -5603,6 +5838,98 @@ opp-650000000 {
};
};
mdss_dsi0: dsi@ae94000 {
compatible = "qcom,qcs8300-dsi-ctrl",
"qcom,sa8775p-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0x0 0x0ae94000 0x0 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>,
<&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
phys = <&mdss_dsi0_phy>;
operating-points-v2 = <&mdss_dsi_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
refgen-supply = <&refgen>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
mdss_dsi0_out: endpoint {
};
};
};
mdss_dsi_opp_table: opp-table {
compatible = "operating-points-v2";
opp-358000000 {
opp-hz = /bits/ 64 <358000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
mdss_dsi0_phy: phy@ae94400 {
compatible = "qcom,qcs8300-dsi-phy-5nm",
"qcom,sa8775p-dsi-phy-5nm";
reg = <0x0 0x0ae94400 0x0 0x200>,
<0x0 0x0ae94600 0x0 0x280>,
<0x0 0x0ae94900 0x0 0x280>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface",
"ref";
status = "disabled";
};
mdss_dp0_phy: phy@aec2a00 {
compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy";
@ -5697,8 +6024,8 @@ port@1 {
dp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-162000000 {
opp-hz = /bits/ 64 <162000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
@ -5730,7 +6057,9 @@ dispcc: clock-controller@af00000 {
<&mdss_dp0_phy 0>,
<&mdss_dp0_phy 1>,
<0>, <0>,
<0>, <0>, <0>, <0>;
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
<0>, <0>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
#clock-cells = <1>;
#reset-cells = <1>;
@ -5876,6 +6205,225 @@ tlmm: pinctrl@f100000 {
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
cam0_default: cam0-default-state {
pins = "gpio67";
function = "cam_mclk";
drive-strength = <2>;
bias-disable;
};
cam1_default: cam1-default-state {
pins = "gpio68";
function = "cam_mclk";
drive-strength = <2>;
bias-disable;
};
cam2_default: cam2-default-state {
pins = "gpio69";
function = "cam_mclk";
drive-strength = <2>;
bias-disable;
};
cci0_0_default: cci0-0-default-state {
sda-pins {
pins = "gpio57";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-up = <2200>;
};
scl-pins {
pins = "gpio58";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-up = <2200>;
};
};
cci0_0_sleep: cci0-0-sleep-state {
sda-pins {
pins = "gpio57";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-down;
};
scl-pins {
pins = "gpio58";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-down;
};
};
cci0_1_default: cci0-1-default-state {
sda-pins {
pins = "gpio29";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-up = <2200>;
};
scl-pins {
pins = "gpio30";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-up = <2200>;
};
};
cci0_1_sleep: cci0-1-sleep-state {
sda-pins {
pins = "gpio29";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-down;
};
scl-pins {
pins = "gpio30";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-down;
};
};
cci1_0_default: cci1-0-default-state {
sda-pins {
pins = "gpio59";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-up = <2200>;
};
scl-pins {
pins = "gpio60";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-up = <2200>;
};
};
cci1_0_sleep: cci1-0-sleep-state {
sda-pins {
pins = "gpio59";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-down;
};
scl-pins {
pins = "gpio60";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-down;
};
};
cci1_1_default: cci1-1-default-state {
sda-pins {
pins = "gpio31";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-up = <2200>;
};
scl-pins {
pins = "gpio32";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-up = <2200>;
};
};
cci1_1_sleep: cci1-1-sleep-state {
sda-pins {
pins = "gpio31";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-down;
};
scl-pins {
pins = "gpio32";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-down;
};
};
cci2_0_default: cci2-0-default-state {
sda-pins {
pins = "gpio61";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-up = <2200>;
};
scl-pins {
pins = "gpio62";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-up = <2200>;
};
};
cci2_0_sleep: cci2-0-sleep-state {
sda-pins {
pins = "gpio61";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-down;
};
scl-pins {
pins = "gpio62";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-down;
};
};
cci2_1_default: cci2-1-default-state {
sda-pins {
pins = "gpio54";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-up = <2200>;
};
scl-pins {
pins = "gpio55";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-up = <2200>;
};
};
cci2_1_sleep: cci2-1-sleep-state {
sda-pins {
pins = "gpio54";
function = "cci_i2c_sda";
drive-strength = <2>;
bias-pull-down;
};
scl-pins {
pins = "gpio55";
function = "cci_i2c_scl";
drive-strength = <2>;
bias-pull-down;
};
};
dp_hot_plug_det: dp-hot-plug-det-state {
pins = "gpio94";
function = "edp0_hot";
bias-disable;
};
hs0_mi2s_active: hs0-mi2s-active-state {
pins = "gpio106", "gpio107", "gpio108", "gpio109";
function = "hs0_mi2s";
@ -7192,6 +7740,55 @@ compute-cb@4 {
<&apps_smmu 0x1964 0x0400>;
dma-coherent;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x19c5 0x0400>;
dma-coherent;
};
compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
reg = <6>;
iommus = <&apps_smmu 0x19c6 0x0400>;
dma-coherent;
};
compute-cb@7 {
compatible = "qcom,fastrpc-compute-cb";
reg = <7>;
iommus = <&apps_smmu 0x19c7 0x0400>;
dma-coherent;
};
compute-cb@8 {
compatible = "qcom,fastrpc-compute-cb";
reg = <8>;
iommus = <&apps_smmu 0x19c8 0x0400>;
dma-coherent;
};
compute-cb@9 {
compatible = "qcom,fastrpc-compute-cb";
reg = <9>;
iommus = <&apps_smmu 0x19c9 0x0400>;
dma-coherent;
};
compute-cb@11 {
compatible = "qcom,fastrpc-compute-cb";
reg = <0xb>;
iommus = <&apps_smmu 0x19cb 0x0400>;
dma-coherent;
};
compute-cb@12 {
compatible = "qcom,fastrpc-compute-cb";
reg = <0xc>;
iommus = <&apps_smmu 0x19cc 0x000>;
dma-coherent;
};
};
};
};
@ -7707,9 +8304,9 @@ cpuss1-critical {
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};

18
arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts
View File

@ -16,6 +16,15 @@ &battery {
constant-charge-voltage-max-microvolt = <4350000>;
};
&charger {
richtek,usb-connector = <&usb_con_sm5502>;
status = "okay";
};
&muic_sm5502 {
status = "okay";
};
&st_accel {
status = "okay";
};
@ -23,3 +32,12 @@ &st_accel {
&st_magn {
status = "okay";
};
&usb {
extcon = <&muic_sm5502>, <&muic_sm5502>;
status = "okay";
};
&usb_hs_phy {
extcon = <&muic_sm5502>;
};

44
arch/arm64/boot/dts/qcom/msm8916-samsung-coreprimeltevzw.dts Normal file
View File

@ -0,0 +1,44 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "msm8916-samsung-rossa-common.dtsi"
/ {
model = "Samsung Galaxy Core Prime LTE Verizon Wireless";
compatible = "samsung,coreprimeltevzw", "qcom,msm8916";
chassis-type = "handset";
};
&battery {
charge-term-current-microamp = <150000>;
constant-charge-current-max-microamp = <700000>;
constant-charge-voltage-max-microvolt = <4400000>;
};
&charger {
richtek,usb-connector = <&usb_con_sm5502>;
status = "okay";
};
&mpss_mem {
/* Firmware for coreprimeltevzw needs more space */
reg = <0x0 0x86800000 0x0 0x5400000>;
};
&muic_sm5502 {
status = "okay";
};
&s3fwrn5_nfc {
status = "disabled";
};
&usb {
extcon = <&muic_sm5502>, <&muic_sm5502>;
status = "okay";
};
&usb_hs_phy {
extcon = <&muic_sm5502>;
};

32
arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi
View File

@ -144,14 +144,31 @@ reg_vdd_tsp_a: regulator-vdd-tsp-a {
&blsp_i2c1 {
status = "okay";
muic: extcon@25 {
/* MUIC/extcon varies depending on model variant */
muic_sm5504: extcon@14 {
compatible = "siliconmitus,sm5504-muic";
reg = <0x14>;
interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&muic_int_default>;
pinctrl-names = "default";
status = "disabled";
usb_con_sm5504: connector {
compatible = "usb-b-connector";
label = "micro-USB";
type = "micro";
};
};
muic_sm5502: extcon@25 {
compatible = "siliconmitus,sm5502-muic";
reg = <0x25>;
interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&muic_int_default>;
pinctrl-names = "default";
status = "disabled";
usb_con: connector {
usb_con_sm5502: connector {
compatible = "usb-b-connector";
label = "micro-USB";
type = "micro";
@ -298,7 +315,7 @@ rt5033_reg_safe_ldo: SAFE_LDO {
charger: charger {
compatible = "richtek,rt5033-charger";
monitored-battery = <&battery>;
richtek,usb-connector = <&usb_con>;
status = "disabled";
};
};
};
@ -348,15 +365,6 @@ &sound {
"AMIC3", "MIC BIAS External1";
};
&usb {
extcon = <&muic>, <&muic>;
status = "okay";
};
&usb_hs_phy {
extcon = <&muic>;
};
&venus {
status = "okay";
};

15
arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts
View File

@ -86,7 +86,7 @@ rt5033_reg_safe_ldo: SAFE_LDO {
charger: charger {
compatible = "richtek,rt5033-charger";
monitored-battery = <&battery>;
richtek,usb-connector = <&usb_con>;
richtek,usb-connector = <&usb_con_sm5502>;
};
};
};
@ -95,3 +95,16 @@ &mpss_mem {
/* Firmware for gprimeltecan needs more space */
reg = <0x0 0x86800000 0x0 0x5400000>;
};
&muic_sm5502 {
status = "okay";
};
&usb {
extcon = <&muic_sm5502>, <&muic_sm5502>;
status = "okay";
};
&usb_hs_phy {
extcon = <&muic_sm5502>;
};

18
arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts
View File

@ -24,7 +24,25 @@ &bosch_magn {
status = "okay";
};
&charger {
richtek,usb-connector = <&usb_con_sm5502>;
status = "okay";
};
&mpss_mem {
/* Firmware for grandprimelte needs more space */
reg = <0x0 0x86800000 0x0 0x5400000>;
};
&muic_sm5502 {
status = "okay";
};
&usb {
extcon = <&muic_sm5502>, <&muic_sm5502>;
status = "okay";
};
&usb_hs_phy {
extcon = <&muic_sm5502>;
};

19
arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi
View File

@ -2,28 +2,9 @@
#include "msm8916-samsung-fortuna-common.dtsi"
/* SM5504 MUIC instead of SM5502 */
/delete-node/ &muic;
/* IST3038 instead of Zinitix BT541 */
/delete-node/ &touchscreen;
&blsp_i2c1 {
muic: extcon@14 {
compatible = "siliconmitus,sm5504-muic";
reg = <0x14>;
interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&muic_int_default>;
pinctrl-names = "default";
usb_con: connector {
compatible = "usb-b-connector";
label = "micro-USB";
type = "micro";
};
};
};
&blsp_i2c5 {
touchscreen: touchscreen@50 {
compatible = "imagis,ist3038";

18
arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts
View File

@ -16,7 +16,25 @@ &battery {
constant-charge-voltage-max-microvolt = <4400000>;
};
&charger {
richtek,usb-connector = <&usb_con_sm5504>;
status = "okay";
};
&mpss_mem {
/* Firmware for rossa needs more space */
reg = <0x0 0x86800000 0x0 0x5800000>;
};
&muic_sm5504 {
status = "okay";
};
&usb {
extcon = <&muic_sm5504>, <&muic_sm5504>;
status = "okay";
};
&usb_hs_phy {
extcon = <&muic_sm5504>;
};

314
arch/arm64/boot/dts/qcom/msm8916-wiko-chuppito.dts Normal file
View File

@ -0,0 +1,314 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "msm8916-pm8916.dtsi"
#include "msm8916-modem-qdsp6.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
/ {
model = "Wiko Pulp 4G";
compatible = "wiko,chuppito", "qcom,msm8916";
chassis-type = "handset";
aliases {
mmc0 = &sdhc_1; /* eMMC */
mmc1 = &sdhc_2; /* SD card */
serial0 = &blsp_uart2;
};
chosen {
stdout-path = "serial0";
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pm8916_pwm 0 100000>;
brightness-levels = <0 255>;
num-interpolated-steps = <255>;
default-brightness-level = <255>;
enable-gpios = <&tlmm 119 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&button_backlight_default>;
pinctrl-names = "default";
};
gpio-hall-sensor {
compatible = "gpio-keys";
pinctrl-0 = <&gpio_hall_sensor_default>;
pinctrl-names = "default";
label = "Hall Effect Sensor";
event-hall-sensor {
label = "Hall Effect Sensor";
gpios = <&tlmm 117 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
linux,can-disable;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&gpio_keys_default>;
pinctrl-names = "default";
label = "Buttons";
button-volume-up {
label = "Volume up";
gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
};
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&usb_id_default>;
pinctrl-names = "default";
};
};
&blsp_i2c2 {
status = "okay";
magnetometer@c {
compatible = "asahi-kasei,ak09911";
reg = <0x0c>;
vdd-supply = <&pm8916_l17>;
vid-supply = <&pm8916_l6>;
reset-gpios = <&tlmm 120 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&mag_reset_default>;
pinctrl-names = "default";
mount-matrix = "1", "0", "0",
"0", "1", "0",
"0", "0", "1";
};
proximity@48 {
compatible = "sensortek,stk3310";
reg = <0x48>;
interrupts-extended = <&tlmm 113 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&proximity_int_default>;
pinctrl-names = "default";
};
imu@68 {
compatible = "invensense,mpu6880";
reg = <0x68>;
interrupts-extended = <&tlmm 115 IRQ_TYPE_EDGE_FALLING>;
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l6>;
pinctrl-0 = <&imu_int_default>;
pinctrl-names = "default";
mount-matrix = "0", "-1", "0",
"-1", "0", "0",
"0", "0", "-1";
};
};
&blsp_i2c5 {
status = "okay";
touchscreen@39 {
compatible = "syna,rmi4-i2c";
reg = <0x39>;
interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>;
vdd-supply = <&pm8916_l17>;
vio-supply = <&pm8916_l6>;
pinctrl-0 = <&touchscreen_default>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
syna,startup-delay-ms = <100>;
syna,reset-delay-ms = <160>;
rmi4-f01@1 {
reg = <0x1>;
syna,nosleep-mode = <1>;
};
rmi4-f11@11 {
reg = <0x11>;
syna,sensor-type = <1>;
};
};
};
&blsp_uart2 {
status = "okay";
};
&gpu {
status = "okay";
};
&mdss {
status = "okay";
};
&mpss_mem {
reg = <0x0 0x86800000 0x0 0x5600000>;
};
&pm8916_codec {
qcom,hphl-jack-type-normally-open;
};
&pm8916_mpps {
pwm_out: mpp4-state {
pins = "mpp4";
function = "digital";
power-source = <PM8916_MPP_VPH>;
output-low;
qcom,dtest = <1>;
};
};
&pm8916_pwm {
pinctrl-0 = <&pwm_out>;
pinctrl-names = "default";
status = "okay";
};
&pm8916_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&pm8916_rpm_regulators {
pm8916_l17: l17 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
};
&pm8916_vib {
status = "okay";
};
&sdhc_1 {
status = "okay";
};
&sdhc_2 {
pinctrl-0 = <&sdc2_default>, <&sdc2_cd_default>;
pinctrl-1 = <&sdc2_sleep>, <&sdc2_cd_default>;
pinctrl-names = "default", "sleep";
cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&sound {
audio-routing = "AMIC1", "MIC BIAS Internal1",
"AMIC2", "MIC BIAS Internal2";
};
&tlmm {
button_backlight_default: button-backlight-default-state {
pins = "gpio119";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
gpio_hall_sensor_default: gpio-hall-sensor-default-state {
pins = "gpio117";
function = "gpio";
drive-strength = <6>;
bias-pull-up;
};
gpio_keys_default: gpio-keys-default-state {
pins = "gpio107";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
imu_int_default: imu-int-default-state {
pins = "gpio115";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
mag_reset_default: mag-reset-default-state {
pins = "gpio120";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
proximity_int_default: proximity-int-default-state {
pins = "gpio113";
function = "gpio";
drive-strength = <6>;
bias-pull-up;
};
sdc2_cd_default: sdc2-cd-default-state {
pins = "gpio38";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
touchscreen_default: touchscreen-default-state {
touchscreen-pins {
pins = "gpio13";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
reset-pins {
pins = "gpio12";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
usb_id_default: usb-id-default-state {
pins = "gpio110";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
&usb {
extcon = <&usb_id>, <&usb_id>;
status = "okay";
};
&usb_hs_phy {
extcon = <&usb_id>;
};
&venus {
status = "okay";
};
&venus_mem {
status = "okay";
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
};
&wcnss_mem {
status = "okay";
};

310
arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts
View File

@ -5,28 +5,13 @@
/dts-v1/;
#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/gpio/gpio.h>
#include "msm8917.dtsi"
#include "pm8937.dtsi"
/delete-node/ &qseecom_mem;
#include "msm8917-xiaomi-wingtech.dtsi"
/ {
model = "Xiaomi Redmi 5A (riva)";
compatible = "xiaomi,riva", "qcom,msm8917";
chassis-type = "handset";
qcom,msm-id = <QCOM_ID_MSM8917 0>;
qcom,board-id = <0x1000b 2>, <0x2000b 2>;
pwm_backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pm8937_pwm 0 100000>;
brightness-levels = <0 255>;
num-interpolated-steps = <255>;
default-brightness-level = <128>;
};
qcom,board-id = <0x1000b 1>, <0x1000b 2>;
battery: battery {
compatible = "simple-battery";
@ -38,96 +23,18 @@ battery: battery {
charge-term-current-microamp = <60000>;
voltage-min-design-microvolt = <3400000>;
};
chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
stdout-path = "framebuffer0";
framebuffer0: framebuffer@90001000 {
compatible = "simple-framebuffer";
reg = <0x0 0x90001000 0x0 (720 * 1280 * 3)>;
width = <720>;
height = <1280>;
stride = <(720 * 3)>;
format = "r8g8b8";
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_VSYNC_CLK>,
<&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_BYTE0_CLK>,
<&gcc GCC_MDSS_PCLK0_CLK>,
<&gcc GCC_MDSS_ESC0_CLK>;
power-domains = <&gcc MDSS_GDSC>;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&gpio_keys_default>;
pinctrl-names = "default";
key-volup {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
debounce-interval = <15>;
};
};
vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-boot-on;
};
reserved-memory {
qseecom_mem: qseecom@84a00000 {
reg = <0x0 0x84a00000 0x0 0x1900000>;
no-map;
};
framebuffer_mem: memory@90001000 {
reg = <0x0 0x90001000 0x0 (720 * 1280 * 3)>;
no-map;
};
};
};
&blsp1_i2c3 {
status = "okay";
touchscreen@38 {
compatible = "edt,edt-ft5306";
reg = <0x38>;
interrupts-extended = <&tlmm 65 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&tsp_int_rst_default>;
pinctrl-names = "default";
vcc-supply = <&pm8937_l10>;
iovcc-supply = <&pm8937_l5>;
touchscreen-size-x = <720>;
touchscreen-size-y = <1280>;
};
};
&blsp2_i2c1 {
status = "okay";
bq27426@55 {
power-monitor@55 {
compatible = "ti,bq27426";
reg = <0x55>;
monitored-battery = <&battery>;
};
bq25601@6b {
charger@6b {
compatible = "ti,bq25601";
reg = <0x6b>;
interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>;
@ -139,172 +46,6 @@ bq25601@6b {
};
};
&pm8937_gpios {
pwm_enable_default: pwm-enable-default-state {
pins = "gpio8";
function = "dtest2";
output-low;
bias-disable;
qcom,drive-strength = <2>;
};
};
&pm8937_pwm {
pinctrl-0 = <&pwm_enable_default>;
pinctrl-names = "default";
status = "okay";
};
&pm8937_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&rpm_requests {
regulators-0 {
compatible = "qcom,rpm-pm8937-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_s2-supply = <&vph_pwr>;
vdd_s3-supply = <&vph_pwr>;
vdd_s4-supply = <&vph_pwr>;
vdd_l1_l19-supply = <&pm8937_s3>;
vdd_l2_l23-supply = <&pm8937_s3>;
vdd_l3-supply = <&pm8937_s3>;
vdd_l4_l5_l6_l7_l16-supply = <&pm8937_s4>;
vdd_l8_l11_l12_l17_l22-supply = <&vph_pwr>;
vdd_l9_l10_l13_l14_l15_l18-supply = <&vph_pwr>;
pm8937_s1: s1 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1225000>;
};
pm8937_s3: s3 {
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
};
pm8937_s4: s4 {
regulator-min-microvolt = <2050000>;
regulator-max-microvolt = <2050000>;
};
pm8937_l2: l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
pm8937_l5: l5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8937_l6: l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8937_l7: l7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8937_l8: l8 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2900000>;
};
pm8937_l9: l9 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
};
pm8937_l10: l10 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3000000>;
};
pm8937_l11: l11 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
regulator-system-load = <200000>;
};
pm8937_l12: l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
pm8937_l13: l13 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
};
pm8937_l14: l14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
pm8937_l15: l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
pm8937_l16: l16 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8937_l17: l17 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2900000>;
};
pm8937_l19: l19 {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1350000>;
};
pm8937_l22: l22 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
pm8937_l23: l23 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
};
};
&sdhc_1 {
vmmc-supply = <&pm8937_l8>;
vqmmc-supply = <&pm8937_l5>;
status = "okay";
};
&sdhc_2 {
cd-gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
vmmc-supply = <&pm8937_l11>;
vqmmc-supply = <&pm8937_l12>;
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
pinctrl-names = "default", "sleep";
status = "okay";
};
&sleep_clk {
clock-frequency = <32768>;
};
&tlmm {
bq25601_int_default: bq25601-int-default-state {
pins = "gpio61";
@ -312,47 +53,4 @@ bq25601_int_default: bq25601-int-default-state {
drive-strength = <2>;
bias-pull-up;
};
gpio_keys_default: gpio-keys-default-state {
pins = "gpio91";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
sdc2_cd_default: sdc2-cd-default-state {
pins = "gpio67";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tsp_int_rst_default: tsp-int-rst-default-state {
pins = "gpio64", "gpio65";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
&wcnss {
vddpx-supply = <&pm8937_l5>;
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
vddxo-supply = <&pm8937_l7>;
vddrfa-supply = <&pm8937_l19>;
vddpa-supply = <&pm8937_l9>;
vdddig-supply = <&pm8937_l5>;
};
&wcnss_mem {
status = "okay";
};
&xo_board {
clock-frequency = <19200000>;
};

15
arch/arm64/boot/dts/qcom/msm8917-xiaomi-rolex.dts Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2026, Barnabas Czeman
*/
/dts-v1/;
#include "msm8917-xiaomi-wingtech.dtsi"
/ {
model = "Xiaomi Redmi 4A (rolex)";
compatible = "xiaomi,rolex", "qcom,msm8917";
qcom,board-id = <0x1000b 1>;
};

20
arch/arm64/boot/dts/qcom/msm8917-xiaomi-tiare.dts Normal file
View File

@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2026, Barnabas Czeman
*/
/dts-v1/;
#include "msm8917-xiaomi-wingtech.dtsi"
/ {
model = "Xiaomi Redmi Go (tiare)";
compatible = "xiaomi,tiare", "qcom,msm8917";
qcom,board-id = <0x1000b 1>;
};
&pm8937_l22 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};

331
arch/arm64/boot/dts/qcom/msm8917-xiaomi-wingtech.dtsi Normal file
View File

@ -0,0 +1,331 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023, Barnabas Czeman
*/
/dts-v1/;
#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/gpio/gpio.h>
#include "msm8917.dtsi"
#include "pm8937.dtsi"
/delete-node/ &qseecom_mem;
/ {
chassis-type = "handset";
qcom,msm-id = <QCOM_ID_MSM8917 0>;
pwm_backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pm8937_pwm 0 100000>;
brightness-levels = <0 255>;
num-interpolated-steps = <255>;
default-brightness-level = <128>;
};
chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
framebuffer {
compatible = "simple-framebuffer";
memory-region = <&framebuffer_mem>;
width = <720>;
height = <1280>;
stride = <(720 * 3)>;
format = "r8g8b8";
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_VSYNC_CLK>,
<&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_BYTE0_CLK>,
<&gcc GCC_MDSS_PCLK0_CLK>,
<&gcc GCC_MDSS_ESC0_CLK>;
power-domains = <&gcc MDSS_GDSC>;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&gpio_keys_default>;
pinctrl-names = "default";
key-volup {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
debounce-interval = <15>;
};
};
vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-boot-on;
};
reserved-memory {
qseecom_mem: qseecom@84a00000 {
reg = <0x0 0x84a00000 0x0 0x1900000>;
no-map;
};
framebuffer_mem: memory@90001000 {
reg = <0x0 0x90001000 0x0 (720 * 1280 * 3)>;
no-map;
};
};
};
&blsp1_i2c3 {
status = "okay";
edt_ft5306: touchscreen@38 {
compatible = "edt,edt-ft5306";
reg = <0x38>;
interrupts-extended = <&tlmm 65 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&tsp_int_rst_default>;
pinctrl-names = "default";
vcc-supply = <&pm8937_l10>;
iovcc-supply = <&pm8937_l5>;
touchscreen-size-x = <720>;
touchscreen-size-y = <1280>;
status = "disabled";
};
goodix_gt911: touchscreen@5d {
compatible = "goodix,gt911";
reg = <0x5d>;
interrupts-extended = <&tlmm 65 IRQ_TYPE_LEVEL_LOW>;
irq-gpios = <&tlmm 65 GPIO_ACTIVE_HIGH>;
reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&tsp_int_rst_default>;
pinctrl-names = "default";
AVDD28-supply = <&pm8937_l10>;
VDDIO-supply = <&pm8937_l5>;
touchscreen-size-x = <720>;
touchscreen-size-y = <1280>;
status = "disabled";
};
};
&pm8937_gpios {
pwm_enable_default: pwm-enable-default-state {
pins = "gpio8";
function = "dtest2";
output-low;
bias-disable;
qcom,drive-strength = <2>;
};
};
&pm8937_pwm {
pinctrl-0 = <&pwm_enable_default>;
pinctrl-names = "default";
status = "okay";
};
&pm8937_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&rpm_requests {
regulators-0 {
compatible = "qcom,rpm-pm8937-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_s2-supply = <&vph_pwr>;
vdd_s3-supply = <&vph_pwr>;
vdd_s4-supply = <&vph_pwr>;
vdd_l1_l19-supply = <&pm8937_s3>;
vdd_l2_l23-supply = <&pm8937_s3>;
vdd_l3-supply = <&pm8937_s3>;
vdd_l4_l5_l6_l7_l16-supply = <&pm8937_s4>;
vdd_l8_l11_l12_l17_l22-supply = <&vph_pwr>;
vdd_l9_l10_l13_l14_l15_l18-supply = <&vph_pwr>;
pm8937_s1: s1 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1225000>;
};
pm8937_s3: s3 {
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
};
pm8937_s4: s4 {
regulator-min-microvolt = <2050000>;
regulator-max-microvolt = <2050000>;
};
pm8937_l2: l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
pm8937_l5: l5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8937_l6: l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8937_l7: l7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8937_l8: l8 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2900000>;
};
pm8937_l9: l9 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
};
pm8937_l10: l10 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3000000>;
};
pm8937_l11: l11 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
regulator-system-load = <200000>;
};
pm8937_l12: l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
pm8937_l13: l13 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
};
pm8937_l14: l14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
pm8937_l15: l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
pm8937_l16: l16 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8937_l17: l17 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2900000>;
};
pm8937_l19: l19 {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1350000>;
};
pm8937_l22: l22 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
pm8937_l23: l23 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
};
};
&sdhc_1 {
vmmc-supply = <&pm8937_l8>;
vqmmc-supply = <&pm8937_l5>;
status = "okay";
};
&sdhc_2 {
cd-gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
vmmc-supply = <&pm8937_l11>;
vqmmc-supply = <&pm8937_l12>;
pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
pinctrl-names = "default", "sleep";
status = "okay";
};
&sleep_clk {
clock-frequency = <32768>;
};
&tlmm {
gpio_keys_default: gpio-keys-default-state {
pins = "gpio91";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
sdc2_cd_default: sdc2-cd-default-state {
pins = "gpio67";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tsp_int_rst_default: tsp-int-rst-default-state {
pins = "gpio64", "gpio65";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
&wcnss {
vddpx-supply = <&pm8937_l5>;
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
vddxo-supply = <&pm8937_l7>;
vddrfa-supply = <&pm8937_l19>;
vddpa-supply = <&pm8937_l9>;
vdddig-supply = <&pm8937_l5>;
};
&wcnss_mem {
status = "okay";
};
&xo_board {
clock-frequency = <19200000>;
};

2
arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts
View File

@ -178,7 +178,7 @@ &pmi8950_wled {
qcom,num-strings = <2>;
qcom,external-pfet;
qcom,current-limit-microamp = <20000>;
qcom,ovp-millivolt = <29600>;
qcom,ovp-millivolt = <29500>;
status = "okay";
};

21
arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts
View File

@ -147,6 +147,20 @@ magnetometer@c {
pinctrl-names = "default";
};
light-sensor@60 {
compatible = "capella,cm36686", "vishay,vcnl4040";
reg = <0x60>;
interrupts-extended = <&tlmm 113 IRQ_TYPE_EDGE_FALLING>;
proximity-near-level = <30>;
vdd-supply = <&pm8916_l8>;
vio-supply = <&pm8916_l6>;
pinctrl-0 = <&light_int_default>;
pinctrl-names = "default";
};
imu@68 {
compatible = "invensense,mpu6515";
reg = <0x68>;
@ -330,4 +344,11 @@ mag_reset_default: mag-reset-default-state {
drive-strength = <2>;
bias-disable;
};
light_int_default: light-int-default-state {
pins = "gpio113";
function = "gpio";
drive-strength = <16>;
bias-pull-up;
};
};

2
arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts
View File

@ -157,7 +157,7 @@ &pm8953_resin {
&pmi8950_wled {
qcom,current-limit-microamp = <20000>;
qcom,num-strings = <2>;
qcom,num-strings = <3>;
status = "okay";
};

2
arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts
View File

@ -169,7 +169,7 @@ &pm8953_resin {
&pmi8950_wled {
qcom,current-limit-microamp = <20000>;
qcom,ovp-millivolt = <29600>;
qcom,ovp-millivolt = <29500>;
qcom,num-strings = <2>;
qcom,external-pfet;
qcom,cabc;

9
arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi
View File

@ -745,14 +745,7 @@ mdss_dsi_suspend: mdss-dsi-suspend-state {
bias-pull-down;
};
mdss_te_active: mdss-te-active-state {
pins = "gpio10";
function = "mdp_vsync";
drive-strength = <2>;
bias-pull-down;
};
mdss_te_suspend: mdss-te-suspend-state {
mdss_te: mdss-te-state {
pins = "gpio10";
function = "mdp_vsync";
drive-strength = <2>;

63
arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi
View File

@ -1,63 +0,0 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
*/
#include "msm8996.dtsi"
/ {
qcom,msm-id = <246 0x30000>;
};
/*
* This revision seems to have differ GPU CPR
* parameters, GPU frequencies and some differences
* when it comes to voltage delivery to.. once again
* the GPU. Funnily enough, it's simpler to make it an
* overlay on top of 3.1 (the final one) than vice versa.
* The differences will show here as more and more
* features get enabled upstream.
*/
gpu_opp_table_3_0: opp-table-gpu30 {
compatible = "operating-points-v2";
opp-624000000 {
opp-hz = /bits/ 64 <624000000>;
opp-level = <7>;
};
opp-560000000 {
opp-hz = /bits/ 64 <560000000>;
opp-level = <6>;
};
opp-510000000 {
opp-hz = /bits/ 64 <510000000>;
opp-level = <5>;
};
opp-401800000 {
opp-hz = /bits/ 64 <401800000>;
opp-level = <4>;
};
opp-315000000 {
opp-hz = /bits/ 64 <315000000>;
opp-level = <3>;
};
opp-214000000 {
opp-hz = /bits/ 64 <214000000>;
opp-level = <3>;
};
opp-133000000 {
opp-hz = /bits/ 64 <133000000>;
opp-level = <3>;
};
};
&gpu {
operating-points-v2 = <&gpu_opp_table_3_0>;
};

11
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
View File

@ -247,7 +247,7 @@ &mdss_dsi0 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mdss_dsi_default &mdss_te_default>;
pinctrl-1 = <&mdss_dsi_sleep &mdss_te_sleep>;
pinctrl-1 = <&mdss_dsi_sleep &mdss_te_default>;
};
&mdss_dsi0_out {
@ -730,14 +730,7 @@ mdss_dsi_sleep: mdss-dsi-sleep-state {
bias-pull-down;
};
mdss_te_default: mdss-te-default-state {
pins = "gpio10";
function = "mdp_vsync";
drive-strength = <2>;
bias-pull-down;
};
mdss_te_sleep: mdss-te-sleep-state {
mdss_te_default: mdss-te-state {
pins = "gpio10";
function = "mdp_vsync";
drive-strength = <2>;

2
arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts
View File

@ -104,7 +104,7 @@ &mdss_dsi0 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mdss_dsi_default &mdss_te_default>;
pinctrl-1 = <&mdss_dsi_sleep &mdss_te_sleep>;
pinctrl-1 = <&mdss_dsi_sleep &mdss_te_default>;
panel: panel@0 {
compatible = "jdi,fhd-r63452";

2
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@ -3255,7 +3255,7 @@ sdhc2: mmc@74a4900 {
bus-width = <4>;
status = "disabled";
};
};
blsp1_dma: dma-controller@7544000 {
compatible = "qcom,bam-v1.7.0";

2
arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts
View File

@ -51,7 +51,7 @@ &mdss_dsi0 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mdss_dsi_default &mdss_te_default>;
pinctrl-1 = <&mdss_dsi_sleep &mdss_te_sleep>;
pinctrl-1 = <&mdss_dsi_sleep &mdss_te_default>;
panel: panel@0 {
compatible = "jdi,fhd-r63452";

9
arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts
View File

@ -543,14 +543,7 @@ mdss_dsi_suspend_state: mdss-dsi-suspend-state {
bias-pull-down;
};
mdss_te_active_state: mdss-te-active-state {
pins = "gpio10";
function = "mdp_vsync_a";
drive-strength = <2>;
bias-pull-down;
};
mdss_te_suspend_state: mdss-te-suspend-state {
mdss_te_state: mdss-te-state {
pins = "gpio10";
function = "mdp_vsync_a";
drive-strength = <2>;

1
arch/arm64/boot/dts/qcom/pm6125.dtsi
View File

@ -138,7 +138,6 @@ pm6125_rtc: rtc@6000 {
reg = <0x6000>, <0x6100>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
pm6125_gpios: gpio@c000 {

93
arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi Normal file
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@ -0,0 +1,93 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pm8010-m-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pm8010_m_e1_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
pm8010-n-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pm8010_n_e1_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus1 {
pm8010_m_e1: pmic@c {
compatible = "qcom,pm8010", "qcom,spmi-pmic";
reg = <0xc SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8010_m_e1_temp_alarm: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
};
pm8010_n_e1: pmic@d {
compatible = "qcom,pm8010", "qcom,spmi-pmic";
reg = <0xd SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8010_n_e1_temp_alarm: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
};
};

187
arch/arm64/boot/dts/qcom/pmcx0102.dtsi Normal file
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@ -0,0 +1,187 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pmcx0102-c0-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmcx0102_c_e0_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
pmcx0102-c1-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmcx0102_c_e1_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
pmcx0102_d0_thermal: pmcx0102-d0-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmcx0102_d_e0_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
pmcx0102-d1-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmcx0102_d_e1_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus0 {
pmcx0102_c_e0: pmic@2 {
compatible = "qcom,pmcx0102", "qcom,spmi-pmic";
reg = <0x2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmcx0102_c_e0_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmcx0102_c_e0_gpios: gpio@8800 {
compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmcx0102_c_e0_gpios 0 0 14>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmcx0102_d_e0: pmic@3 {
compatible = "qcom,pmcx0102", "qcom,spmi-pmic";
reg = <0x3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmcx0102_d_e0_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmcx0102_d_e0_gpios: gpio@8800 {
compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmcx0102_d_e0_gpios 0 0 14>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
&spmi_bus1 {
pmcx0102_c_e1: pmic@2 {
compatible = "qcom,pmcx0102", "qcom,spmi-pmic";
reg = <0x2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmcx0102_c_e1_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmcx0102_c_e1_gpios: gpio@8800 {
compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmcx0102_c_e1_gpios 0 0 14>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmcx0102_d_e1: pmic@3 {
compatible = "qcom,pmcx0102", "qcom,spmi-pmic";
reg = <0x3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmcx0102_d_e1_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmcx0102_d_e1_gpios: gpio@8800 {
compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmcx0102_d_e1_gpios 0 0 14>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

62
arch/arm64/boot/dts/qcom/pmd8028-kaanapali.dtsi Normal file
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@ -0,0 +1,62 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pmd8028-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmd8028_e1_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus1 {
pmd8028_e1: pmic@4 {
compatible = "qcom,pmd8028", "qcom,spmi-pmic";
reg = <0x4 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmd8028_e1_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmd8028_e1_gpios: gpio@8800 {
compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmd8028_e1_gpios 0 0 4>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

68
arch/arm64/boot/dts/qcom/pmh0101.dtsi Normal file
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@ -0,0 +1,68 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pmh0101-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmh0101_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus0 {
pmic@1 {
compatible = "qcom,pmh0101", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmh0101_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmh0101_gpios: gpio@8800 {
compatible = "qcom,pmh0101-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmh0101_gpios 0 0 18>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pmh0101_flash: led-controller@ee00 {
compatible = "qcom,pmh0101-flash-led", "qcom,spmi-flash-led";
reg = <0xee00>;
status = "disabled";
};
pmh0101_pwm: pwm {
compatible = "qcom,pmh0101-pwm", "qcom,pm8350c-pwm";
#pwm-cells = <2>;
status = "disabled";
};
};
};

144
arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi Normal file
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@ -0,0 +1,144 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/{
thermal_zones {
pmh0104_i0_thermal: pmh0104-i0-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmh0104_i_e0_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
pmh0104_j0_thermal: pmh0104-j0-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmh0104_j_e0_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
pmh0104-l1-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmh0104_l_e1_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus0 {
pmh0104_i_e0: pmic@8 {
compatible = "qcom,pmh0104", "qcom,spmi-pmic";
reg = <0x8 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmh0104_i_e0_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmh0104_i_e0_gpios: gpio@8800 {
compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmh0104_i_e0_gpios 0 0 8>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmh0104_j_e0: pmic@9 {
compatible = "qcom,pmh0104", "qcom,spmi-pmic";
reg = <0x9 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmh0104_j_e0_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmh0104_j_e0_gpios: gpio@8800 {
compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmh0104_j_e0_gpios 0 0 8>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
&spmi_bus1 {
pmh0104_l_e1: pmic@b {
compatible = "qcom,pmh0104", "qcom,spmi-pmic";
reg = <0xb SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmh0104_l_e1_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0xb 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmh0104_l_e1_gpios: gpio@8800 {
compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmh0104_l_e1_gpios 0 0 8>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

63
arch/arm64/boot/dts/qcom/pmh0104-kaanapali.dtsi Normal file
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@ -0,0 +1,63 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pmh0104-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmh0104_j_e1_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus1 {
pmh0104_j_e1: pmic@9 {
compatible = "qcom,pmh0104", "qcom,spmi-pmic";
reg = <0x9 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmh0104_j_e1_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmh0104_j_e1_gpios: gpio@8800 {
compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmh0104_j_e1_gpios 0 0 8>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

144
arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi Normal file
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@ -0,0 +1,144 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pmh0110-f0-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmh0110_f_e0_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
pmh0110-f1-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmh0110_f_e1_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
pmh0110-h0-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmh0110_h_e0_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus0 {
pmh0110_f_e0: pmic@5 {
compatible = "qcom,pmh0110", "qcom,spmi-pmic";
reg = <0x5 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmh0110_f_e0_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmh0110_f_e0_gpios: gpio@8800 {
compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmh0110_f_e0_gpios 0 0 14>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmh0110_h_e0: pmic@7 {
compatible = "qcom,pmh0110", "qcom,spmi-pmic";
reg = <0x7 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmh0110_h_e0_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmh0110_h_e0_gpios: gpio@8800 {
compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmh0110_h_e0_gpios 0 0 14>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
&spmi_bus1 {
pmh0110_f_e1: pmic@5 {
compatible = "qcom,pmh0110", "qcom,spmi-pmic";
reg = <0x5 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmh0110_f_e1_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmh0110_f_e1_gpios: gpio@8800 {
compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmh0110_f_e1_gpios 0 0 14>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pmh0110-d-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmh0110_d_e0_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
pmh0110-f-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmh0110_f_e0_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
pmh0110-g-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmh0110_g_e0_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
pmh0110-i-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmh0110_i_e0_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus0 {
pmh0110_d_e0: pmic@3 {
compatible = "qcom,pmh0110", "qcom,spmi-pmic";
reg = <0x3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmh0110_d_e0_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmh0110_d_e0_gpios: gpio@8800 {
compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmh0110_d_e0_gpios 0 0 14>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmh0110_f_e0: pmic@5 {
compatible = "qcom,pmh0110", "qcom,spmi-pmic";
reg = <0x5 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmh0110_f_e0_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmh0110_f_e0_gpios: gpio@8800 {
compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmh0110_f_e0_gpios 0 0 14>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmh0110_g_e0: pmic@6 {
compatible = "qcom,pmh0110", "qcom,spmi-pmic";
reg = <0x6 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmh0110_g_e0_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmh0110_g_e0_gpios: gpio@8800 {
compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmh0110_g_e0_gpios 0 0 14>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmh0110_i_e0: pmic@8 {
compatible = "qcom,pmh0110", "qcom,spmi-pmic";
reg = <0x8 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmh0110_i_e0_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmh0110_i_e0_gpios: gpio@8800 {
compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmh0110_i_e0_gpios 0 0 14>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pmih0108-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmih0108_e1_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus1 {
pmih0108_e1: pmic@7 {
compatible = "qcom,pmih0108", "qcom,spmi-pmic";
reg = <0x7 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmih0108_e1_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmih0108_e1_gpios: gpio@8800 {
compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmih0108_e1_gpios 0 0 18>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pmih0108_e1_eusb2_repeater: phy@fd00 {
compatible = "qcom,pm8550b-eusb2-repeater";
reg = <0xfd00>;
#phy-cells = <0>;
};
};
};

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arch/arm64/boot/dts/qcom/pmk8550.dtsi
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@ -73,5 +73,15 @@ pmk8550_gpios: gpio@b800 {
interrupt-controller;
#interrupt-cells = <2>;
};
pmk8550_pwm: pwm {
compatible = "qcom,pmk8550-pwm";
#address-cells = <1>;
#size-cells = <0>;
#pwm-cells = <2>;
status = "disabled";
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus0 {
pmic@0 {
compatible = "qcom,pmk8850", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmk8850_pon: pon@1300 {
compatible = "qcom,pmk8350-pon";
reg = <0x1300>,
<0x800>;
reg-names = "hlos",
"pbs";
pon_pwrkey: pwrkey {
compatible = "qcom,pmk8350-pwrkey";
interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
linux,code = <KEY_POWER>;
};
pon_resin: resin {
compatible = "qcom,pmk8350-resin";
interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
status = "disabled";
};
};
pmk8850_gpios: gpio@b800 {
compatible = "qcom,pmk8850-gpio", "qcom,spmi-gpio";
reg = <0xb800>;
gpio-controller;
gpio-ranges = <&pmk8850_gpios 0 0 8>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pmk8850_rtc: rtc@6100 {
compatible = "qcom,pmk8350-rtc";
reg = <0x6100>,
<0x6200>;
reg-names = "rtc",
"alarm";
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
};
pmk8850_sdam_2: nvram@7100 {
compatible = "qcom,spmi-sdam";
reg = <0x7100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x7100 0x100>;
reboot_reason: reboot-reason@48 {
reg = <0x48 0x1>;
bits = <1 7>;
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pmr735d-thermal {
polling-delay-passive = <100>;
thermal-sensors = <&pmr735d_e1_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus1 {
pmr735d_e1: pmic@a {
compatible = "qcom,pmr735d", "qcom,spmi-pmic";
reg = <0xa SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmr735d_e1_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmr735d_e1_gpios: gpio@8800 {
compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmr735d_e1_gpios 0 0 2>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include "purwa.dtsi"
#include "hamoa-pmics.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
/delete-node/ &pmc8380_6;
/delete-node/ &pmc8380_6_thermal;
/ {
reserved-memory {
linux,cma {
compatible = "shared-dma-pool";
size = <0x0 0x8000000>;
reusable;
linux,cma-default;
};
};
};
&apps_rsc {
/* PMC8380C_B */
regulators-0 {
compatible = "qcom,pm8550-rpmh-regulators";
qcom,pmic-id = "b";
vdd-bob1-supply = <&vph_pwr>;
vdd-bob2-supply = <&vph_pwr>;
vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
vdd-l2-l13-l14-supply = <&vreg_bob1>;
vdd-l5-l16-supply = <&vreg_bob1>;
vdd-l6-l7-supply = <&vreg_bob2>;
vdd-l8-l9-supply = <&vreg_bob1>;
vdd-l12-supply = <&vreg_s5j_1p2>;
vdd-l15-supply = <&vreg_s4c_1p8>;
vdd-l17-supply = <&vreg_bob2>;
vreg_bob1: bob1 {
regulator-name = "vreg_bob1";
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_bob2: bob2 {
regulator-name = "vreg_bob2";
regulator-min-microvolt = <2504000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1b_1p8: ldo1 {
regulator-name = "vreg_l1b_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2b_3p0: ldo2 {
regulator-name = "vreg_l2b_3p0";
regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3100000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4b_1p8: ldo4 {
regulator-name = "vreg_l4b_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5b_3p0: ldo5 {
regulator-name = "vreg_l5b_3p0";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6b_1p8: ldo6 {
regulator-name = "vreg_l6b_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7b_2p8: ldo7 {
regulator-name = "vreg_l7b_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8b_3p0: ldo8 {
regulator-name = "vreg_l8b_3p0";
regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9b_2p9: ldo9 {
regulator-name = "vreg_l9b_2p9";
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10b_1p8: ldo10 {
regulator-name = "vreg_l10b_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12b_1p2: ldo12 {
regulator-name = "vreg_l12b_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_l13b_3p0: ldo13 {
regulator-name = "vreg_l13b_3p0";
regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3100000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l14b_3p0: ldo14 {
regulator-name = "vreg_l14b_3p0";
regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l15b_1p8: ldo15 {
regulator-name = "vreg_l15b_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_l16b_2p9: ldo16 {
regulator-name = "vreg_l16b_2p9";
regulator-min-microvolt = <2912000>;
regulator-max-microvolt = <2912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l17b_2p5: ldo17 {
regulator-name = "vreg_l17b_2p5";
regulator-min-microvolt = <2504000>;
regulator-max-microvolt = <2504000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
/* PMC8380VE_C */
regulators-1 {
compatible = "qcom,pm8550ve-rpmh-regulators";
qcom,pmic-id = "c";
vdd-l1-supply = <&vreg_s5j_1p2>;
vdd-l2-supply = <&vreg_s1f_0p7>;
vdd-l3-supply = <&vreg_s1f_0p7>;
vdd-s4-supply = <&vph_pwr>;
vreg_s4c_1p8: smps4 {
regulator-name = "vreg_s4c_1p8";
regulator-min-microvolt = <1856000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1c_1p2: ldo1 {
regulator-name = "vreg_l1c_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2c_0p8: ldo2 {
regulator-name = "vreg_l2c_0p8";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3c_0p8: ldo3 {
regulator-name = "vreg_l3c_0p8";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
/* PMC8380_D */
regulators-2 {
compatible = "qcom,pmc8380-rpmh-regulators";
qcom,pmic-id = "d";
vdd-l1-supply = <&vreg_s1f_0p7>;
vdd-l2-supply = <&vreg_s1f_0p7>;
vdd-l3-supply = <&vreg_s4c_1p8>;
vdd-s1-supply = <&vph_pwr>;
vreg_l1d_0p8: ldo1 {
regulator-name = "vreg_l1d_0p8";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2d_0p9: ldo2 {
regulator-name = "vreg_l2d_0p9";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3d_1p8: ldo3 {
regulator-name = "vreg_l3d_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
/* PMC8380_E */
regulators-3 {
compatible = "qcom,pmc8380-rpmh-regulators";
qcom,pmic-id = "e";
vdd-l2-supply = <&vreg_s1f_0p7>;
vdd-l3-supply = <&vreg_s5j_1p2>;
vreg_l2e_0p8: ldo2 {
regulator-name = "vreg_l2e_0p8";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3e_1p2: ldo3 {
regulator-name = "vreg_l3e_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
/* PMC8380_F */
regulators-4 {
compatible = "qcom,pmc8380-rpmh-regulators";
qcom,pmic-id = "f";
vdd-l1-supply = <&vreg_s5j_1p2>;
vdd-l2-supply = <&vreg_s5j_1p2>;
vdd-l3-supply = <&vreg_s5j_1p2>;
vdd-s1-supply = <&vph_pwr>;
vreg_s1f_0p7: smps1 {
regulator-name = "vreg_s1f_0p7";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1f_1p0: ldo1 {
regulator-name = "vreg_l1f_1p0";
regulator-min-microvolt = <1024000>;
regulator-max-microvolt = <1024000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2f_1p0: ldo2 {
regulator-name = "vreg_l2f_1p0";
regulator-min-microvolt = <1024000>;
regulator-max-microvolt = <1024000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3f_1p0: ldo3 {
regulator-name = "vreg_l3f_1p0";
regulator-min-microvolt = <1024000>;
regulator-max-microvolt = <1024000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
/* PMC8380VE_I */
regulators-6 {
compatible = "qcom,pm8550ve-rpmh-regulators";
qcom,pmic-id = "i";
vdd-l1-supply = <&vreg_s4c_1p8>;
vdd-l2-supply = <&vreg_s5j_1p2>;
vdd-l3-supply = <&vreg_s1f_0p7>;
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vreg_s1i_0p9: smps1 {
regulator-name = "vreg_s1i_0p9";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s2i_1p0: smps2 {
regulator-name = "vreg_s2i_1p0";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1100000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1i_1p8: ldo1 {
regulator-name = "vreg_l1i_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2i_1p2: ldo2 {
regulator-name = "vreg_l2i_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3i_0p8: ldo3 {
regulator-name = "vreg_l3i_0p8";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
/* PMC8380VE_J */
regulators-7 {
compatible = "qcom,pm8550ve-rpmh-regulators";
qcom,pmic-id = "j";
vdd-l1-supply = <&vreg_s1f_0p7>;
vdd-l2-supply = <&vreg_s5j_1p2>;
vdd-l3-supply = <&vreg_s1f_0p7>;
vdd-s5-supply = <&vph_pwr>;
vreg_s5j_1p2: smps5 {
regulator-name = "vreg_s5j_1p2";
regulator-min-microvolt = <1256000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1j_0p8: ldo1 {
regulator-name = "vreg_l1j_0p8";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2j_1p2: ldo2 {
regulator-name = "vreg_l2j_1p2";
regulator-min-microvolt = <1256000>;
regulator-max-microvolt = <1256000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3j_0p8: ldo3 {
regulator-name = "vreg_l3j_0p8";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
};
&gpu {
status = "okay";
};
&gpu_zap_shader {
firmware-name = "qcom/x1p42100/gen71500_zap.mbn";
};
&pcie3 {
pinctrl-0 = <&pcie3_default>;
pinctrl-names = "default";
status = "okay";
};
&pcie3_phy {
vdda-phy-supply = <&vreg_l3c_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&pcie4 {
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
status = "okay";
};
&pcie4_phy {
vdda-phy-supply = <&vreg_l3i_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&pcie5 {
pinctrl-0 = <&pcie5_default>;
pinctrl-names = "default";
status = "okay";
};
&pcie5_phy {
vdda-phy-supply = <&vreg_l3i_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&pcie6a {
pinctrl-0 = <&pcie6a_default>;
pinctrl-names = "default";
status = "okay";
};
&pcie6a_phy {
vdda-phy-supply = <&vreg_l1d_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;
status = "okay";
};
&qupv3_0 {
status = "okay";
};
&qupv3_1 {
status = "okay";
};
&qupv3_2 {
status = "okay";
};
&remoteproc_adsp {
firmware-name = "qcom/x1e80100/adsp.mbn",
"qcom/x1e80100/adsp_dtb.mbn";
status = "okay";
};
&remoteproc_cdsp {
firmware-name = "qcom/x1e80100/cdsp.mbn",
"qcom/x1e80100/cdsp_dtb.mbn";
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <34 2>; /* TPM LP & INT */
pcie3_default: pcie3-default-state {
clkreq-n-pins {
pins = "gpio144";
function = "pcie3_clk";
drive-strength = <2>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio143";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wake-n-pins {
pins = "gpio145";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie4_default: pcie4-default-state {
clkreq-n-pins {
pins = "gpio147";
function = "pcie4_clk";
drive-strength = <2>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio146";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wake-n-pins {
pins = "gpio148";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie5_default: pcie5-default-state {
clkreq-n-pins {
pins = "gpio150";
function = "pcie5_clk";
drive-strength = <2>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio149";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wake-n-pins {
pins = "gpio151";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie6a_default: pcie6a-default-state {
clkreq-n-pins {
pins = "gpio153";
function = "pcie6a_clk";
drive-strength = <2>;
bias-pull-up;
};
perst-n-pins {
pins = "gpio152";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wake-n-pins {
pins = "gpio154";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
&usb_1_ss0 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
&usb_1_ss0_hsphy {
vdd-supply = <&vreg_l3j_0p8>;
vdda12-supply = <&vreg_l2j_1p2>;
status = "okay";
};
&usb_1_ss0_qmpphy {
vdda-phy-supply = <&vreg_l2j_1p2>;
vdda-pll-supply = <&vreg_l1j_0p8>;
status = "okay";
};
&usb_1_ss1 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
&usb_1_ss1_hsphy {
vdd-supply = <&vreg_l3j_0p8>;
vdda12-supply = <&vreg_l2j_1p2>;
status = "okay";
};
&usb_1_ss1_qmpphy {
vdda-phy-supply = <&vreg_l2j_1p2>;
vdda-pll-supply = <&vreg_l2d_0p9>;
status = "okay";
};
&usb_1_ss2 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
&usb_1_ss2_hsphy {
vdd-supply = <&vreg_l3j_0p8>;
vdda12-supply = <&vreg_l2j_1p2>;
status = "okay";
};
&usb_1_ss2_qmpphy {
vdda-phy-supply = <&vreg_l2j_1p2>;
vdda-pll-supply = <&vreg_l2d_0p9>;
status = "okay";
};
&usb_2 {
dr_mode = "host";
status = "okay";
};
&usb_2_hsphy {
vdd-supply = <&vreg_l2e_0p8>;
vdda12-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&usb_mp {
status = "okay";
};
&usb_mp_hsphy0 {
vdd-supply = <&vreg_l2e_0p8>;
vdda12-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&usb_mp_hsphy1 {
vdd-supply = <&vreg_l2e_0p8>;
vdda12-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&usb_mp_qmpphy0 {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l3c_0p8>;
status = "okay";
};
&usb_mp_qmpphy1 {
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l3c_0p8>;
status = "okay";
};

606
arch/arm64/boot/dts/qcom/purwa.dtsi
View File

@ -20,7 +20,21 @@
/delete-node/ &gpu_opp_table;
/delete-node/ &gpu_speed_bin;
/delete-node/ &pcie3_phy;
/delete-node/ &thermal_zones;
/delete-node/ &thermal_aoss3;
/delete-node/ &thermal_cpu2_0_btm;
/delete-node/ &thermal_cpu2_0_top;
/delete-node/ &thermal_cpu2_1_btm;
/delete-node/ &thermal_cpu2_1_top;
/delete-node/ &thermal_cpu2_2_btm;
/delete-node/ &thermal_cpu2_2_top;
/delete-node/ &thermal_cpu2_3_btm;
/delete-node/ &thermal_cpu2_3_top;
/delete-node/ &thermal_cpuss2_btm;
/delete-node/ &thermal_cpuss2_top;
/delete-node/ &thermal_gpuss_4;
/delete-node/ &thermal_gpuss_5;
/delete-node/ &thermal_gpuss_6;
/delete-node/ &thermal_gpuss_7;
&gcc {
compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc";
@ -198,557 +212,47 @@ pcie3_phy: phy@1bd4000 {
};
};
&thermal_camera0 {
thermal-sensors = <&tsens2 9>;
};
&thermal_camera1 {
thermal-sensors = <&tsens2 10>;
};
&thermal_gpuss_0 {
thermal-sensors = <&tsens2 5>;
};
&thermal_gpuss_1 {
thermal-sensors = <&tsens2 6>;
};
&thermal_gpuss_2 {
thermal-sensors = <&tsens2 7>;
};
&thermal_gpuss_3 {
thermal-sensors = <&tsens2 8>;
};
&thermal_nsp0 {
thermal-sensors = <&tsens2 1>;
};
&thermal_nsp1 {
thermal-sensors = <&tsens2 2>;
};
&thermal_nsp2 {
thermal-sensors = <&tsens2 3>;
};
&thermal_nsp3 {
thermal-sensors = <&tsens2 4>;
};
/* While physically present, this controller is left unconfigured and unused */
&tsens3 {
status = "disabled";
};
/ {
thermal-zones {
aoss0-thermal {
thermal-sensors = <&tsens0 0>;
trips {
trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
trip-point1 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu0-0-top-thermal {
thermal-sensors = <&tsens0 1>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu0-0-btm-thermal {
thermal-sensors = <&tsens0 2>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu0-1-top-thermal {
thermal-sensors = <&tsens0 3>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu0-1-btm-thermal {
thermal-sensors = <&tsens0 4>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu0-2-top-thermal {
thermal-sensors = <&tsens0 5>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu0-2-btm-thermal {
thermal-sensors = <&tsens0 6>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu0-3-top-thermal {
thermal-sensors = <&tsens0 7>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu0-3-btm-thermal {
thermal-sensors = <&tsens0 8>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpuss0-top-thermal {
thermal-sensors = <&tsens0 9>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpuss0-btm-thermal {
thermal-sensors = <&tsens0 10>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
mem-thermal {
thermal-sensors = <&tsens0 11>;
trips {
trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
trip-point1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
video-thermal {
thermal-sensors = <&tsens0 12>;
trips {
trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
trip-point1 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
aoss1-thermal {
thermal-sensors = <&tsens1 0>;
trips {
trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
trip-point1 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu1-0-top-thermal {
thermal-sensors = <&tsens1 1>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu1-0-btm-thermal {
thermal-sensors = <&tsens1 2>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu1-1-top-thermal {
thermal-sensors = <&tsens1 3>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu1-1-btm-thermal {
thermal-sensors = <&tsens1 4>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu1-2-top-thermal {
thermal-sensors = <&tsens1 5>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu1-2-btm-thermal {
thermal-sensors = <&tsens1 6>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu1-3-top-thermal {
thermal-sensors = <&tsens1 7>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpu1-3-btm-thermal {
thermal-sensors = <&tsens1 8>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpuss1-top-thermal {
thermal-sensors = <&tsens1 9>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
cpuss1-btm-thermal {
thermal-sensors = <&tsens1 10>;
trips {
trip-point0 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
aoss2-thermal {
thermal-sensors = <&tsens2 0>;
trips {
trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
trip-point1 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
nsp0-thermal {
thermal-sensors = <&tsens2 1>;
trips {
trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
trip-point1 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
nsp1-thermal {
thermal-sensors = <&tsens2 2>;
trips {
trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
trip-point1 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
nsp2-thermal {
thermal-sensors = <&tsens2 3>;
trips {
trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
trip-point1 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
nsp3-thermal {
thermal-sensors = <&tsens2 4>;
trips {
trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
trip-point1 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
gpuss-0-thermal {
polling-delay-passive = <200>;
thermal-sensors = <&tsens2 5>;
cooling-maps {
map0 {
trip = <&gpuss0_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpuss0_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
gpuss-1-thermal {
polling-delay-passive = <200>;
thermal-sensors = <&tsens2 6>;
cooling-maps {
map0 {
trip = <&gpuss1_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpuss1_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
gpuss-2-thermal {
polling-delay-passive = <200>;
thermal-sensors = <&tsens2 7>;
cooling-maps {
map0 {
trip = <&gpuss2_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpuss2_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
gpuss-3-thermal {
polling-delay-passive = <200>;
thermal-sensors = <&tsens2 8>;
cooling-maps {
map0 {
trip = <&gpuss3_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
gpuss3_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
trip-point1 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
camera0-thermal {
thermal-sensors = <&tsens2 9>;
trips {
trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
trip-point1 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
camera1-thermal {
thermal-sensors = <&tsens2 10>;
trips {
trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
trip-point1 {
temperature = <115000>;
hysteresis = <1000>;
type = "critical";
};
};
};
};
};

121
arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
View File

@ -12,6 +12,7 @@
#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/media/video-interfaces.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/sound/qcom,q6asm.h>
@ -626,6 +627,23 @@ vreg_bob: bob {
};
};
&camss {
vdda-phy-supply = <&vreg_l10c>;
vdda-pll-supply = <&vreg_l6b>;
status = "okay";
ports {
port@3 {
csiphy3_ep: endpoint {
data-lanes = <0 1 2 3>;
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
remote-endpoint = <&camera_s5kjn1_ep>;
};
};
};
};
&cci0 {
status = "okay";
};
@ -666,7 +684,34 @@ &cci1 {
};
&cci1_i2c1 {
/* S5KJN1SQ03 @ 10 */
camera@10 {
compatible = "samsung,s5kjn1";
reg = <0x10>;
vdda-supply = <&vreg_l3p>;
vddd-supply = <&vreg_l2p>;
vddio-supply = <&vreg_l6p>;
clocks = <&camcc CAM_CC_MCLK3_CLK>;
assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>;
assigned-clock-rates = <24000000>;
reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&cam_mclk3_default>;
pinctrl-names = "default";
orientation = <0>; /* Front facing */
rotation = <270>;
port {
camera_s5kjn1_ep: endpoint {
data-lanes = <1 2 3 4>;
link-frequencies = /bits/ 64 <700000000>;
remote-endpoint = <&csiphy3_ep>;
};
};
};
eeprom@51 {
compatible = "giantec,gt24p128f", "atmel,24c128";
@ -1257,41 +1302,6 @@ &tlmm {
*/
gpio-reserved-ranges = <32 2>, <56 4>;
bluetooth_enable_default: bluetooth-enable-default-state {
pins = "gpio85";
function = "gpio";
output-low;
bias-disable;
};
disp_reset_n_active: disp-reset-n-active-state {
pins = "gpio44";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
disp_reset_n_suspend: disp-reset-n-suspend-state {
pins = "gpio44";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
hall_sensor_default: hall-sensor-default-state {
pins = "gpio155";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
mdp_vsync: mdp-vsync-state {
pins = "gpio80";
function = "mdp_vsync";
drive-strength = <2>;
bias-pull-down;
};
pm8008_int_default: pm8008-int-default-state {
pins = "gpio25";
function = "gpio";
@ -1345,9 +1355,17 @@ qup_uart7_sleep_rx: qup-uart7-sleep-rx-state {
bias-pull-up;
};
sw_ctrl_default: sw-ctrl-default-state {
pins = "gpio86";
disp_reset_n_active: disp-reset-n-active-state {
pins = "gpio44";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
disp_reset_n_suspend: disp-reset-n-suspend-state {
pins = "gpio44";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
@ -1359,12 +1377,39 @@ usb_redrive_1v8_en_default: usb-redrive-1v8-en-default-state {
output-high;
};
mdp_vsync: mdp-vsync-state {
pins = "gpio80";
function = "mdp_vsync";
drive-strength = <2>;
bias-pull-down;
};
bluetooth_enable_default: bluetooth-enable-default-state {
pins = "gpio85";
function = "gpio";
output-low;
bias-disable;
};
sw_ctrl_default: sw-ctrl-default-state {
pins = "gpio86";
function = "gpio";
bias-pull-down;
};
aw86927_int_default: aw86927-int-default-state {
pins = "gpio101";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
hall_sensor_default: hall-sensor-default-state {
pins = "gpio155";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
&uart5 {

169
arch/arm64/boot/dts/qcom/qcm6490-idp.dts
View File

@ -36,6 +36,7 @@ / {
aliases {
serial0 = &uart5;
serial1 = &uart7;
};
pm8350c_pwm_backlight: backlight {
@ -194,6 +195,63 @@ wcd9370: audio-codec-0 {
#sound-dai-cells = <1>;
};
wcn6750-pmu {
compatible = "qcom,wcn6750-pmu";
pinctrl-0 = <&bt_en>;
pinctrl-names = "default";
vddaon-supply = <&vreg_s7b_0p972>;
vddasd-supply = <&vreg_l11c_2p8>;
vddpmu-supply = <&vreg_s7b_0p972>;
vddrfa0p8-supply = <&vreg_s7b_0p972>;
vddrfa1p2-supply = <&vreg_s8b_1p272>;
vddrfa1p7-supply = <&vreg_s1b_1p872>;
vddrfa2p2-supply = <&vreg_s1c_2p19>;
bt-enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>;
regulators {
vreg_pmu_rfa_cmn: ldo0 {
regulator-name = "vreg_pmu_rfa_cmn";
};
vreg_pmu_aon_0p59: ldo1 {
regulator-name = "vreg_pmu_aon_0p59";
};
vreg_pmu_wlcx_0p8: ldo2 {
regulator-name = "vreg_pmu_wlcx_0p8";
};
vreg_pmu_wlmx_0p85: ldo3 {
regulator-name = "vreg_pmu_wlmx_0p85";
};
vreg_pmu_btcmx_0p85: ldo4 {
regulator-name = "vreg_pmu_btcmx_0p85";
};
vreg_pmu_rfa_0p8: ldo5 {
regulator-name = "vreg_pmu_rfa_0p8";
};
vreg_pmu_rfa_1p2: ldo6 {
regulator-name = "vreg_pmu_rfa_1p2";
};
vreg_pmu_rfa_1p7: ldo7 {
regulator-name = "vreg_pmu_rfa_1p7";
};
vreg_pmu_pcie_0p9: ldo8 {
regulator-name = "vreg_pmu_pcie_0p9";
};
vreg_pmu_pcie_1p8: ldo9 {
regulator-name = "vreg_pmu_pcie_1p8";
};
};
};
};
&apps_rsc {
@ -695,6 +753,39 @@ &pon_resin {
status = "okay";
};
&qup_uart7_cts {
/*
* Configure a bias-bus-hold on CTS to lower power
* usage when Bluetooth is turned off. Bus hold will
* maintain a low power state regardless of whether
* the Bluetooth module drives the pin in either
* direction or leaves the pin fully unpowered.
*/
bias-bus-hold;
};
&qup_uart7_rts {
/* We'll drive RTS, so no pull */
drive-strength = <2>;
bias-disable;
};
&qup_uart7_rx {
/*
* Configure a pull-up on RX. This is needed to avoid
* garbage data when the TX pin of the Bluetooth module is
* in tri-state (module powered off or not driving the
* signal yet).
*/
bias-pull-up;
};
&qup_uart7_tx {
/* We'll drive TX, so no pull */
drive-strength = <2>;
bias-disable;
};
&qupv3_id_0 {
status = "okay";
};
@ -920,6 +1011,59 @@ &tlmm {
gpio-reserved-ranges = <32 2>, /* ADSP */
<48 4>; /* NFC */
bt_en: bt-en-state {
pins = "gpio85";
function = "gpio";
output-low;
bias-disable;
};
qup_uart7_sleep_cts: qup-uart7-sleep-cts-state {
pins = "gpio28";
function = "gpio";
/*
* Configure a bias-bus-hold on CTS to lower power
* usage when Bluetooth is turned off. Bus hold will
* maintain a low power state regardless of whether
* the Bluetooth module drives the pin in either
* direction or leaves the pin fully unpowered.
*/
bias-bus-hold;
};
qup_uart7_sleep_rts: qup-uart7-sleep-rts-state {
pins = "gpio29";
function = "gpio";
/*
* Configure pull-down on RTS. As RTS is active low
* signal, pull it low to indicate the BT SoC that it
* can wakeup the system anytime from suspend state by
* pulling RX low (by sending wakeup bytes).
*/
bias-pull-down;
};
qup_uart7_sleep_rx: qup-uart7-sleep-rx-state {
pins = "gpio31";
function = "gpio";
/*
* Configure a pull-up on RX. This is needed to avoid
* garbage data when the TX pin of the Bluetooth module
* is floating which may cause spurious wakeups.
*/
bias-pull-up;
};
qup_uart7_sleep_tx: qup-uart7-sleep-tx-state {
pins = "gpio30";
function = "gpio";
/*
* Configure pull-up on TX when it isn't actively driven
* to prevent BT SoC from receiving garbage during sleep.
*/
bias-pull-up;
};
sd_cd: sd-cd-state {
pins = "gpio91";
function = "gpio";
@ -938,6 +1082,31 @@ &uart5 {
status = "okay";
};
&uart7 {
/delete-property/ interrupts;
interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
pinctrl-1 = <&qup_uart7_sleep_cts>,
<&qup_uart7_sleep_rts>,
<&qup_uart7_sleep_tx>,
<&qup_uart7_sleep_rx>;
pinctrl-names = "default",
"sleep";
status = "okay";
bluetooth: bluetooth {
compatible = "qcom,wcn6750-bt";
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
vddaon-supply = <&vreg_pmu_aon_0p59>;
vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
max-speed = <3200000>;
};
};
&ufs_mem_hc {
reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l7b_2p952>;

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