This was done entirely with mindless brute force, using
git grep -l '\<k[vmz]*alloc_objs*(.*, GFP_KERNEL)' |
xargs sed -i 's/\(alloc_objs*(.*\), GFP_KERNEL)/\1)/'
to convert the new alloc_obj() users that had a simple GFP_KERNEL
argument to just drop that argument.
Note that due to the extreme simplicity of the scripting, any slightly
more complex cases spread over multiple lines would not be triggered:
they definitely exist, but this covers the vast bulk of the cases, and
the resulting diff is also then easier to check automatically.
For the same reason the 'flex' versions will be done as a separate
conversion.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This is the result of running the Coccinelle script from
scripts/coccinelle/api/kmalloc_objs.cocci. The script is designed to
avoid scalar types (which need careful case-by-case checking), and
instead replace kmalloc-family calls that allocate struct or union
object instances:
Single allocations: kmalloc(sizeof(TYPE), ...)
are replaced with: kmalloc_obj(TYPE, ...)
Array allocations: kmalloc_array(COUNT, sizeof(TYPE), ...)
are replaced with: kmalloc_objs(TYPE, COUNT, ...)
Flex array allocations: kmalloc(struct_size(PTR, FAM, COUNT), ...)
are replaced with: kmalloc_flex(*PTR, FAM, COUNT, ...)
(where TYPE may also be *VAR)
The resulting allocations no longer return "void *", instead returning
"TYPE *".
Signed-off-by: Kees Cook <kees@kernel.org>
There's no need to calculate HHI_HDMI_PLL_CNTL + 8 when we have a
HHI_HDMI_PLL_CNTL3 macro that has the correct offset already. No
functional changes, this makes it easier to compare the driver with the
datasheets.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20260105204710.447779-4-martin.blumenstingl@googlemail.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
GXBB has the HDMI PLL OD in the HHI_HDMI_PLL_CNTL2 register while for
G12A/G12B/SM1 the OD has moved to HHI_HDMI_PLL_CNTL0. At first glance
the rest of the OD setup seems identical.
However, looking at the downstream kernel sources as well as testing
shows that G12A/G12B/SM1 only supports three OD values:
- register value 0 means: divide by 1
- register value 1 means: divide by 2
- register value 2 means: divide by 4
Downstream sources are also only using OD register values 0, 1 and 2
for G12A/G12B/SM1 (while for GXBB the downstream kernel sources are also
using value 3 which means: divide by 8).
Add clk_div_table and have it replace the CLK_DIVIDER_POWER_OF_TWO flag
to make the kernel's view of this register match with how the hardware
actually works.
Fixes: 085a4ea93d ("clk: meson: g12a: add peripheral clock controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20260105204710.447779-3-martin.blumenstingl@googlemail.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
GXBB has the HDMI PLL OD in the HHI_HDMI_PLL_CNTL2 register while for
GXL/GXM the OD has moved to HHI_HDMI_PLL_CNTL3. At first glance the rest
of the OD setup seems identical.
However, looking at the downstream kernel sources as well as testing
shows that GXL only supports three OD values:
- register value 0 means: divide by 1
- register value 1 means: divide by 2
- register value 2 means: divide by 4
Using register value 3 (which on GXBB means: divide by 8) still divides
by 4 as verified using meson-clk-measure. Downstream sources are also
only using OD register values 0, 1 and 2 for GXL (while for GXBB the
downstream kernel sources are also using value 3).
Add clk_div_table and have it replace the CLK_DIVIDER_POWER_OF_TWO flag
to make the kernel's view of this register match with how the hardware
actually works.
Fixes: 69d9229327 ("clk: meson: add the gxl hdmi pll")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20260105204710.447779-2-martin.blumenstingl@googlemail.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
The video clocks enci, encp, vdac and hdmitx share the same clock
source. Adding CLK_SET_RATE_PARENT to the mux may unintentionally change
the shared parent clock, which could affect other video clocks.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20250919-add_video_clk-v6-3-fe223161fb3f@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Use the composite clock helpers to define simple composite clocks of
the c3-peripherals clock controller.
This reduces the verbosity of the controller code on these very simple
parts, making maintenance simpler.
Reviewed-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-12-0f402f01e117@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
s4 and c3 follow exactly the same structure when it comes to PWM clocks but
differ in the way these clocks are described, for no obvious reason.
Align the description of the pwm clocks of these SoCs with the composite
clock helpers.
Reviewed-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-11-0f402f01e117@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Device composite clocks tend to reproduce the usual sel/div/gate
arrangement.
Add macros to help define simple composite clocks in the system.
The idea is _not_ to replace all instances of mux, div or gate with those
macros. It is rather to use it for recurring and/or simple composite
clocks, reducing controller verbosity where it makes sense. This should
help reviews focus on the tricky parts.
Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-10-0f402f01e117@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
All Amlogic peripheral clocks are more or less the same. The only thing
that differs is the parent data.
Adapt the common pclk definition so it takes clk_parent_data and can be
used by all controllers.
Reviewed-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-8-0f402f01e117@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Every usage of CLK_IGNORE_UNUSED should be explicitly motivated and
documented. However, the PCLK macros used by most Amlogic platforms are
adding that flag systematically. Because of this, all pclks are marked with
CLK_IGNORE_UNUSED, without any form of distinction or motivation.
This may have been fine in the early days of CCF but it is not anymore.
Just removing the flag is not an option at this stage since it could cause
regression on existing platforms.
Instead, drop the flag from the macro definition and add it to the each
clock definition, for the existing clocks. This makes quite a nasty change
but it will make it a lot easier for people to contribute to fixing the
problem, clock by clock. It will also prevent new platform from being added
with a silent use of the flag.
Reviewed-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-7-0f402f01e117@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
On Amlogic SoCs, the rate of a peripheral clock should not be changed,
let alone the rate of the parent PLL.
These clocks are meant to be used as provided by the parent PLL. Changing
the rate would be dangerous and would likely break a lot of devices running
from the same PLL.
Don't propagate any rate change request that may come from these clocks and
drop the corresponding flag.
Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-6-0f402f01e117@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
clk-regmap was always meant to stay generic, without any amlogic specifics.
The hope was that it could move out of the amlogic directory one day.
Even if this may actually not become true, it should remain generic.
Move the amlogic peripheral clock definition out of clk-regmap header.
Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-5-0f402f01e117@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Factorize the probe function of the mmio based amlogic clock controllers
using the newly introduced probe helper. This removes a fair amount
of duplicated code.
Reviewed-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-3-0f402f01e117@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
What is being done by the Amlogic clock controller registration helper for
EE controllers could benefit other controllers. As such, having a specific
module for this makes little sense.
Move the helper function to clkc-utils and rename it to describe what it
does, registering syscon based controller, instead of what it serves.
Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-1-0f402f01e117@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Following the removal of the clk_regmap clock table from the s4-peripherals
clock controller driver, it appears some clocks are unused, which means
these are not exported or even registered.
In all likelihood, these clocks have not been tested. Remove the unused
clocks for now. These can added back later when they have been properly
tested.
Reviewed-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20250623-amlogic-clk-drop-clk-regmap-tables-v4-3-ff04918211cc@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Remove the clk_regmap tables that are used to keep track which clock
need to be initialised before being registered. The initialisation is now
done by the .init() operation of clk_regmap.
This rework saves a bit memory and makes maintenance a bit easier.
Link: https://lore.kernel.org/r/20250623-amlogic-clk-drop-clk-regmap-tables-v4-2-ff04918211cc@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Add clk_regmap_init() and use it with all clock types which derive from
clk_regmap. This helps initialise clk_regmap clocks without requiring
tables to keep track of the clock using this type.
The way it is done couples clk_regmap with the controllers, which is not
ideal. This is a temporary solution to get rid of the tables. The situation
will eventually be improved.
Link: https://lore.kernel.org/r/20250623-amlogic-clk-drop-clk-regmap-tables-v4-1-ff04918211cc@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Some Amlogic clock controller drivers have a dedicated headers file, some
do not. Over time, these headers have evolved and now only carry register
offset definitions. These offsets are only used by the related controller
and are not meant to be shared.
These headers are not serving any purpose now.
Start enforcing some consistency between the different Amlogic clock
drivers and move the register offset definitions to the related driver.
Link: https://lore.kernel.org/r/20250623-clk-meson-no-headers-v1-1-468161a7279e@baylibre.com
[jbrunet: checkpatch strict: removed extra blank line]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Enabling the compile test should not cause automatic enabling of all
drivers.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20250404-kconfig-defaults-clk-v1-1-4d2df5603332@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
SPICC is missing fclk_div2, which means fclk_div5 and fclk_div7 indexes
are wrong on this clock. This causes the spicc module to output sclk at
2.5x the expected rate when clock index 3 is picked.
Adding the missing fclk_div2 resolves this.
[jbrunet: amended commit description]
Fixes: a18c8e0b76 ("clk: meson: g12a: add support for the SPICC SCLK Source clocks")
Cc: stable@vger.kernel.org # 6.1
Signed-off-by: Da Xue <da@libre.computer>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20250512142617.2175291-1-da@libre.computer
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Fix a typo in MODULE_DESCRIPTION for a1 PLL driver, S4 should be A1.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Reviewed-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241231062552.2982266-1-jian.hu@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
The 32k clock reference a parent 'cts_slow_oscin' with a fixme note saying
that this clock should be provided by AO controller.
The HW probably has this clock but it does not exist at the moment in
any controller implementation. Furthermore, referencing clock by the global
name should be avoided whenever possible.
There is no reason to keep this hack around, at least for now.
Fixes: 14c735c8e3 ("clk: meson-gxbb: Add EE 32K Clock for CEC")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241220-amlogic-clk-gxbb-32k-fixes-v1-2-baca56ecf2db@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
gxbb_32k_clk_div sets CLK_DIVIDER_ROUND_CLOSEST in the init_data flag which
is incorrect. This is field is not where the divider flags belong.
Thankfully, CLK_DIVIDER_ROUND_CLOSEST maps to bit 4 which is an unused
clock flag, so there is no unintended consequence to this error.
Effectively, the clock has been used without CLK_DIVIDER_ROUND_CLOSEST
so far, so just drop it.
Fixes: 14c735c8e3 ("clk: meson-gxbb: Add EE 32K Clock for CEC")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241220-amlogic-clk-gxbb-32k-fixes-v1-1-baca56ecf2db@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Several clocks used by both g12a and g12b use the g12a cpu A clock hw
pointer as clock parent. This is incorrect on g12b since the parents of
cluster A cpu clock are different. Also the hw clock provided as parent to
these children is not even registered clock on g12b.
Fix the problem by reverting to the global namespace and let CCF pick
the appropriate, as it is already done for other clocks, such as
cpu_clk_trace_div.
Fixes: 25e682a02d ("clk: meson: g12a: migrate to the new parent description method")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241213-amlogic-clk-g12a-cpua-parent-fix-v1-1-d8c0f41865fe@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
The bit index of the peripheral clock for mmc A is wrong
This was probably not a problem for mmc A as the peripheral is likely left
enabled by the bootloader.
No issues has been reported so far but it could be a problem, most likely
some form of conflict between the ethernet and mmc A clock, breaking
ethernet on init.
Use the value provided by the documentation for mmc A before this
becomes an actual problem.
Fixes: 085a4ea93d ("clk: meson: g12a: add peripheral clock controller")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241213-amlogic-clk-g12a-mmca-fix-v1-1-5af421f58b64@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
- Revert the attempt to make CLK_GET_RATE_NOCACHE flag work in
clk_set_rate() because it led to problems with the Qualcomm CPUFreq
driver
- Revert Amlogic reset driver back to the initial implementation. This
broke probe of the audio subsystem on axg based platforms and also
had compilation problems. We'll try again next time.
- Fix a clk frequency and fix array bounds runtime checks in the Airoha
EN7581 driver
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"Two reverts and two EN7581 driver fixes:
- Revert the attempt to make CLK_GET_RATE_NOCACHE flag work in
clk_set_rate() because it led to problems with the Qualcomm CPUFreq
driver
- Revert Amlogic reset driver back to the initial implementation.
This broke probe of the audio subsystem on axg based platforms and
also had compilation problems. We'll try again next time.
- Fix a clk frequency and fix array bounds runtime checks in the
Airoha EN7581 driver"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: en7523: Initialize num before accessing hws in en7523_register_clocks()
clk: en7523: Fix wrong BUS clock for EN7581
clk: amlogic: axg-audio: revert reset implementation
Revert "clk: Fix invalid execution of clk_set_rate"
The audio subsystem of axg based platform is not probing anymore.
This is due to the introduction of RESET_MESON_AUX and the config
not being enabled with the default arm64 defconfig.
This brought another discussion around proper decoupling between
the clock and reset part. While this discussion gets sorted out,
revert back to the initial implementation.
This reverts
* commit 681ed497d6 ("clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX")
* commit 664988eb47 ("clk: amlogic: axg-audio: use the auxiliary reset driver")
Both are reverted with single change to avoid creating more compilation
problems.
Fixes: 681ed497d6 ("clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX")
Cc: Arnd Bergmann <arnd@arndb.de>
Reported-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20241128-clk-audio-fix-rst-missing-v2-1-cf437d1a73da@baylibre.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
As in most cases, using 'imply' is wrong here and does not prevent
build failures since that code may not be visible to a built-in
clk driver:
axg-audio.c:(.text+0x15c): undefined reference to `devm_meson_rst_aux_register'
Replace the incorrt 'imply' with the necessary 'depends on'.
Fixes: 664988eb47 ("clk: amlogic: axg-audio: use the auxiliary reset driver")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20241111102932.3209861-1-arnd@kernel.org
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Remove the implementation of the reset driver in axg audio
clock driver and migrate to the one provided by the reset framework
on the auxiliary bus
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241008-meson-clk-rst-aux-v2-1-682ab9151f4f@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
The spinlock in meson8b clock controller is now only protecting a call to
regmap_update_bits().
The regmap API already has its own locking system so this spinlock
is redundant. Remove it.
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20240925-clk-meson8b-spinlock-v1-1-50b7f2d02d7d@baylibre.com
[jbrunet: amended to remove unused variable as reported by lkp]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
The register corresponding to MPLL does not share the same register
with other module drivers, so there is no concurrent access to the
register with other modules drivers. The spinlock defined in struct
meson_clk_mpll_data is no longer useful.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20240925-mpll_spinlock-v2-1-8f9b73588ec1@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
The fractional denominator of C3's hifi_pll fractional multiplier is
fixed to 100000.
Fixes: 8a9a129dc5 ("clk: meson: c3: add support for the C3 SoC PLL clock")
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20240909-fix_clk-v3-2-a6d8f6333c04@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Some PLLS with fractional multipliers have fractional denominators with
fixed values, instead of the previous "(1 << pll-> frc.width)".
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20240909-fix_clk-v3-1-a6d8f6333c04@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
The s4's hifi_pll supports a fractional frequency multiplier, but frac
parameters are not configured in the driver.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20240906-fix_clk-v1-3-2977ef0d72e7@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Symbols exported by the Amlogic clock modules are only meant to be used by
Amlogic clock controller drivers. Using a dedicated symbols namespace make
that clear and help clean the global namespace of symbols other modules do
no need.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240719094228.3985595-1-jbrunet@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
