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clk: amlogic: drop meson-clkcee

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What is being done by the Amlogic clock controller registration helper for
EE controllers could benefit other controllers. As such, having a specific
module for this makes little sense.

Move the helper function to clkc-utils and rename it to describe what it
does, registering syscon based controller, instead of what it serves.

Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-1-0f402f01e117@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Jerome Brunet 2025-08-25 16:26:26 +02:00
parent 4c4e17f270
commit e256a6602a
9 changed files with 85 additions and 115 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/clk/meson/Kconfig
View File

@ -36,6 +36,8 @@ config COMMON_CLK_MESON_VCLK
select COMMON_CLK_MESON_REGMAP
config COMMON_CLK_MESON_CLKC_UTILS
select REGMAP
select MFD_SYSCON
tristate
config COMMON_CLK_MESON_AO_CLKC
@ -44,11 +46,6 @@ config COMMON_CLK_MESON_AO_CLKC
select COMMON_CLK_MESON_CLKC_UTILS
select RESET_CONTROLLER
config COMMON_CLK_MESON_EE_CLKC
tristate
select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_CLKC_UTILS
config COMMON_CLK_MESON_CPU_DYNDIV
tristate
select COMMON_CLK_MESON_REGMAP
@ -73,12 +70,12 @@ config COMMON_CLK_GXBB
depends on ARM64
default ARCH_MESON
select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_CLKC_UTILS
select COMMON_CLK_MESON_DUALDIV
select COMMON_CLK_MESON_VID_PLL_DIV
select COMMON_CLK_MESON_MPLL
select COMMON_CLK_MESON_PLL
select COMMON_CLK_MESON_AO_CLKC
select COMMON_CLK_MESON_EE_CLKC
select MFD_SYSCON
help
Support for the clock controller on AmLogic S905 devices, aka gxbb.
@ -89,11 +86,11 @@ config COMMON_CLK_AXG
depends on ARM64
default ARCH_MESON
select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_CLKC_UTILS
select COMMON_CLK_MESON_DUALDIV
select COMMON_CLK_MESON_MPLL
select COMMON_CLK_MESON_PLL
select COMMON_CLK_MESON_AO_CLKC
select COMMON_CLK_MESON_EE_CLKC
select MFD_SYSCON
help
Support for the clock controller on AmLogic A113D devices, aka axg.
@ -167,11 +164,11 @@ config COMMON_CLK_G12A
depends on ARM64
default ARCH_MESON
select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_CLKC_UTILS
select COMMON_CLK_MESON_DUALDIV
select COMMON_CLK_MESON_MPLL
select COMMON_CLK_MESON_PLL
select COMMON_CLK_MESON_AO_CLKC
select COMMON_CLK_MESON_EE_CLKC
select COMMON_CLK_MESON_CPU_DYNDIV
select COMMON_CLK_MESON_VID_PLL_DIV
select COMMON_CLK_MESON_VCLK

1
drivers/clk/meson/Makefile
View File

@ -5,7 +5,6 @@ obj-$(CONFIG_COMMON_CLK_MESON_CLKC_UTILS) += meson-clkc-utils.o
obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o
obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o
obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o
obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o

6
drivers/clk/meson/axg.c
View File

@ -18,7 +18,7 @@
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-mpll.h"
#include "meson-eeclk.h"
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/axg-clkc.h>
@ -2110,7 +2110,7 @@ static struct clk_hw *axg_hw_clks[] = {
[CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
};
static const struct meson_eeclkc_data axg_clkc_data = {
static const struct meson_clkc_data axg_clkc_data = {
.hw_clks = {
.hws = axg_hw_clks,
.num = ARRAY_SIZE(axg_hw_clks),
@ -2124,7 +2124,7 @@ static const struct of_device_id axg_clkc_match_table[] = {
MODULE_DEVICE_TABLE(of, axg_clkc_match_table);
static struct platform_driver axg_clkc_driver = {
.probe = meson_eeclkc_probe,
.probe = meson_clkc_syscon_probe,
.driver = {
.name = "axg-clkc",
.of_match_table = axg_clkc_match_table,

28
drivers/clk/meson/g12a.c
View File

@ -23,7 +23,7 @@
#include "clk-cpu-dyndiv.h"
#include "vid-pll-div.h"
#include "vclk.h"
#include "meson-eeclk.h"
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/g12a-clkc.h>
@ -5360,26 +5360,26 @@ static int g12a_dvfs_setup(struct platform_device *pdev)
}
struct g12a_clkc_data {
const struct meson_eeclkc_data eeclkc_data;
const struct meson_clkc_data clkc_data;
int (*dvfs_setup)(struct platform_device *pdev);
};
static int g12a_clkc_probe(struct platform_device *pdev)
{
const struct meson_eeclkc_data *eeclkc_data;
const struct meson_clkc_data *clkc_data;
const struct g12a_clkc_data *g12a_data;
int ret;
eeclkc_data = of_device_get_match_data(&pdev->dev);
if (!eeclkc_data)
clkc_data = of_device_get_match_data(&pdev->dev);
if (!clkc_data)
return -EINVAL;
ret = meson_eeclkc_probe(pdev);
ret = meson_clkc_syscon_probe(pdev);
if (ret)
return ret;
g12a_data = container_of(eeclkc_data, struct g12a_clkc_data,
eeclkc_data);
g12a_data = container_of(clkc_data, struct g12a_clkc_data,
clkc_data);
if (g12a_data->dvfs_setup)
return g12a_data->dvfs_setup(pdev);
@ -5388,7 +5388,7 @@ static int g12a_clkc_probe(struct platform_device *pdev)
}
static const struct g12a_clkc_data g12a_clkc_data = {
.eeclkc_data = {
.clkc_data = {
.hw_clks = {
.hws = g12a_hw_clks,
.num = ARRAY_SIZE(g12a_hw_clks),
@ -5400,7 +5400,7 @@ static const struct g12a_clkc_data g12a_clkc_data = {
};
static const struct g12a_clkc_data g12b_clkc_data = {
.eeclkc_data = {
.clkc_data = {
.hw_clks = {
.hws = g12b_hw_clks,
.num = ARRAY_SIZE(g12b_hw_clks),
@ -5410,7 +5410,7 @@ static const struct g12a_clkc_data g12b_clkc_data = {
};
static const struct g12a_clkc_data sm1_clkc_data = {
.eeclkc_data = {
.clkc_data = {
.hw_clks = {
.hws = sm1_hw_clks,
.num = ARRAY_SIZE(sm1_hw_clks),
@ -5422,15 +5422,15 @@ static const struct g12a_clkc_data sm1_clkc_data = {
static const struct of_device_id g12a_clkc_match_table[] = {
{
.compatible = "amlogic,g12a-clkc",
.data = &g12a_clkc_data.eeclkc_data
.data = &g12a_clkc_data.clkc_data
},
{
.compatible = "amlogic,g12b-clkc",
.data = &g12b_clkc_data.eeclkc_data
.data = &g12b_clkc_data.clkc_data
},
{
.compatible = "amlogic,sm1-clkc",
.data = &sm1_clkc_data.eeclkc_data
.data = &sm1_clkc_data.clkc_data
},
{}
};

8
drivers/clk/meson/gxbb.c
View File

@ -13,7 +13,7 @@
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-mpll.h"
#include "meson-eeclk.h"
#include "meson-clkc-utils.h"
#include "vid-pll-div.h"
#include <dt-bindings/clock/gxbb-clkc.h>
@ -3234,14 +3234,14 @@ static struct clk_hw *gxl_hw_clks[] = {
[CLKID_ACODEC] = &gxl_acodec.hw,
};
static const struct meson_eeclkc_data gxbb_clkc_data = {
static const struct meson_clkc_data gxbb_clkc_data = {
.hw_clks = {
.hws = gxbb_hw_clks,
.num = ARRAY_SIZE(gxbb_hw_clks),
},
};
static const struct meson_eeclkc_data gxl_clkc_data = {
static const struct meson_clkc_data gxl_clkc_data = {
.hw_clks = {
.hws = gxl_hw_clks,
.num = ARRAY_SIZE(gxl_hw_clks),
@ -3256,7 +3256,7 @@ static const struct of_device_id gxbb_clkc_match_table[] = {
MODULE_DEVICE_TABLE(of, gxbb_clkc_match_table);
static struct platform_driver gxbb_clkc_driver = {
.probe = meson_eeclkc_probe,
.probe = meson_clkc_syscon_probe,
.driver = {
.name = "gxbb-clkc",
.of_match_table = gxbb_clkc_match_table,

50
drivers/clk/meson/meson-clkc-utils.c
View File

@ -3,9 +3,13 @@
* Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
*/
#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "meson-clkc-utils.h"
struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data)
@ -22,6 +26,50 @@ struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_da
}
EXPORT_SYMBOL_NS_GPL(meson_clk_hw_get, "CLK_MESON");
int meson_clkc_syscon_probe(struct platform_device *pdev)
{
const struct meson_clkc_data *data;
struct device *dev = &pdev->dev;
struct device_node *np;
struct regmap *map;
struct clk_hw *hw;
int ret, i;
data = of_device_get_match_data(dev);
if (!data)
return -EINVAL;
np = of_get_parent(dev->of_node);
map = syscon_node_to_regmap(np);
of_node_put(np);
if (IS_ERR(map)) {
dev_err(dev,
"failed to get parent syscon regmap\n");
return PTR_ERR(map);
}
if (data->init_count)
regmap_multi_reg_write(map, data->init_regs, data->init_count);
for (i = 0; i < data->hw_clks.num; i++) {
hw = data->hw_clks.hws[i];
/* array might be sparse */
if (!hw)
continue;
ret = devm_clk_hw_register(dev, hw);
if (ret) {
dev_err(dev, "registering %s clock failed\n",
hw->init->name);
return ret;
}
}
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
}
EXPORT_SYMBOL_NS_GPL(meson_clkc_syscon_probe, "CLK_MESON");
MODULE_DESCRIPTION("Amlogic Clock Controller Utilities");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS("CLK_MESON");

10
drivers/clk/meson/meson-clkc-utils.h
View File

@ -9,6 +9,8 @@
#include <linux/of_device.h>
#include <linux/clk-provider.h>
struct platform_device;
struct meson_clk_hw_data {
struct clk_hw **hws;
unsigned int num;
@ -16,4 +18,12 @@ struct meson_clk_hw_data {
struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data);
struct meson_clkc_data {
const struct reg_sequence *init_regs;
unsigned int init_count;
struct meson_clk_hw_data hw_clks;
};
int meson_clkc_syscon_probe(struct platform_device *pdev);
#endif

60
drivers/clk/meson/meson-eeclk.c
View File

@ -1,60 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 BayLibre, SAS.
* Author: Jerome Brunet <jbrunet@baylibre.com>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/module.h>
#include "clk-regmap.h"
#include "meson-eeclk.h"
int meson_eeclkc_probe(struct platform_device *pdev)
{
const struct meson_eeclkc_data *data;
struct device *dev = &pdev->dev;
struct device_node *np;
struct regmap *map;
int ret, i;
data = of_device_get_match_data(dev);
if (!data)
return -EINVAL;
/* Get the hhi system controller node */
np = of_get_parent(dev->of_node);
map = syscon_node_to_regmap(np);
of_node_put(np);
if (IS_ERR(map)) {
dev_err(dev,
"failed to get HHI regmap\n");
return PTR_ERR(map);
}
if (data->init_count)
regmap_multi_reg_write(map, data->init_regs, data->init_count);
for (i = 0; i < data->hw_clks.num; i++) {
/* array might be sparse */
if (!data->hw_clks.hws[i])
continue;
ret = devm_clk_hw_register(dev, data->hw_clks.hws[i]);
if (ret) {
dev_err(dev, "Clock registration failed\n");
return ret;
}
}
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
}
EXPORT_SYMBOL_NS_GPL(meson_eeclkc_probe, "CLK_MESON");
MODULE_DESCRIPTION("Amlogic Main Clock Controller Helpers");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS("CLK_MESON");

24
drivers/clk/meson/meson-eeclk.h
View File

@ -1,24 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 BayLibre, SAS.
* Author: Jerome Brunet <jbrunet@baylibre.com>
*/
#ifndef __MESON_CLKC_H
#define __MESON_CLKC_H
#include <linux/clk-provider.h>
#include "clk-regmap.h"
#include "meson-clkc-utils.h"
struct platform_device;
struct meson_eeclkc_data {
const struct reg_sequence *init_regs;
unsigned int init_count;
struct meson_clk_hw_data hw_clks;
};
int meson_eeclkc_probe(struct platform_device *pdev);
#endif /* __MESON_CLKC_H */