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clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs

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GXBB has the HDMI PLL OD in the HHI_HDMI_PLL_CNTL2 register while for
GXL/GXM the OD has moved to HHI_HDMI_PLL_CNTL3. At first glance the rest
of the OD setup seems identical.

However, looking at the downstream kernel sources as well as testing
shows that GXL only supports three OD values:
- register value 0 means: divide by 1
- register value 1 means: divide by 2
- register value 2 means: divide by 4

Using register value 3 (which on GXBB means: divide by 8) still divides
by 4 as verified using meson-clk-measure. Downstream sources are also
only using OD register values 0, 1 and 2 for GXL (while for GXBB the
downstream kernel sources are also using value 3).

Add clk_div_table and have it replace the CLK_DIVIDER_POWER_OF_TWO flag
to make the kernel's view of this register match with how the hardware
actually works.

Fixes: 69d9229327 ("clk: meson: add the gxl hdmi pll")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20260105204710.447779-2-martin.blumenstingl@googlemail.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Martin Blumenstingl 2026-01-05 21:47:08 +01:00 committed by Jerome Brunet
parent 4aca7e9202
commit 5b1a43950f
1 changed files with 14 additions and 3 deletions
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17
drivers/clk/meson/gxbb.c
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@ -349,12 +349,23 @@ static struct clk_regmap gxbb_hdmi_pll = {
},
};
/*
* GXL hdmi OD dividers are POWER_OF_TWO dividers but limited to /4.
* A divider value of 3 should map to /8 but instead map /4 so ignore it.
*/
static const struct clk_div_table gxl_hdmi_pll_od_div_table[] = {
{ .val = 0, .div = 1 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 4 },
{ /* sentinel */ }
};
static struct clk_regmap gxl_hdmi_pll_od = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_HDMI_PLL_CNTL + 8,
.shift = 21,
.width = 2,
.flags = CLK_DIVIDER_POWER_OF_TWO,
.table = gxl_hdmi_pll_od_div_table,
},
.hw.init = &(struct clk_init_data){
.name = "hdmi_pll_od",
@ -372,7 +383,7 @@ static struct clk_regmap gxl_hdmi_pll_od2 = {
.offset = HHI_HDMI_PLL_CNTL + 8,
.shift = 23,
.width = 2,
.flags = CLK_DIVIDER_POWER_OF_TWO,
.table = gxl_hdmi_pll_od_div_table,
},
.hw.init = &(struct clk_init_data){
.name = "hdmi_pll_od2",
@ -390,7 +401,7 @@ static struct clk_regmap gxl_hdmi_pll = {
.offset = HHI_HDMI_PLL_CNTL + 8,
.shift = 19,
.width = 2,
.flags = CLK_DIVIDER_POWER_OF_TWO,
.table = gxl_hdmi_pll_od_div_table,
},
.hw.init = &(struct clk_init_data){
.name = "hdmi_pll",