Commit Graph

22 Commits

Author SHA1 Message Date
Tomer Maimon
60b9d5b8ca arm64: dts: nuvoton: npcm845: Reorder timer0 and PECI nodes
Move the timer0 and PECI nodes so the APB children are ordered by
ascending unit address.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://patch.msgid.link/20260708165929.2233934-3-tmaimon77@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-07-22 20:27:35 +09:30
Tomer Maimon
050253f365 arm64: dts: nuvoton: npcm845: Drop redundant timer clock-names
The NPCM845 timer0 node references a single clock, but its
clock-names property is not described by the timer binding. Drop the
undocumented name so the DTS matches the binding.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://patch.msgid.link/20260708165929.2233934-2-tmaimon77@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-07-22 20:27:35 +09:30
Joey Lu
eae82b6e8c arm64: dts: nuvoton: Add Ethernet nodes
Add GMAC nodes for our MA35D1 development boards:
two RGMII interfaces for SOM board, and one RGMII
and one RMII interface for IoT board.

Signed-off-by: Joey Lu <a0987203069@gmail.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-05-18 23:18:01 +09:30
Tomer Maimon
6ee3f20368 arm64: dts: nuvoton: drop unused syscon property from watchdog node
The NPCM8XX DTSI currently includes a 'syscon' phandle in the watchdog
node, but this property is not used by any upstream driver and is not
documented in the NPCM watchdog binding. Since it was never reviewed and
does not form part of the DT ABI, remove it.

[arj: Drop 'safely' language in line with Krzysztof's commentary]

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260218184800.2261674-1-tmaimon77@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-02-23 09:43:36 +10:30
Arnd Bergmann
6b82510294 Minor improvements in ARM64 DTS for v6.20
Several minor cleanups for Nuvoton, LG, Spreadtrum, Toshiba, Cavium, ARM
 and APM SoCs:
 
 1. Switch to recommended node names by fixing style
    (s/lowercase/hyphen/), using generic naming and adhering to DT
    bindings.
 
 2. Use consistent whitespaces around.
 
 3. Add missing properties like UART clocks (Cavium Thunder 88xx) or
    "reg" (APM).
 
 4. Drop incorrect or long time deprecated propeties.
 
 5. Correct clock cells to 0 for fixed-factor-clock clocks.
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Merge tag 'dt64-cleanup-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt

Minor improvements in ARM64 DTS for v6.20

Several minor cleanups for Nuvoton, LG, Spreadtrum, Toshiba, Cavium, ARM
and APM SoCs:

1. Switch to recommended node names by fixing style
   (s/lowercase/hyphen/), using generic naming and adhering to DT
   bindings.

2. Use consistent whitespaces around.

3. Add missing properties like UART clocks (Cavium Thunder 88xx) or
   "reg" (APM).

4. Drop incorrect or long time deprecated propeties.

5. Correct clock cells to 0 for fixed-factor-clock clocks.

* tag 'dt64-cleanup-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt:
  arm64: dts: apm: Drop "dma" device_type
  arm64: dts: apm: Add "reg" to "syscon-reboot" and "syscon-poweroff"
  arm64: dts: apm: Use recommended i2c node names
  arm64: dts: apm/shadowcat: More clock clean-ups
  ARM: dts: vexpress/v2m-rs1: Use documented arm,vexpress,config-bus child node names
  arm64: dts: cavium: Drop thunder2
  arm64: dts: cavium: thunder-88xx: Add missing PL011 "uartclk"
  arm64: dts: toshiba: Use recommended node names
  arm64: dts: sprd: Use recommended node names
  arm64: dts: lg: Use recommended simple-bus node name
  arm64: dts: nuvoton: npcm845: Minor whitespace cleanup
  arm64: dts: toshiba: tmpv7708: Align node names with DT bindings

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-26 15:40:34 +01:00
Rob Herring (Arm)
c6a40c8674 arm64: dts: nuvoton: Add missing "device_type" property on memory node
"device_type" is required for memory nodes, but is missing on Nuvoton
npcm845-evb.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2026-01-08 17:52:13 +10:30
Krzysztof Kozlowski
1b06942cda arm64: dts: nuvoton: npcm845: Minor whitespace cleanup
The DTS code coding style expects exactly one space around '='
character.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20250819131725.86770-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2025-12-17 10:06:51 +01:00
Tomer Maimon
13587befb3 arm64: dts: nuvoton: add refclk and update peripheral clocks for NPCM845
Add a 25 MHz fixed-clock node (refclk) in the NPCM845-EVB board device
tree to represent the external reference clock used by the NPCM845 reset
and clock controller.

Update peripherals (timer0, watchdog0-2) in the NPCM845 device tree to
reference this refclk directly instead of the previous clock controller
output (NPCM8XX_CLK_REFCLK).

Depends-on: arm64: dts: nuvoton: Combine NPCM845 reset and clk nodes

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://patch.msgid.link/20250706134207.2168184-3-tmaimon77@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-08-11 09:38:08 +09:30
Tomer Maimon
2e6028f8fa arm64: dts: nuvoton: combine NPCM845 reset and clk nodes
Combine the NPCM845 reset and clock controller nodes into a single node
with compatible "nuvoton,npcm845-reset" in nuvoton-common-npcm8xx.dtsi,
using the auxiliary device framework to provide clock functionality.

Update the register range to 0xC4 to cover the shared reset and clock
registers at 0xf0801000.

Remove the separate nuvoton,npcm845-clk node, as the reset driver now
handles clocks via an auxiliary device.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://patch.msgid.link/20250706134207.2168184-2-tmaimon77@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-08-11 09:38:08 +09:30
Tomer Maimon
91f8329e67 arm64: dts: nuvoton: npcm845: Add pinctrl groups
Add 64 missing pinctrl groups to the NPCM845 device tree source file to
support additional pinmux configurations defined in the npcm845-pinctrl
driver.

This enhances the pinmux configuration for the NPCM845 SoC, enabling
further hardware pin functionalities.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://patch.msgid.link/20250706153551.2180052-1-tmaimon77@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-08-11 09:38:08 +09:30
Rob Herring (Arm)
8e7e63fc47
arm64: dts: nuvoton: npcm8xx: Drop the GIC "ppi-partitions" node
The Arm GIC "ppi-partitions" node is only relevant to GICv3 and makes no
sense for GICv2 implementations which the GIC-400 is. PPIs in GICv2 have
no CPU affinity.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250609203721.2852879-1-robh@kernel.org
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Link: https://lore.kernel.org/r/20250710-nuvoton-arm64-dt-v1-1-ec7db96ea507@codeconstruct.com.au
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-21 17:02:57 +02:00
William A. Kennington III
7e1a0dfb3f
arm64: dts: nuvoton: Add pinctrl
This is critical to support multifunction pins shared between devices as
well as generic GPIOs.

Signed-off-by: William A. Kennington III <william@wkennington.com>
Link: https://patch.msgid.link/20250416015902.2091251-1-william@wkennington.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Link: https://lore.kernel.org/r/20250515-nuvoton-arm64-dt-v1-1-25769b8c1509@codeconstruct.com.au
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-21 23:10:24 +02:00
Jacky Huang
82d7cf5655
arm64: dts: nuvoton: ma35d1: Add uart pinctrl settings
Enable all UART nodes presented on som and iot boards, and add pinctrl
function settings to these nodes.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Link: https://lore.kernel.org/r/20240819035647.306-4-ychuang570808@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-09-05 15:27:21 +00:00
Jacky Huang
0dfa542df9
arm64: dts: nuvoton: ma35d1: Add pinctrl and gpio nodes
Added the pinctrl node and its subnodes, the gpioa through gpion
nodes, to the MA35D1 device tree.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Link: https://lore.kernel.org/r/20240819035647.306-3-ychuang570808@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-09-05 15:27:21 +00:00
Jacky Huang
a957af0896
arm64: dts: nuvoton: Add syscon to the system-management node
According to the binding document, add the "syscon" compatible to the
system-management node.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Link: https://lore.kernel.org/r/20240819035647.306-2-ychuang570808@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-09-05 15:26:59 +00:00
Rob Herring
5c04a5b065 arm64: dts: Add/fix /memory node unit-addresses
'/memory' nodes always have a 'reg' property, and therefore should have
a unit-address with just plain hex (i.e. no commas). Fix all the arm64
'/memory' nodes.

It's possible that some bootloader depends on /memory (arm32 ATAG to DT
code does for example). If so, the memory node should be commented with
that requirement.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Chanho Min <chanho.min@lge.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240430191856.874600-2-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-05-02 14:56:02 +02:00
Linus Torvalds
1c9f8dff62 Char/Misc driver changes for 6.6-rc1
Here is the big set of char/misc and other small driver subsystem
 changes for 6.6-rc1.
 
 Stuff all over the place here, lots of driver updates and changes and
 new additions.  Short summary is:
   - new IIO drivers and updates
   - Interconnect driver updates
   - fpga driver updates and additions
   - fsi driver updates
   - mei driver updates
   - coresight driver updates
   - nvmem driver updates
   - counter driver updates
   - lots of smaller misc and char driver updates and additions
 
 All of these have been in linux-next for a long time with no reported
 problems.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'char-misc-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc driver updates from Greg KH:
 "Here is the big set of char/misc and other small driver subsystem
  changes for 6.6-rc1.

  Stuff all over the place here, lots of driver updates and changes and
  new additions. Short summary is:

   - new IIO drivers and updates

   - Interconnect driver updates

   - fpga driver updates and additions

   - fsi driver updates

   - mei driver updates

   - coresight driver updates

   - nvmem driver updates

   - counter driver updates

   - lots of smaller misc and char driver updates and additions

  All of these have been in linux-next for a long time with no reported
  problems"

* tag 'char-misc-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (267 commits)
  nvmem: core: Notify when a new layout is registered
  nvmem: core: Do not open-code existing functions
  nvmem: core: Return NULL when no nvmem layout is found
  nvmem: core: Create all cells before adding the nvmem device
  nvmem: u-boot-env:: Replace zero-length array with DECLARE_FLEX_ARRAY() helper
  nvmem: sec-qfprom: Add Qualcomm secure QFPROM support
  dt-bindings: nvmem: sec-qfprom: Add bindings for secure qfprom
  dt-bindings: nvmem: Add compatible for QCM2290
  nvmem: Kconfig: Fix typo "drive" -> "driver"
  nvmem: Explicitly include correct DT includes
  nvmem: add new NXP QorIQ eFuse driver
  dt-bindings: nvmem: Add t1023-sfp efuse support
  dt-bindings: nvmem: qfprom: Add compatible for MSM8226
  nvmem: uniphier: Use devm_platform_get_and_ioremap_resource()
  nvmem: qfprom: do some cleanup
  nvmem: stm32-romem: Use devm_platform_get_and_ioremap_resource()
  nvmem: rockchip-efuse: Use devm_platform_get_and_ioremap_resource()
  nvmem: meson-mx-efuse: Convert to devm_platform_ioremap_resource()
  nvmem: lpc18xx_otp: Convert to devm_platform_ioremap_resource()
  nvmem: brcm_nvram: Use devm_platform_get_and_ioremap_resource()
  ...
2023-09-01 09:53:54 -07:00
Iwona Winiarska
d7c99890fe arm64: dts: nuvoton: Add PECI controller node
Add PECI controller node with all required information.

Reviewed-by: Tomer Maimon <tmaimon77@gmail.com>
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
Link: https://lore.kernel.org/r/20230727202126.1477515-5-iwona.winiarska@intel.com
2023-08-07 18:27:55 +02:00
Krzysztof Kozlowski
a8cf500c42 arm64: dts: nuvoton: add missing cache properties
As all level 2 and level 3 caches are unified, add required
cache-unified and cache-level properties to fix warnings like:

  nuvoton-npcm845-evb.dtb: l2-cache: 'cache-level' is a required property
  nuvoton-npcm845-evb.dtb: l2-cache: 'cache-unified' is a required property

Reviewed-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://lore.kernel.org/r/20230421223154.115312-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-07-13 08:43:54 +02:00
Jacky Huang
b69af09847 arm64: dts: nuvoton: Add initial ma35d1 device tree
Add initial device tree support for Nuvoton ma35d1 SoC, including
cpu, clock, reset, and serial controllers.
Add reference boards som-256m and iot-512m.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-05 13:18:08 +02:00
Tomer Maimon
f21d8e7165 arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
Add initial Nuvoton NPCM845 evaluation board device tree.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-19 15:41:04 +02:00
Tomer Maimon
6cc82f07fc arm64: dts: nuvoton: Add initial NPCM8XX device tree
This adds initial device tree support for the Nuvoton NPCM845 Board
Management controller (BMC) SoC family.

The NPCM845 based quad-core Cortex-A35 ARMv8 architecture and have
various peripheral IPs.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-19 15:41:04 +02:00