github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-06-04 12:35:52 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

arm64: dts: nuvoton: add refclk and update peripheral clocks for NPCM845

Browse Source 
Add a 25 MHz fixed-clock node (refclk) in the NPCM845-EVB board device
tree to represent the external reference clock used by the NPCM845 reset
and clock controller.

Update peripherals (timer0, watchdog0-2) in the NPCM845 device tree to
reference this refclk directly instead of the previous clock controller
output (NPCM8XX_CLK_REFCLK).

Depends-on: arm64: dts: nuvoton: Combine NPCM845 reset and clk nodes

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://patch.msgid.link/20250706134207.2168184-3-tmaimon77@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
This commit is contained in:
Tomer Maimon 2025-07-06 16:42:07 +03:00 committed by Andrew Jeffery
parent 2e6028f8fa
commit 13587befb3
2 changed files with 11 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
View File

@ -47,6 +47,7 @@ clk: rstc: reset-controller@f0801000 {
reg = <0x0 0xf0801000 0x0 0xC4>;
nuvoton,sysgcr = <&gcr>;
#reset-cells = <2>;
clocks = <&refclk>;
#clock-cells = <1>;
};
@ -71,7 +72,7 @@ timer0: timer@8000 {
compatible = "nuvoton,npcm845-timer";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x8000 0x1C>;
clocks = <&clk NPCM8XX_CLK_REFCLK>;
clocks = <&refclk>;
clock-names = "refclk";
};
@ -143,7 +144,7 @@ watchdog0: watchdog@801c {
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x801c 0x4>;
status = "disabled";
clocks = <&clk NPCM8XX_CLK_REFCLK>;
clocks = <&refclk>;
syscon = <&gcr>;
};
@ -152,7 +153,7 @@ watchdog1: watchdog@901c {
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x901c 0x4>;
status = "disabled";
clocks = <&clk NPCM8XX_CLK_REFCLK>;
clocks = <&refclk>;
syscon = <&gcr>;
};
@ -161,7 +162,7 @@ watchdog2: watchdog@a01c {
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xa01c 0x4>;
status = "disabled";
clocks = <&clk NPCM8XX_CLK_REFCLK>;
clocks = <&refclk>;
syscon = <&gcr>;
};
};

6
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts
View File

@ -19,6 +19,12 @@ chosen {
memory@0 {
reg = <0x0 0x0 0x0 0x40000000>;
};
refclk: refclk-25mhz {
compatible = "fixed-clock";
clock-frequency = <25000000>;
#clock-cells = <0>;
};
};
&serial0 {