From 13587befb34ffa5d605196494c243420e045f28e Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Sun, 6 Jul 2025 16:42:07 +0300 Subject: [PATCH] arm64: dts: nuvoton: add refclk and update peripheral clocks for NPCM845 Add a 25 MHz fixed-clock node (refclk) in the NPCM845-EVB board device tree to represent the external reference clock used by the NPCM845 reset and clock controller. Update peripherals (timer0, watchdog0-2) in the NPCM845 device tree to reference this refclk directly instead of the previous clock controller output (NPCM8XX_CLK_REFCLK). Depends-on: arm64: dts: nuvoton: Combine NPCM845 reset and clk nodes Signed-off-by: Tomer Maimon Link: https://patch.msgid.link/20250706134207.2168184-3-tmaimon77@gmail.com Signed-off-by: Andrew Jeffery --- arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 9 +++++---- arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 6 ++++++ 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index 400d5c5b71ac..24133528b8e9 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -47,6 +47,7 @@ clk: rstc: reset-controller@f0801000 { reg = <0x0 0xf0801000 0x0 0xC4>; nuvoton,sysgcr = <&gcr>; #reset-cells = <2>; + clocks = <&refclk>; #clock-cells = <1>; }; @@ -71,7 +72,7 @@ timer0: timer@8000 { compatible = "nuvoton,npcm845-timer"; interrupts = ; reg = <0x8000 0x1C>; - clocks = <&clk NPCM8XX_CLK_REFCLK>; + clocks = <&refclk>; clock-names = "refclk"; }; @@ -143,7 +144,7 @@ watchdog0: watchdog@801c { interrupts = ; reg = <0x801c 0x4>; status = "disabled"; - clocks = <&clk NPCM8XX_CLK_REFCLK>; + clocks = <&refclk>; syscon = <&gcr>; }; @@ -152,7 +153,7 @@ watchdog1: watchdog@901c { interrupts = ; reg = <0x901c 0x4>; status = "disabled"; - clocks = <&clk NPCM8XX_CLK_REFCLK>; + clocks = <&refclk>; syscon = <&gcr>; }; @@ -161,7 +162,7 @@ watchdog2: watchdog@a01c { interrupts = ; reg = <0xa01c 0x4>; status = "disabled"; - clocks = <&clk NPCM8XX_CLK_REFCLK>; + clocks = <&refclk>; syscon = <&gcr>; }; }; diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts index eeceb5b292a8..2638ee1c3846 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts @@ -19,6 +19,12 @@ chosen { memory@0 { reg = <0x0 0x0 0x0 0x40000000>; }; + + refclk: refclk-25mhz { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + #clock-cells = <0>; + }; }; &serial0 {