github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-12 16:18:45 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity

Pin control changes for the v7.1 kernel cycle:

Browse Source 
Core changes:
 
 - Perform basic checks on pin config properties so as not to
   allow directly contradictory settings such as setting a pin
   to more than one bias or drive mode.
 
 - Handle input-threshold-voltage-microvolt property.
 
 - Introduce pinctrl_gpio_get_config() handling in the core for
   SCMI GPIO using pin control.
 
 New drivers:
 
 - GPIO-by-pin control driver (also apperaing in the GPIO pull
   request) fulfilling a promise on a comment from
   Grant Likely many years ago: "can't GPIO just be a front-end
   for pin control?" it turns out it can, if and only if you
   design something new from scratch, such as SCMI.
 
 - Broadcom BCM7038 as a pinctrl-single delegate.
 
 - Mobileye EyeQ6Lplus OLB pin controller.
 
 - Qualcomm Eliza and Hawi families TLMM pin controllers.
 
 - Qualcomm SDM670 and Milos family LPASS LPI pin controllers.
 
 - Qualcomm IPQ5210 pin controller.
 
 - Realtek RTD1625 pin controller support.
 
 - Rockchip RV1103B pin controller support.
 
 - Texas Instruments AM62L as a pinctrl-single delegate.
 
 Improvements:
 
 - Set config implementation for the Spacemit K1 pin controller.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmnkAuIACgkQQRCzN7AZ
 XXMK2xAAwiHAlVzZ0BqOCEBzC0vtp3pratUKC5la8lF/ndWQrSOfdaY+UtS6vnRE
 ZqkFsEg4lu4beRota0orLYVeo+JcPdqI1iGu/BgsEr3U2wCC6SlP26Ixo2Xp72cO
 r0axhvMH0h/cqbsn9eYhRzUWQtzDEWMRZOI6uPSOvM9YoE7OYLNbb1bMEy9nGk6I
 CtNut9+3pR8f1qvdFnHdAPIO0e8I7+qjZXYnFVGSHBwoXXGTfFMsOpBO8lyfN7Mu
 NJtfDQvuI/Vnj+6ZVi7XaOzqLNRTvLdo5UPtcZC6gVDe7nYcVjIPFqzHDRvGwaNa
 5pqlIMCw+f3h64wl2E9H2cEx3wZfWeQP3HKrq5+NbNbHH1UIm2xsdykR2S5G3khc
 WPq28ob3naFC4AmIrcpZ5nNqX9hHfqQp891NySmL86uozfHy6p6Cu9K5ksq0Oo1v
 LRb7WqJ4pEko61vVvs4kCJF5W/LyNjTcBvZFQTQiDwZn2Ixz0vIheKpUlFIhldmC
 MpxyQ/Ct9YTSU3AZ7lZETVj/VASHnjpvE5JhDm2F89mI9yNYIBO70L1XDfUm3vPh
 /cFyrPCRJPPLyClc6UQRUEtmoMhbgM74f4rfV+JtA9J49o14I+ewVa7DtWtIZ6Pl
 X5DCS9Hl5o4mocaiOoXbCCTIn1cl1EWXSn/f6AVV5tI2hHOnbJc=
 =mkXM
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "Core changes:

   - Perform basic checks on pin config properties so as not to allow
     directly contradictory settings such as setting a pin to more than
     one bias or drive mode

   - Handle input-threshold-voltage-microvolt property

   - Introduce pinctrl_gpio_get_config() handling in the core for SCMI
     GPIO using pin control

  New drivers:

   - GPIO-by-pin control driver (also appearing in the GPIO pull
     request) fulfilling a promise on a comment from Grant Likely many
     years ago: "can't GPIO just be a front-end for pin control?" it
     turns out it can, if and only if you design something new from
     scratch, such as SCMI

   - Broadcom BCM7038 as a pinctrl-single delegate

   - Mobileye EyeQ6Lplus OLB pin controller

   - Qualcomm Eliza and Hawi families TLMM pin controllers

   - Qualcomm SDM670 and Milos family LPASS LPI pin controllers

   - Qualcomm IPQ5210 pin controller

   - Realtek RTD1625 pin controller support

   - Rockchip RV1103B pin controller support

   - Texas Instruments AM62L as a pinctrl-single delegate

  Improvements:

   - Set config implementation for the Spacemit K1 pin controller"

* tag 'pinctrl-v7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (84 commits)
  pinctrl: qcom: Add Hawi pinctrl driver
  dt-bindings: pinctrl: qcom: Describe Hawi TLMM block
  dt-bindings: pinctrl: pinctrl-max77620: convert to DT schema
  pinctrl: single: Add bcm7038-padconf compatible matching
  dt-bindings: pinctrl: pinctrl-single: Add brcm,bcm7038-padconf
  dt-bindings: pinctrl: apple,pinctrl: Add t8122 compatible
  pinctrl: qcom: sdm670-lpass-lpi: label variables as static
  pinctrl: sophgo: pinctrl-sg2044: Fix wrong module description
  pinctrl: sophgo: pinctrl-sg2042: Fix wrong module description
  pinctrl: qcom: add sdm670 lpi tlmm
  dt-bindings: pinctrl: qcom: Add SDM670 LPASS LPI pinctrl
  dt-bindings: qcom: lpass-lpi-common: add reserved GPIOs property
  pinctrl: qcom: Introduce IPQ5210 TLMM driver
  dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl
  pinctrl: qcom: Drop redundant intr_target_reg on modern SoCs
  pinctrl: qcom: eliza: Fix interrupt target bit
  pinctrl: core: Don't use "proxy" headers
  pinctrl: amd: Support new ACPI ID AMDI0033
  pinctrl: renesas: rzg2l: Drop superfluous blank line
  pinctrl: renesas: rzg2l: Fix save/restore of {IOLH,IEN,PUPD,SMT} registers
  ...
This commit is contained in:
Linus Torvalds 2026-04-18 16:59:09 -07:00
commit faeab16616
120 changed files with 9879 additions and 606 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml
View File

@ -18,7 +18,9 @@ properties:
compatible:
oneOf:
- items:
- const: apple,t6020-pinctrl
- enum:
- apple,t6020-pinctrl
- apple,t8122-pinctrl
- const: apple,t8103-pinctrl
- items:
# Do not add additional SoC to this list.

126
Documentation/devicetree/bindings/pinctrl/fsl,imx27-iomuxc.yaml Normal file
View File

@ -0,0 +1,126 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx27-iomuxc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX1/i.MX25/i.MX27 IOMUX Controller
maintainers:
- Frank Li <Frank.Li@nxp.com>
description:
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
for common binding part and usage.
properties:
compatible:
enum:
- fsl,imx1-iomuxc
- fsl,imx27-iomuxc
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 1
ranges: true
patternProperties:
'^gpio@[0-9a-f]+$':
type: object
$ref: /schemas/gpio/fsl-imx-gpio.yaml
unevaluatedProperties: false
'grp$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
properties:
fsl,pins:
description:
three integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description:
PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32
configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN
is the pin number on the specific port (between 0 and 31)
- description: |
MUX_ID is function + (direction << 2) + (gpio_oconf << 4)
+ (gpio_iconfa << 8) + (gpio_iconfb << 10)
function value is used to select the pin function.
Possible values:
0 - Primary function
1 - Alternate function
2 - GPIO
Registers: GIUS (GPIO In Use), GPR (General Purpose Register)
direction defines the data direction of the pin.
Possible values:
0 - Input
1 - Output
Register: DDIR
gpio_oconf configures the gpio submodule output signal.
This does not have any effect unless GPIO function is
selected. A/B/C_IN are output signals of function blocks
A,B and C. Specific function blocks are described in the
reference manual.
Possible values:
0 - A_IN
1 - B_IN
2 - C_IN
3 - Data Register
Registers: OCR1, OCR2
gpio_iconfa/b configures the gpio submodule input to
functionblocks A and B. GPIO function should be selected if
this is configured.
Possible values:
0 - GPIO_IN
1 - Interrupt Status Register
2 - Pulldown
3 - Pullup
Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
- description:
CONFIG can be 0 or 1, meaning Pullup disable/enable.
required:
- fsl,pins
additionalProperties: false
required:
- compatible
- reg
allOf:
- $ref: pinctrl.yaml#
unevaluatedProperties: false
examples:
- |
pinmux@10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;
uartgrp {
fsl,pins = <
0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
>;
};
};

121
Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
View File

@ -1,121 +0,0 @@
* Freescale IMX27 IOMUX Controller
Required properties:
- compatible: "fsl,imx27-iomuxc"
The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
Required properties for pin configuration node:
- fsl,pins: three integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
number on the specific port (between 0 and 31).
MUX_ID is
function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
function value is used to select the pin function.
Possible values:
0 - Primary function
1 - Alternate function
2 - GPIO
Registers: GIUS (GPIO In Use), GPR (General Purpose Register)
direction defines the data direction of the pin.
Possible values:
0 - Input
1 - Output
Register: DDIR
gpio_oconf configures the gpio submodule output signal. This does not
have any effect unless GPIO function is selected. A/B/C_IN are output
signals of function blocks A,B and C. Specific function blocks are
described in the reference manual.
Possible values:
0 - A_IN
1 - B_IN
2 - C_IN
3 - Data Register
Registers: OCR1, OCR2
gpio_iconfa/b configures the gpio submodule input to functionblocks A and
B. GPIO function should be selected if this is configured.
Possible values:
0 - GPIO_IN
1 - Interrupt Status Register
2 - Pulldown
3 - Pullup
Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
CONFIG can be 0 or 1, meaning Pullup disable/enable.
The iomux controller has gpio child nodes which are embedded in the iomux
control registers. They have to be defined as child nodes of the iomux device
node. If gpio subnodes are defined "#address-cells", "#size-cells" and "ranges"
properties for the iomux device node are required.
Example:
iomuxc: iomuxc@10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio1: gpio@10015000 {
...
};
...
uart {
pinctrl_uart1: uart-1 {
fsl,pins = <
0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
>;
};
...
};
};
For convenience there are macros defined in imx27-pinfunc.h which provide PIN
and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
are defined in the i.MX27 reference manual.
The above example using macros:
iomuxc: iomuxc@10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio1: gpio@10015000 {
...
};
...
uart {
pinctrl_uart1: uart-1 {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
MX27_PAD_UART1_CTS__UART1_CTS 0x0
MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
...
};
};

1
Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml
View File

@ -20,6 +20,7 @@ properties:
compatible:
oneOf:
- enum:
- fsl,imx25-iomuxc
- fsl,imx35-iomuxc
- fsl,imx51-iomuxc
- fsl,imx53-iomuxc

11
Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml
View File

@ -84,11 +84,12 @@ patternProperties:
properties:
groups:
enum: [ emmc_nb, i2c1, i2c2, jtag, mii_col, onewire, pcie1,
pcie1_clkreq, pcie1_wakeup, pmic0, pmic1, ptp, ptp_clk,
ptp_trig, pwm0, pwm1, pwm2, pwm3, rgmii, sdio0, sdio_sb, smi,
spi_cs1, spi_cs2, spi_cs3, spi_quad, uart1, uart2,
usb2_drvvbus1, usb32_drvvbus0 ]
items:
enum: [ emmc_nb, i2c1, i2c2, jtag, mii_col, onewire, pcie1,
pcie1_clkreq, pcie1_wakeup, pmic0, pmic1, ptp, ptp_clk,
ptp_trig, pwm0, pwm1, pwm2, pwm3, rgmii, sdio0, sdio_sb,
smi, spi_cs1, spi_cs2, spi_cs3, spi_quad, uart1, uart2,
usb2_drvvbus1, usb32_drvvbus0 ]
function:
enum: [ drvbus, emmc, gpio, i2c, jtag, led, mii, mii_err, onewire,

98
Documentation/devicetree/bindings/pinctrl/maxim,max77620-pinctrl.yaml Normal file
View File

@ -0,0 +1,98 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/maxim,max77620-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Pinmux controller function for Maxim MAX77620 Power management IC
maintainers:
- Svyatoslav Ryhel <clamor95@gmail.com>
description:
Device has 8 GPIO pins which can be configured as GPIO as well as the
special IO functions.
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml
- $ref: /schemas/pinctrl/pinmux-node.yaml
patternProperties:
"^(pin|gpio).":
type: object
additionalProperties: false
properties:
pins:
items:
enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7 ]
function:
items:
enum: [ gpio, lpm-control-in, fps-out, 32k-out1, sd0-dvs-in, sd1-dvs-in,
reference-out ]
drive-push-pull: true
drive-open-drain: true
bias-pull-up: true
bias-pull-down: true
maxim,active-fps-source:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
FPS source for the GPIOs to get enabled/disabled when system is in
active state. Valid values are:
- MAX77620_FPS_SRC_0: FPS source is FPS0.
- MAX77620_FPS_SRC_1: FPS source is FPS1
- MAX77620_FPS_SRC_2: FPS source is FPS2
- MAX77620_FPS_SRC_NONE: GPIO is not controlled by FPS events and
it gets enabled/disabled by register access.
Absence of this property will leave the FPS configuration register
for that GPIO to default configuration.
maxim,active-fps-power-up-slot:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Sequencing event slot number on which the GPIO get enabled when
master FPS input event set to HIGH. This is applicable if FPS source
is selected as FPS0, FPS1 or FPS2.
enum: [0, 1, 2, 3, 4, 5, 6, 7]
maxim,active-fps-power-down-slot:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Sequencing event slot number on which the GPIO get disabled when
master FPS input event set to LOW. This is applicable if FPS source
is selected as FPS0, FPS1 or FPS2.
enum: [0, 1, 2, 3, 4, 5, 6, 7]
maxim,suspend-fps-source:
$ref: /schemas/types.yaml#/definitions/uint32
description:
This is same as property "maxim,active-fps-source" but value get
configured when system enters in to suspend state.
maxim,suspend-fps-power-up-slot:
$ref: /schemas/types.yaml#/definitions/uint32
description:
This is same as property "maxim,active-fps-power-up-slot" but this
value get configured into FPS configuration register when system
enters into suspend. This is applicable if suspend state FPS source
is selected as FPS0, FPS1 or FPS2.
enum: [0, 1, 2, 3, 4, 5, 6, 7]
maxim,suspend-fps-power-down-slot:
$ref: /schemas/types.yaml#/definitions/uint32
description:
This is same as property "maxim,active-fps-power-down-slot" but this
value get configured into FPS configuration register when system
enters into suspend. This is applicable if suspend state FPS source
is selected as FPS0, FPS1 or FPS2.
enum: [0, 1, 2, 3, 4, 5, 6, 7]
required:
- pins
additionalProperties: false
# see maxim,max77620.yaml for an example

107
Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
View File

@ -162,12 +162,105 @@ properties:
this affects the expected delay in ps before latching a value to
an output pin.
if:
required:
- skew-delay
then:
properties:
skew-delay-input-ps: false
skew-delay-output-ps: false
input-threshold-voltage-microvolt:
description: Specifies the input voltage level of the pin in microvolts.
This defines the reference for VIH (Input High Voltage) and VIL
(Input Low Voltage) thresholds for proper signal detection.
allOf:
- if:
required:
- skew-delay
then:
properties:
skew-delay-input-ps: false
skew-delay-output-ps: false
- if:
required:
- input-disable
then:
properties:
input-enable: false
input-threshold-voltage-microvolt: false
- if:
required:
- output-disable
then:
properties:
output-enable: false
output-impedance-ohms: false
- if:
required:
- output-low
then:
properties:
output-high: false
- if:
required:
- low-power-enable
then:
properties:
low-power-disable: false
- if:
required:
- input-schmitt-disable
then:
properties:
input-schmitt-enable: false
input-schmitt-microvolt: false
- if:
required:
- drive-strength
then:
properties:
drive-strength-microamp: false
- if:
anyOf:
- required:
- drive-open-source
- required:
- drive-open-drain
- required:
- drive-push-pull
then:
oneOf:
- required:
- drive-open-source
- required:
- drive-open-drain
- required:
- drive-push-pull
- if:
anyOf:
- required:
- bias-disable
- required:
- bias-bus-hold
- required:
- bias-pull-up
- required:
- bias-pull-down
- required:
- bias-pull-pin-default
then:
oneOf:
- required:
- bias-disable
- required:
- bias-bus-hold
- required:
- bias-pull-up
- required:
- bias-pull-down
- required:
- bias-pull-pin-default
additionalProperties: true

127
Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt
View File

@ -1,127 +0,0 @@
Pincontrol driver for MAX77620 Power management IC from Maxim Semiconductor.
Device has 8 GPIO pins which can be configured as GPIO as well as the
special IO functions.
Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
for details of the common pinctrl bindings used by client devices,
including the meaning of the phrase "pin configuration node".
Optional Pinmux properties:
--------------------------
Following properties are required if default setting of pins are required
at boot.
- pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
<pinctrl-bindings.txt>.
The pin configurations are defined as child of the pinctrl states node. Each
sub-node have following properties:
Required properties:
------------------
- pins: List of pins. Valid values of pins properties are:
gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7.
Optional properties:
-------------------
Following are optional properties defined as pinmux DT binding document
<pinctrl-bindings.txt>. Absence of properties will leave the configuration
on default.
function,
drive-push-pull,
drive-open-drain,
bias-pull-up,
bias-pull-down.
Valid values for function properties are:
gpio, lpm-control-in, fps-out, 32k-out, sd0-dvs-in, sd1-dvs-in,
reference-out
There are also customised properties for the GPIO1, GPIO2 and GPIO3. These
customised properties are required to configure FPS configuration parameters
of these GPIOs. Please refer <devicetree/bindings/mfd/max77620.txt> for more
detail of Flexible Power Sequence (FPS).
- maxim,active-fps-source: FPS source for the GPIOs to get
enabled/disabled when system is in
active state. Valid values are:
- MAX77620_FPS_SRC_0,
FPS source is FPS0.
- MAX77620_FPS_SRC_1,
FPS source is FPS1
- MAX77620_FPS_SRC_2 and
FPS source is FPS2
- MAX77620_FPS_SRC_NONE.
GPIO is not controlled
by FPS events and it gets
enabled/disabled by register
access.
Absence of this property will leave
the FPS configuration register for that
GPIO to default configuration.
- maxim,active-fps-power-up-slot: Sequencing event slot number on which
the GPIO get enabled when
master FPS input event set to HIGH.
Valid values are 0 to 7.
This is applicable if FPS source is
selected as FPS0, FPS1 or FPS2.
- maxim,active-fps-power-down-slot: Sequencing event slot number on which
the GPIO get disabled when master
FPS input event set to LOW.
Valid values are 0 to 7.
This is applicable if FPS source is
selected as FPS0, FPS1 or FPS2.
- maxim,suspend-fps-source: This is same as property
"maxim,active-fps-source" but value
get configured when system enters in
to suspend state.
- maxim,suspend-fps-power-up-slot: This is same as property
"maxim,active-fps-power-up-slot" but
this value get configured into FPS
configuration register when system
enters into suspend.
This is applicable if suspend state
FPS source is selected as FPS0, FPS1 or
- maxim,suspend-fps-power-down-slot: This is same as property
"maxim,active-fps-power-down-slot" but
this value get configured into FPS
configuration register when system
enters into suspend.
This is applicable if suspend state
FPS source is selected as FPS0, FPS1 or
FPS2.
Example:
--------
#include <dt-bindings/mfd/max77620.h>
...
max77620@3c {
pinctrl-names = "default";
pinctrl-0 = <&spmic_default>;
spmic_default: pinmux@0 {
pin_gpio0 {
pins = "gpio0";
function = "gpio";
};
pin_gpio1 {
pins = "gpio1";
function = "fps-out";
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
pin_gpio2 {
pins = "gpio2";
function = "fps-out";
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
};
};
};

4
Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
View File

@ -38,6 +38,10 @@ properties:
- enum:
- marvell,pxa1908-padconf
- const: pinconf-single
- items:
- enum:
- brcm,bcm7038-padconf
- const: pinctrl-single
reg:
maxItems: 1

138
Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml Normal file
View File

@ -0,0 +1,138 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,eliza-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Eliza TLMM block
maintainers:
- Abel Vesa <abel.vesa@oss.qualcomm.com>
description:
Top Level Mode Multiplexer pin controller in Qualcomm Eliza SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,eliza-tlmm
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 93
gpio-line-names:
maxItems: 185
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-eliza-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-eliza-tlmm-state"
additionalProperties: false
$defs:
qcom-eliza-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-4])$"
- enum: [ ufs_reset ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0,
audio_ref_clk, cam_mclk, cci_async_in, cci_i2c_scl,
cci_i2c_sda, cci_timer, coex_uart1_rx, coex_uart1_tx,
coex_uart2_rx, coex_uart2_tx, dbg_out_clk,
ddr_bist_complete, ddr_bist_fail, ddr_bist_start,
ddr_bist_stop, ddr_pxi0, ddr_pxi1, dp0_hot, egpio,
gcc_gp1, gcc_gp2, gcc_gp3, gnss_adc0, gnss_adc1,
hdmi_ddc_scl, hdmi_ddc_sda, hdmi_dtest0, hdmi_dtest1,
hdmi_hot_plug, hdmi_pixel_clk, hdmi_rcv_det, hdmi_tx_cec,
host2wlan_sol, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws,
ibi_i3c, jitter_bist, mdp_esync0_out, mdp_esync1_out,
mdp_vsync, mdp_vsync0_out, mdp_vsync11_out,
mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out,
mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3,
pcie0_clk_req_n, pcie1_clk_req_n, phase_flag,
pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1,
prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio_traceclk,
qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable,
qlink_big_request, qlink_little_enable,
qlink_little_request, qlink_wmss, qspi0, qspi_clk,
qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4,
qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1,
qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6,
qup2_se7, resout_gpio, sd_write_protect, sdc1, sdc2,
sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tmess_prng0,
tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1,
tsense_pwm2, tsense_pwm3, tsense_pwm4, uim0_clk,
uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data,
uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1,
vsense_trigger_mirnat, wcn_sw_ctrl ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@f100000 {
compatible = "qcom,eliza-tlmm";
reg = <0x0f100000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 186>;
gpio-wo-state {
pins = "gpio1";
function = "gpio";
};
qup-uart14-default-state {
pins = "gpio18", "gpio19";
function = "qup2_se5";
drive-strength = <2>;
bias-disable;
};
};
...

120
Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml Normal file
View File

@ -0,0 +1,120 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,hawi-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Hawi TLMM block
maintainers:
- Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
description:
Top Level Mode Multiplexer pin controller in Qualcomm Hawi SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,hawi-tlmm
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 113
gpio-line-names:
maxItems: 226
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-hawi-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-hawi-tlmm-state"
additionalProperties: false
$defs:
qcom-hawi-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-9]|22[0-5])$"
- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk,
audio_ref_clk, cam_mclk, cci_async_in, cci_i2c0, cci_i2c1,
cci_i2c2, cci_i2c3, cci_i2c4, cci_i2c5, cci_timer, coex_espmi,
coex_uart1_rx, coex_uart1_tx, dbg_out_clk, ddr_bist, ddr_pxi,
dp_hot, egpio, gcc_gp, gnss_adc, host_rst, i2chub0_se0,
i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4, i2s0, i2s1,
ibi_i3c, jitter_bist, mdp_esync0, mdp_esync1, mdp_esync2,
mdp_vsync, mdp_vsync_e, mdp_vsync_p, mdp_vsync0_out,
mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out,
modem_pps_in, modem_pps_out, nav_gpio, nav_gpio0, nav_gpio3,
nav_rffe, pcie0_clk_req_n, pcie0_rst_n, pcie1_clk_req_n,
phase_flag, pll_bist_sync, pll_clk_aux, qdss_cti, qlink,
qspi, qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2,
qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0,
qup2_se1, qup2_se2, qup2_se3, qup2_se4_01, qup2_se4_23,
qup3_se0_01, qup3_se0_23, qup3_se1, qup3_se2, qup3_se3,
qup3_se4, qup3_se5, qup4_se0, qup4_se1, qup4_se2, qup4_se3_01,
qup4_se3_23, qup4_se3_l3, qup4_se4_01, qup4_se4_23, qup4_se4_l3,
rng_rosc, sd_write_protect, sdc4_clk, sdc4_cmd, sdc4_data,
sys_throttle, tb_trig_sdc, tmess_rng, tsense_clm, tsense_pwm,
uim0, uim1, usb0_hs, usb_phy, vfr, vsense_trigger_mirnat,
wcn_sw_ctrl ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@f100000 {
compatible = "qcom,hawi-tlmm";
reg = <0x0f100000 0x300000>;
interrupts = <GIC_ESPI 272 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 227>;
interrupt-controller;
#interrupt-cells = <2>;
qup-uart7-state {
pins = "gpio62", "gpio63";
function = "qup1_se7";
};
};
...

123
Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml Normal file
View File

@ -0,0 +1,123 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5210-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm IPQ5210 TLMM pin controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
description:
Top Level Mode Multiplexer pin controller in Qualcomm IPQ5210 SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,ipq5210-tlmm
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 27
gpio-line-names:
maxItems: 54
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-ipq5210-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-ipq5210-tlmm-state"
additionalProperties: false
$defs:
qcom-ipq5210-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$"
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ atest_char_start, atest_char_status0, atest_char_status1,
atest_char_status2, atest_char_status3, atest_tic_en, audio_pri,
audio_pri_mclk_out0, audio_pri_mclk_in0, audio_pri_mclk_out1,
audio_pri_mclk_in1, audio_pri_mclk_out2, audio_pri_mclk_in2,
audio_pri_mclk_out3, audio_pri_mclk_in3, audio_sec,
audio_sec_mclk_out0, audio_sec_mclk_in0, audio_sec_mclk_out1,
audio_sec_mclk_in1, audio_sec_mclk_out2, audio_sec_mclk_in2,
audio_sec_mclk_out3, audio_sec_mclk_in3, core_voltage_0,
cri_trng0, cri_trng1, cri_trng2, cri_trng3, dbg_out_clk, dg_out,
gcc_plltest_bypassnl, gcc_plltest_resetn, gcc_tlmm, gpio, led0,
led1, led2, mdc_mst, mdc_slv0, mdc_slv1, mdc_slv2, mdio_mst,
mdio_slv0, mdio_slv1, mdio_slv2, mux_tod_out, pcie0_clk_req_n,
pcie0_wake, pcie1_clk_req_n, pcie1_wake, pll_test,
pon_active_led, pon_mux_sel, pon_rx, pon_rx_los, pon_tx,
pon_tx_burst, pon_tx_dis, pon_tx_fault, pon_tx_sd, gpn_rx_los,
gpn_tx_burst, gpn_tx_dis, gpn_tx_fault, gpn_tx_sd, pps, pwm0,
pwm1, pwm2, pwm3, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a,
qdss_tracedata_a, qrng_rosc0, qrng_rosc1, qrng_rosc2,
qspi_data, qspi_clk, qspi_cs_n, qup_se0, qup_se1, qup_se2,
qup_se3, qup_se4, qup_se5, qup_se5_l1, resout, rx_los0, rx_los1,
rx_los2, sdc_clk, sdc_cmd, sdc_data, tsens_max ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5210-tlmm";
reg = <0x01000000 0x300000>;
gpio-controller;
#gpio-cells = <0x2>;
gpio-ranges = <&tlmm 0 0 54>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <0x2>;
qup-uart1-default-state {
pins = "gpio38", "gpio39";
function = "qup_se1";
drive-strength = <6>;
bias-pull-down;
};
};

8
Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-common.yaml
View File

@ -27,6 +27,14 @@ properties:
gpio-ranges:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 30
description:
Pins can be reserved for trusted applications or for LPASS, thereby
inaccessible from the OS. This property can be used to mark the pins
which resources should not be accessed by the OS.
required:
- gpio-controller
- "#gpio-cells"

109
Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml Normal file
View File

@ -0,0 +1,109 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Milos SoC LPASS LPI TLMM
maintainers:
- Luca Weiss <luca.weiss@fairphone.com>
description:
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
(LPASS) Low Power Island (LPI) of Qualcomm Milos SoC.
properties:
compatible:
const: qcom,milos-lpass-lpi-pinctrl
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
- description: LPASS LPI MCC registers
clocks:
items:
- description: LPASS Core voting clock
- description: LPASS Audio voting clock
clock-names:
items:
- const: core
- const: audio
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-milos-lpass-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-milos-lpass-state"
additionalProperties: false
$defs:
qcom-milos-lpass-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
function:
enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,
dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b,
ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk,
i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,
i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, qca_swr_clk,
qca_swr_data, slimbus_clk, slimbus_data, swr_rx_clk,
swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk,
wsa_swr_data ]
description:
Specify the alternative function to be configured for the specified
pins.
allOf:
- $ref: qcom,lpass-lpi-common.yaml#
required:
- compatible
- reg
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
pinctrl@3440000 {
compatible = "qcom,milos-lpass-lpi-pinctrl";
reg = <0x03440000 0x20000>,
<0x034d0000 0x10000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 23>;
clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core",
"audio";
tx-swr-active-clk-state {
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <4>;
slew-rate = <1>;
bias-disable;
};
};

81
Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml Normal file
View File

@ -0,0 +1,81 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SDM670 SoC LPASS LPI TLMM
maintainers:
- Richard Acayan <mailingradian@gmail.com>
description:
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
(LPASS) Low Power Island (LPI) of Qualcomm SDM670 SoC.
properties:
compatible:
const: qcom,sdm670-lpass-lpi-pinctrl
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-sdm670-lpass-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-sdm670-lpass-state"
additionalProperties: false
$defs:
qcom-sdm670-lpass-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|1[0-9]|2[0-9]|3[0-1])$"
function:
enum: [ gpio, comp_rx, dmic1_clk, dmic1_data, dmic2_clk, dmic2_data,
i2s1_clk, i2s_data, i2s_ws, lpi_cdc_rst, mclk0, pdm_rx,
pdm_sync, pdm_tx, slimbus_clk ]
description:
Specify the alternative function to be configured for the specified
pins.
allOf:
- $ref: qcom,lpass-lpi-common.yaml#
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
lpi_tlmm: pinctrl@62b40000 {
compatible = "qcom,sdm670-lpass-lpi-pinctrl";
reg = <0x62b40000 0x20000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpi_tlmm 0 0 32>;
cdc_comp_default: cdc-comp-default-state {
pins = "gpio22", "gpio24";
function = "comp_rx";
drive-strength = <4>;
};
};

8
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
View File

@ -15,7 +15,13 @@ description:
properties:
compatible:
const: qcom,sm8450-lpass-lpi-pinctrl
oneOf:
- const: qcom,sm8450-lpass-lpi-pinctrl
- items:
- enum:
- qcom,qcs8300-lpass-lpi-pinctrl
- qcom,sa8775p-lpass-lpi-pinctrl
- const: qcom,sm8450-lpass-lpi-pinctrl
reg:
items:

4
Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml
View File

@ -19,7 +19,9 @@ properties:
oneOf:
- const: qcom,sm8650-lpass-lpi-pinctrl
- items:
- const: qcom,sm8750-lpass-lpi-pinctrl
- enum:
- qcom,glymur-lpass-lpi-pinctrl
- qcom,sm8750-lpass-lpi-pinctrl
- const: qcom,sm8650-lpass-lpi-pinctrl
reg:

7
Documentation/devicetree/bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml
View File

@ -135,8 +135,11 @@ patternProperties:
realtek,duty-cycle:
description: |
An integer describing the level to adjust output duty cycle, controlling
the proportion of positive and negative waveforms in nanoseconds.
An integer describing the level to adjust the output pulse width, it
provides a fixed nanosecond-level adjustment to the rising/falling
edges of an existing signal. It is used for Signal Integrity tuning
(adding/subtracting delay to fine-tune the high/low duration), rather
than generating a specific PWM frequency.
Valid arguments are described as below:
0: 0ns
2: + 0.25ns

7
Documentation/devicetree/bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml
View File

@ -134,8 +134,11 @@ patternProperties:
realtek,duty-cycle:
description: |
An integer describing the level to adjust output duty cycle, controlling
the proportion of positive and negative waveforms in nanoseconds.
An integer describing the level to adjust the output pulse width, it
provides a fixed nanosecond-level adjustment to the rising/falling
edges of an existing signal. It is used for Signal Integrity tuning
(adding/subtracting delay to fine-tune the high/low duration), rather
than generating a specific PWM frequency.
Valid arguments are described as below:
0: 0ns
2: + 0.25ns

7
Documentation/devicetree/bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml
View File

@ -133,8 +133,11 @@ patternProperties:
realtek,duty-cycle:
description: |
An integer describing the level to adjust output duty cycle, controlling
the proportion of positive and negative waveforms in nanoseconds.
An integer describing the level to adjust the output pulse width, it
provides a fixed nanosecond-level adjustment to the rising/falling
edges of an existing signal. It is used for Signal Integrity tuning
(adding/subtracting delay to fine-tune the high/low duration), rather
than generating a specific PWM frequency.
Valid arguments are described as below:
0: 0ns
2: + 0.25ns

260
Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml Normal file
View File

@ -0,0 +1,260 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2025 Realtek Semiconductor Corporation
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/realtek,rtd1625-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Realtek DHC RTD1625 Pin Controller
maintainers:
- Tzuyi Chang <tychang@realtek.com>
- Yu-Chun Lin <eleanor.lin@realtek.com>
description:
The Realtek DHC RTD1625 is a high-definition media processor SoC. The
RTD1625 pin controller is used to control pin function, pull-up/down
resistors, drive strength, slew rate, Schmitt trigger, power source
(I/O output voltage), input threshold domain selection and a higher-VIL mode.
properties:
compatible:
items:
- enum:
- realtek,rtd1625-iso-pinctrl
- realtek,rtd1625-main2-pinctrl
- realtek,rtd1625-isom-pinctrl
- realtek,rtd1625-ve4-pinctrl
reg:
maxItems: 1
patternProperties:
'-pins$':
type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
properties:
pins:
items:
enum: [gpio_0, gpio_1, gpio_2, gpio_3, gpio_4, gpio_5, gpio_6,
gpio_7, gpio_8, gpio_9, gpio_10, gpio_11, gpio_12, gpio_13,
gpio_14, gpio_15, gpio_16, gpio_17, gpio_18, gpio_19, gpio_20,
gpio_21, gpio_22, gpio_23, gpio_24, gpio_25, gpio_28, gpio_29,
gpio_30, gpio_31, gpio_32, gpio_33, gpio_34, gpio_35, gpio_40,
gpio_41, gpio_42, gpio_43, gpio_44, gpio_45, gpio_46, gpio_47,
gpio_48, gpio_49, gpio_50, gpio_51, gpio_52, gpio_53, gpio_54,
gpio_55, gpio_56, gpio_57, gpio_58, gpio_59, gpio_60, gpio_61,
gpio_62, gpio_63, gpio_64, gpio_65, gpio_66, gpio_67, gpio_80,
gpio_81, gpio_82, gpio_83, gpio_84, gpio_85, gpio_86, gpio_87,
gpio_88, gpio_89, gpio_90, gpio_91, gpio_92, gpio_93, gpio_94,
gpio_95, gpio_96, gpio_97, gpio_98, gpio_99, gpio_100,
gpio_101, gpio_102, gpio_103, gpio_104, gpio_105, gpio_106,
gpio_107, gpio_108, gpio_109, gpio_110, gpio_111, gpio_112,
gpio_128, gpio_129, gpio_130, gpio_131, gpio_132, gpio_133,
gpio_134, gpio_135, gpio_136, gpio_137, gpio_138, gpio_139,
gpio_140, gpio_141, gpio_142, gpio_143, gpio_144, gpio_145,
gpio_146, gpio_147, gpio_148, gpio_149, gpio_150, gpio_151,
gpio_152, gpio_153, gpio_154, gpio_155, gpio_156, gpio_157,
gpio_158, gpio_159, gpio_160, gpio_161, gpio_162, gpio_163,
gpio_164, gpio_165, ai_i2s1_loc, ao_i2s1_loc, arm_trace_dbg_en,
csi_vdsel, ejtag_acpu_loc, ejtag_aucpu0_loc, ejtag_aucpu1_loc,
ejtag_pcpu_loc, ejtag_scpu_loc, ejtag_ve2_loc, emmc_clk,
emmc_cmd, emmc_data_0, emmc_data_1, emmc_data_2, emmc_data_3,
emmc_data_4, emmc_data_5, emmc_data_6, emmc_data_7,
emmc_dd_sb, emmc_rst_n, etn_phy_loc, hif_clk, hif_data,
hif_en, hif_rdy, hi_width, i2c6_loc, ir_rx_loc, rgmii_vdsel,
sf_en, spdif_in_mode, spdif_loc, uart0_loc, usb_cc1, usb_cc2,
ve4_uart_loc]
function:
enum: [gpio, ai_i2s0, ai_i2s2, ai_tdm0, ai_tdm1, ai_tdm2, ao_i2s0,
ao_i2s2, ao_tdm0, ao_tdm1, ao_tdm2, csi0, csi1, csi_1v2, csi_1v8,
csi_2v5, csi_3v3, dmic0, dmic1, dmic2, dptx_hpd, edptx_hdp, emmc,
gspi0, gspi1, gspi2, hi_width_1bit, hi_width_disable, i2c0, i2c1,
i2c3, i2c4, i2c5, i2c7, iso_tristate, pcie0, pcie1, pcm, pctrl,
pwm4, pwm5, pwm6, rgmii, rgmii_1v2, rgmii_1v8, rgmii_2v5,
rgmii_3v3, rmii, sd, sdio, sf_disable, sf_enable,
spdif_in_coaxial, spdif_in_gpio, spdif_out, spi, ts0, ts1, uart1,
uart2, uart3, uart4, uart5, uart6, uart7, uart8, uart9, uart10,
usb_cc1, usb_cc2, vi0_dtv, vi1_dtv, vtc_ao_i2s, vtc_dmic,
vtc_i2s, ai_i2s1_loc0, ai_i2s1_loc1, ao_i2s0_loc0, ao_i2s0_loc1,
ao_i2s1_loc0, ao_i2s1_loc1, ao_tdm1_loc0, ao_tdm1_loc1,
etn_led_loc0, etn_led_loc1, etn_phy_loc0, etn_phy_loc1,
i2c6_loc0, i2c6_loc1, ir_rx_loc0, ir_rx_loc1, pwm0_loc0,
pwm0_loc1, pwm0_loc2, pwm0_loc3, pwm1_loc0, pwm1_loc1, pwm2_loc0,
pwm2_loc1, pwm3_loc0, pwm3_loc1, spdif_loc0, spdif_loc1,
uart0_loc0, uart0_loc1, ve4_uart_loc0, ve4_uart_loc1,
ve4_uart_loc2, acpu_ejtag_loc0, acpu_ejtag_loc1, acpu_ejtag_loc2,
aucpu0_ejtag_loc0, aucpu0_ejtag_loc1, aucpu0_ejtag_loc2,
aucpu1_ejtag_loc0, aucpu1_ejtag_loc1, aucpu1_ejtag_loc2,
aupu0_ejtag_loc1, aupu1_ejtag_loc1, gpu_ejtag_loc0,
pcpu_ejtag_loc0, pcpu_ejtag_loc1, pcpu_ejtag_loc2,
scpu_ejtag_loc0, scpu_ejtag_loc1, scpu_ejtag_loc2,
ve2_ejtag_loc0, ve2_ejtag_loc1, ve2_ejtag_loc2, pll_test_loc0,
pll_test_loc1, dbg_out1, isom_dbg_out, arm_trace_debug_disable,
arm_trace_debug_enable]
drive-strength:
enum: [4, 8]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
input-schmitt-enable: true
input-schmitt-disable: true
input-voltage-microvolt:
description: |
Select the input receiver voltage domain for the pin.
Valid arguments are:
- 1800000: 1.8V input logic level
- 3300000: 3.3V input logic level
enum: [1800000, 3300000]
drive-push-pull: true
power-source:
description: |
Valid arguments are described as below:
0: power supply of 1.8V
1: power supply of 3.3V
enum: [0, 1]
slew-rate:
description: |
Valid arguments are described as below:
1: ~1ns falling time
10: ~10ns falling time
20: ~20ns falling time
30: ~30ns falling time
enum: [1, 10, 20, 30]
realtek,drive-strength-p:
description: |
Some of pins can be driven using the P-MOS and N-MOS transistor to
achieve finer adjustments. The block-diagram representation is as
follows:
VDD
|
||--+
+-----o|| P-MOS-FET
| ||--+
IN --+ +----- out
| ||--+
+------|| N-MOS-FET
||--+
|
GND
The driving strength of the P-MOS/N-MOS transistors impacts the
waveform's rise/fall times. Greater driving strength results in
shorter rise/fall times. Each P-MOS and N-MOS transistor offers
8 configurable levels (0 to 7), with higher values indicating
greater driving strength, contributing to achieving the desired
speed.
The realtek,drive-strength-p is used to control the driving strength
of the P-MOS output.
This value is not a simple count of transistors. Instead, it
represents a weighted configuration. There is a base driving
capability (even at value 0), and each bit adds a different weight to
the total strength. The resulting current is non-linear and varies
significantly based on the IO voltage (1.8V vs 3.3V) and the specific
pad group.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 7
realtek,drive-strength-n:
description: |
Similar to the realtek,drive-strength-p, the realtek,drive-strength-n
is used to control the driving strength of the N-MOS output.
This property uses the same weighted configuration logic where values
0-7 represent non-linear strength adjustments rather than a transistor
count.
Higher values indicate greater driving strength, resulting in shorter
fall times.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 7
realtek,duty-cycle:
description: |
An integer describing the level to adjust the output pulse width, it
provides a fixed nanosecond-level adjustment to the rising/falling
edges of an existing signal. It is used for Signal Integrity tuning
(adding/subtracting delay to fine-tune the high/low duration), rather
than generating a specific PWM frequency.
Valid arguments are described as below:
0: 0ns
2: + 0.25ns
3: + 0.5ns
4: -0.25ns
5: -0.5ns
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 2, 3, 4, 5]
realtek,high-vil-microvolt:
description: |
The threshold value for the input receiver's LOW recognition (VIL).
This property is used to address specific HDMI I2C compatibility
issues where some sinks (TVs) have weak pull-down capabilities and
fail to pull the bus voltage below the standard VIL threshold
(~0.7V).
Setting this property to 1100000 (1.1V) enables a specialized input
receiver mode that raises the effective VIL threshold to improve
detection.
enum: [1100000]
required:
- pins
additionalProperties: false
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pinctrl@4e000 {
compatible = "realtek,rtd1625-iso-pinctrl";
reg = <0x4e000 0x130>;
emmc-hs200-pins {
pins = "emmc_clk",
"emmc_cmd",
"emmc_data_0",
"emmc_data_1",
"emmc_data_2",
"emmc_data_3",
"emmc_data_4",
"emmc_data_5",
"emmc_data_6",
"emmc_data_7";
function = "emmc";
realtek,drive-strength-p = <2>;
realtek,drive-strength-n = <2>;
};
i2c-0-pins {
pins = "gpio_12",
"gpio_13";
function = "i2c0";
drive-strength = <4>;
};
};

17
Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
View File

@ -83,6 +83,23 @@ definitions:
input: true
input-enable: true
output-enable: true
bias-disable: true
bias-pull-down: true
bias-pull-up: true
input-schmitt-enable: true
input-schmitt-disable: true
slew-rate:
description: 0 is slow slew rate, 1 is fast slew rate
enum: [0, 1]
drive-strength-microamp:
description: |
Four discrete levels are supported (via registers DRCTLm), corresponding
to the following nominal values:
- 2500 (Low strength)
- 5000 (Middle strength)
- 9000 (High strength)
- 11800 (Ultra High strength)
enum: [2500, 5000, 9000, 11800]
oneOf:
- required: [pinmux]
- required: [pins]

1
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
View File

@ -50,6 +50,7 @@ properties:
- rockchip,rk3568-pinctrl
- rockchip,rk3576-pinctrl
- rockchip,rk3588-pinctrl
- rockchip,rv1103b-pinctrl
- rockchip,rv1108-pinctrl
- rockchip,rv1126-pinctrl

2
drivers/gpio/gpio-rockchip.c
View File

@ -296,7 +296,7 @@ static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
*/
return -ENOTSUPP;
default:
return -ENOTSUPP;
return gpiochip_generic_config(gc, offset, config);
}
}

1
drivers/gpio/gpio-spacemit-k1.c
View File

@ -228,6 +228,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg,
gc->label = dev_name(dev);
gc->request = gpiochip_generic_request;
gc->free = gpiochip_generic_free;
gc->set_config = gpiochip_generic_config;
gc->ngpio = SPACEMIT_NR_GPIOS_PER_BANK;
gc->base = -1;
gc->of_gpio_n_cells = 3;

11
drivers/pinctrl/Kconfig
View File

@ -77,7 +77,6 @@ config PINCTRL_APPLE_GPIO
select GPIOLIB_IRQCHIP
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select OF_GPIO
help
This is the driver for the GPIO controller found on Apple ARM SoCs,
including M1.
@ -126,7 +125,6 @@ config PINCTRL_AT91PIO4
select GENERIC_PINCONF
select GPIOLIB
select GPIOLIB_IRQCHIP
select OF_GPIO
help
Say Y here to enable the at91 pinctrl/gpio driver for Atmel PIO4
controller available on sama5d2 SoC.
@ -293,7 +291,6 @@ config PINCTRL_K210
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
select GPIOLIB
select OF_GPIO
select REGMAP_MMIO
default SOC_CANAAN_K210
help
@ -419,7 +416,6 @@ config PINCTRL_MICROCHIP_SGPIO
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select OF_GPIO
help
Support for the serial GPIO interface used on Microsemi and
Microchip SoCs. By using a serial interface, the SIO
@ -441,7 +437,6 @@ config PINCTRL_OCELOT
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select OF_GPIO
select REGMAP_MMIO
help
Support for the internal GPIO interfaces on Microsemi Ocelot and
@ -478,11 +473,10 @@ config PINCTRL_PEF2256
config PINCTRL_PIC32
bool "Microchip PIC32 pin controller driver"
depends on OF
depends on MACH_PIC32
depends on MACH_PIC32 || COMPILE_TEST
select PINMUX
select GENERIC_PINCONF
select GPIOLIB_IRQCHIP
select OF_GPIO
help
This is the pin controller and gpio driver for Microchip PIC32
microcontrollers. This option is selected automatically when specific
@ -499,7 +493,6 @@ config PINCTRL_PISTACHIO
select PINMUX
select GENERIC_PINCONF
select GPIOLIB_IRQCHIP
select OF_GPIO
help
This support pinctrl and GPIO driver for IMG Pistachio SoC.
@ -521,7 +514,6 @@ config PINCTRL_ROCKCHIP
select GENERIC_PINCONF
select GENERIC_IRQ_CHIP
select MFD_SYSCON
select OF_GPIO
default ARCH_ROCKCHIP
help
This support pinctrl and GPIO driver for Rockchip SoCs.
@ -557,7 +549,6 @@ config PINCTRL_ST
config PINCTRL_STMFX
tristate "STMicroelectronics STMFX GPIO expander pinctrl driver"
depends on I2C
depends on OF_GPIO
depends on HAS_IOMEM
select GENERIC_PINCONF
select GPIOLIB_IRQCHIP

4
drivers/pinctrl/bcm/Kconfig
View File

@ -120,7 +120,7 @@ source "drivers/pinctrl/bcm/Kconfig.stb"
config PINCTRL_IPROC_GPIO
bool "Broadcom iProc GPIO (with PINCONF) driver"
depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)
depends on ARCH_BCM_IPROC || COMPILE_TEST
select GPIOLIB_IRQCHIP
select PINCONF
select GENERIC_PINCONF
@ -185,7 +185,7 @@ config PINCTRL_NS
config PINCTRL_NSP_GPIO
bool "Broadcom NSP GPIO (with PINCONF) driver"
depends on OF_GPIO && (ARCH_BCM_NSP || COMPILE_TEST)
depends on ARCH_BCM_NSP || COMPILE_TEST
select GPIOLIB_IRQCHIP
select PINCONF
select GENERIC_PINCONF

7
drivers/pinctrl/core.c
View File

@ -24,7 +24,7 @@
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/driver.h>
#include <linux/pinctrl/consumer.h>
@ -1381,7 +1381,8 @@ static int pinctrl_commit_state(struct pinctrl *p, struct pinctrl_state *state)
goto restore_old_state;
unapply_new_state:
dev_err(p->dev, "Error applying setting, reverse things back\n");
dev_err_probe(p->dev, ret,
"Error applying setting, reverse things back\n");
/*
* All we can do here is pinmux_disable_setting.
@ -2022,7 +2023,7 @@ static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev)
device_root = debugfs_create_dir(debugfs_name, debugfs_root);
pctldev->device_root = device_root;
if (IS_ERR(device_root) || !device_root) {
if (IS_ERR_OR_NULL(device_root)) {
pr_warn("failed to create debugfs directory for %s\n",
dev_name(pctldev->dev));
return;

2
drivers/pinctrl/devicetree.c
View File

@ -175,7 +175,7 @@ static int dt_to_map_one_config(struct pinctrl *p,
* return.
*/
dev_info(p->dev,
"there is not valid maps for state %s\n", statename);
"there are no valid maps for state %s\n", statename);
return 0;
}

2
drivers/pinctrl/freescale/Kconfig
View File

@ -9,7 +9,7 @@ config PINCTRL_IMX
config PINCTRL_IMX_SCMI
tristate "i.MX95 pinctrl driver using SCMI protocol interface"
depends on ARM_SCMI_PROTOCOL && OF
depends on (ARM_SCMI_PROTOCOL && OF && ARCH_MXC) || COMPILE_TEST
select PINMUX
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS

1
drivers/pinctrl/meson/Kconfig
View File

@ -8,7 +8,6 @@ menuconfig PINCTRL_MESON
select PINCONF
select GENERIC_PINCONF
select GPIOLIB
select OF_GPIO
select REGMAP_MMIO
if PINCTRL_MESON

2
drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c
View File

@ -686,7 +686,7 @@ static int mpfs_pinctrl_probe(struct platform_device *pdev)
pctrl->regmap = device_node_to_regmap(pdev->dev.parent->of_node);
if (IS_ERR(pctrl->regmap))
dev_err_probe(dev, PTR_ERR(pctrl->regmap), "Failed to find syscon regmap\n");
return dev_err_probe(dev, PTR_ERR(pctrl->regmap), "Failed to find syscon regmap\n");
pctrl->sysreg_regmap = syscon_regmap_lookup_by_compatible("microchip,mpfs-sysreg-scb");
if (IS_ERR(pctrl->sysreg_regmap))

2
drivers/pinctrl/nomadik/pinctrl-abx500.c
View File

@ -852,7 +852,7 @@ static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
int ret = -EINVAL;
int i;
enum pin_config_param param;
enum pin_config_param argument;
unsigned int argument;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);

2
drivers/pinctrl/nxp/pinctrl-s32.h
View File

@ -16,7 +16,7 @@ struct platform_device;
/**
* struct s32_pin_group - describes an S32 pin group
* @data: generic data describes group name, number of pins, and a pin array in
this group.
* this group.
* @pin_sss: an array of source signal select configs paired with pin array.
*/
struct s32_pin_group {

94
drivers/pinctrl/pinconf-generic.c
View File

@ -16,6 +16,7 @@
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/property.h>
#include <linux/slab.h>
#include <linux/seq_file.h>
@ -56,6 +57,7 @@ static const struct pin_config_item conf_items[] = {
PCONFDUMP(PIN_CONFIG_SKEW_DELAY, "skew delay", NULL, true),
PCONFDUMP(PIN_CONFIG_SKEW_DELAY_INPUT_PS, "input skew delay", "ps", true),
PCONFDUMP(PIN_CONFIG_SKEW_DELAY_OUTPUT_PS, "output skew delay", "ps", true),
PCONFDUMP(PIN_CONFIG_INPUT_VOLTAGE_UV, "input voltage in microvolt", "uV", true),
};
static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev,
@ -202,27 +204,31 @@ static const struct pinconf_generic_params dt_params[] = {
{ "skew-delay", PIN_CONFIG_SKEW_DELAY, 0 },
{ "skew-delay-input-ps", PIN_CONFIG_SKEW_DELAY_INPUT_PS, 0 },
{ "skew-delay-output-ps", PIN_CONFIG_SKEW_DELAY_OUTPUT_PS, 0 },
{ "input-threshold-voltage-microvolt", PIN_CONFIG_INPUT_VOLTAGE_UV, 0 },
};
/**
* parse_dt_cfg() - Parse DT pinconf parameters
* @np: DT node
* parse_fw_cfg() - Parse firmware pinconf parameters
* @fwnode: firmware node
* @params: Array of describing generic parameters
* @count: Number of entries in @params
* @cfg: Array of parsed config options
* @ncfg: Number of entries in @cfg
*
* Parse the config options described in @params from @np and puts the result
* Parse the config options described in @params from @fwnode and puts the result
* in @cfg. @cfg does not need to be empty, entries are added beginning at
* @ncfg. @ncfg is updated to reflect the number of entries after parsing. @cfg
* needs to have enough memory allocated to hold all possible entries.
*/
static int parse_dt_cfg(struct device_node *np,
static int parse_fw_cfg(struct fwnode_handle *fwnode,
const struct pinconf_generic_params *params,
unsigned int count, unsigned long *cfg,
unsigned int *ncfg)
{
int i;
unsigned long *properties;
int i, test;
properties = bitmap_zalloc(count, GFP_KERNEL);
for (i = 0; i < count; i++) {
u32 val;
@ -230,7 +236,7 @@ static int parse_dt_cfg(struct device_node *np,
const struct pinconf_generic_params *par = &params[i];
if (par->values && par->num_values) {
ret = fwnode_property_match_property_string(of_fwnode_handle(np),
ret = fwnode_property_match_property_string(fwnode,
par->property,
par->values, par->num_values);
if (ret == -ENOENT)
@ -240,7 +246,7 @@ static int parse_dt_cfg(struct device_node *np,
ret = 0;
}
} else {
ret = of_property_read_u32(np, par->property, &val);
ret = fwnode_property_read_u32(fwnode, par->property, &val);
}
/* property not found */
@ -251,11 +257,45 @@ static int parse_dt_cfg(struct device_node *np,
if (ret)
val = par->default_value;
/* if param is greater than count, these are custom properties */
if (par->param <= count) {
ret = test_and_set_bit(par->param, properties);
if (ret) {
pr_err("%pfw: conflicting setting detected for %s\n",
fwnode, par->property);
bitmap_free(properties);
return -EINVAL;
}
}
pr_debug("found %s with value %u\n", par->property, val);
cfg[*ncfg] = pinconf_to_config_packed(par->param, val);
(*ncfg)++;
}
if (test_bit(PIN_CONFIG_DRIVE_STRENGTH, properties) &&
test_bit(PIN_CONFIG_DRIVE_STRENGTH_UA, properties))
pr_err("%pfw: cannot have multiple drive strength properties\n",
fwnode);
test = test_bit(PIN_CONFIG_BIAS_BUS_HOLD, properties) +
test_bit(PIN_CONFIG_BIAS_DISABLE, properties) +
test_bit(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, properties) +
test_bit(PIN_CONFIG_BIAS_PULL_UP, properties) +
test_bit(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, properties) +
test_bit(PIN_CONFIG_BIAS_PULL_DOWN, properties);
if (test > 1)
pr_err("%pfw: cannot have multiple bias configurations\n",
fwnode);
test = test_bit(PIN_CONFIG_DRIVE_OPEN_DRAIN, properties) +
test_bit(PIN_CONFIG_DRIVE_OPEN_SOURCE, properties) +
test_bit(PIN_CONFIG_DRIVE_PUSH_PULL, properties);
if (test > 1)
pr_err("%pfw: cannot have multiple drive configurations\n",
fwnode);
bitmap_free(properties);
return 0;
}
@ -274,17 +314,22 @@ int pinconf_generic_parse_dt_pinmux(struct device_node *np, struct device *dev,
unsigned int **pid, unsigned int **pmux,
unsigned int *npins)
{
struct fwnode_handle *fwnode = of_fwnode_handle(np);
unsigned int *pid_t;
unsigned int *pmux_t;
struct property *prop;
unsigned int npins_t, i;
u32 value;
int ret;
prop = of_find_property(np, "pinmux", NULL);
if (!prop) {
ret = fwnode_property_count_u32(fwnode, "pinmux");
if (ret < 0) {
dev_info(dev, "Missing pinmux property\n");
return -ENOENT;
return ret;
}
npins_t = ret;
if (npins_t == 0) {
dev_info(dev, "pinmux property doesn't have entries\n");
return -ENODATA;
}
if (!pid || !pmux || !npins) {
@ -292,21 +337,22 @@ int pinconf_generic_parse_dt_pinmux(struct device_node *np, struct device *dev,
return -EINVAL;
}
npins_t = prop->length / sizeof(u32);
pid_t = devm_kcalloc(dev, npins_t, sizeof(*pid_t), GFP_KERNEL);
pmux_t = devm_kcalloc(dev, npins_t, sizeof(*pmux_t), GFP_KERNEL);
if (!pid_t || !pmux_t) {
dev_err(dev, "kalloc memory fail\n");
return -ENOMEM;
}
ret = fwnode_property_read_u32_array(fwnode, "pinmux", pmux_t, npins_t);
if (ret) {
dev_err(dev, "get pinmux value fail\n");
goto exit;
}
for (i = 0; i < npins_t; i++) {
ret = of_property_read_u32_index(np, "pinmux", i, &value);
if (ret) {
dev_err(dev, "get pinmux value fail\n");
goto exit;
}
pmux_t[i] = value & 0xff;
pid_t[i] = (value >> 8) & 0xffffff;
pid_t[i] = pmux_t[i] >> 8;
pmux_t[i] = pmux_t[i] & 0xff;
}
*pid = pid_t;
*pmux = pmux_t;
@ -336,9 +382,11 @@ int pinconf_generic_parse_dt_config(struct device_node *np,
{
unsigned long *cfg;
unsigned int max_cfg, ncfg = 0;
struct fwnode_handle *fwnode;
int ret;
if (!np)
fwnode = of_fwnode_handle(np);
if (!fwnode)
return -EINVAL;
/* allocate a temporary array big enough to hold one of each option */
@ -349,12 +397,12 @@ int pinconf_generic_parse_dt_config(struct device_node *np,
if (!cfg)
return -ENOMEM;
ret = parse_dt_cfg(np, dt_params, ARRAY_SIZE(dt_params), cfg, &ncfg);
ret = parse_fw_cfg(fwnode, dt_params, ARRAY_SIZE(dt_params), cfg, &ncfg);
if (ret)
goto out;
if (pctldev && pctldev->desc->num_custom_params &&
pctldev->desc->custom_params) {
ret = parse_dt_cfg(np, pctldev->desc->custom_params,
ret = parse_fw_cfg(fwnode, pctldev->desc->custom_params,
pctldev->desc->num_custom_params, cfg, &ncfg);
if (ret)
goto out;

1
drivers/pinctrl/pinctrl-amd.c
View File

@ -1274,6 +1274,7 @@ static const struct acpi_device_id amd_gpio_acpi_match[] = {
{ "AMD0030", 0 },
{ "AMDI0030", 0},
{ "AMDI0031", 0},
{ "AMDI0033", 0},
{ },
};
MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);

93
drivers/pinctrl/pinctrl-cy8c95x0.c
View File

@ -72,24 +72,6 @@
#define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) \
(CY8C95X0_VIRTUAL + (x) - CY8C95X0_PORTSEL + (p) * MUXED_STRIDE)
static const struct i2c_device_id cy8c95x0_id[] = {
{ "cy8c9520", 20, },
{ "cy8c9540", 40, },
{ "cy8c9560", 60, },
{ }
};
MODULE_DEVICE_TABLE(i2c, cy8c95x0_id);
#define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio))
static const struct of_device_id cy8c95x0_dt_ids[] = {
{ .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), },
{ .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), },
{ .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), },
{ }
};
MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids);
static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true };
static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = {
@ -144,11 +126,9 @@ static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = {
* @map: Mask used to compensate for Gport2 width
* @nport: Number of Gports in this chip
* @gpio_chip: gpiolib chip
* @driver_data: private driver data
* @dev: struct device
* @pctldev: pin controller device
* @pinctrl_desc: pin controller description
* @name: Chip controller name
* @tpin: Total number of pins
* @gpio_reset: GPIO line handler that can reset the IC
*/
@ -165,11 +145,9 @@ struct cy8c95x0_pinctrl {
DECLARE_BITMAP(map, MAX_LINE);
unsigned int nport;
struct gpio_chip gpio_chip;
unsigned long driver_data;
struct device *dev;
struct pinctrl_dev *pctldev;
struct pinctrl_desc pinctrl_desc;
char name[32];
unsigned int tpin;
struct gpio_desc *gpio_reset;
};
@ -1310,18 +1288,19 @@ static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq)
{
struct gpio_irq_chip *girq = &chip->gpio_chip.irq;
DECLARE_BITMAP(pending_irqs, MAX_LINE);
struct device *dev = chip->dev;
int ret;
mutex_init(&chip->irq_lock);
ret = devm_mutex_init(chip->dev, &chip->irq_lock);
if (ret)
return ret;
bitmap_zero(pending_irqs, MAX_LINE);
/* Read IRQ status register to clear all pending interrupts */
ret = cy8c95x0_irq_pending(chip, pending_irqs);
if (ret) {
dev_err(chip->dev, "failed to clear irq status register\n");
return ret;
}
if (ret)
return dev_err_probe(dev, -EBUSY, "failed to clear irq status register\n");
/* Mask all interrupts */
bitmap_fill(chip->irq_mask, MAX_LINE);
@ -1336,17 +1315,9 @@ static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq)
girq->handler = handle_simple_irq;
girq->threaded = true;
ret = devm_request_threaded_irq(chip->dev, irq,
NULL, cy8c95x0_irq_handler,
IRQF_ONESHOT | IRQF_SHARED,
dev_name(chip->dev), chip);
if (ret) {
dev_err(chip->dev, "failed to request irq %d\n", irq);
return ret;
}
dev_info(chip->dev, "Registered threaded IRQ\n");
return 0;
return devm_request_threaded_irq(dev, irq, NULL, cy8c95x0_irq_handler,
IRQF_ONESHOT | IRQF_SHARED,
dev_name(chip->dev), chip);
}
static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip)
@ -1362,11 +1333,7 @@ static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip)
pd->owner = THIS_MODULE;
chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip);
if (IS_ERR(chip->pctldev))
return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev),
"can't register controller\n");
return 0;
return PTR_ERR_OR_ZERO(chip->pctldev);
}
static int cy8c95x0_detect(struct i2c_client *client,
@ -1384,13 +1351,13 @@ static int cy8c95x0_detect(struct i2c_client *client,
return ret;
switch (ret & GENMASK(7, 4)) {
case 0x20:
name = cy8c95x0_id[0].name;
name = "cy8c9520";
break;
case 0x40:
name = cy8c95x0_id[1].name;
name = "cy8c9540";
break;
case 0x60:
name = cy8c95x0_id[2].name;
name = "cy8c9560";
break;
default:
return -ENODEV;
@ -1408,6 +1375,7 @@ static int cy8c95x0_probe(struct i2c_client *client)
struct cy8c95x0_pinctrl *chip;
struct regmap_config regmap_conf;
struct regmap_range_cfg regmap_range_conf;
unsigned long driver_data;
int ret;
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
@ -1417,26 +1385,21 @@ static int cy8c95x0_probe(struct i2c_client *client)
chip->dev = dev;
/* Set the device type */
chip->driver_data = (uintptr_t)i2c_get_match_data(client);
if (!chip->driver_data)
return -ENODEV;
driver_data = (unsigned long)i2c_get_match_data(client);
chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK;
chip->tpin = driver_data & CY8C95X0_GPIO_MASK;
chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ);
memcpy(&regmap_range_conf, &cy8c95x0_ranges[0], sizeof(regmap_range_conf));
switch (chip->tpin) {
case 20:
strscpy(chip->name, cy8c95x0_id[0].name);
regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE - 1;
break;
case 40:
strscpy(chip->name, cy8c95x0_id[1].name);
regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE - 1;
break;
case 60:
strscpy(chip->name, cy8c95x0_id[2].name);
regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE - 1;
break;
default:
@ -1474,7 +1437,9 @@ static int cy8c95x0_probe(struct i2c_client *client)
bitmap_fill(chip->map, MAX_LINE);
bitmap_clear(chip->map, 20, 4);
mutex_init(&chip->i2c_lock);
ret = devm_mutex_init(dev, &chip->i2c_lock);
if (ret)
return ret;
if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) {
ret = cy8c95x0_acpi_get_irq(&client->dev);
@ -1495,8 +1460,26 @@ static int cy8c95x0_probe(struct i2c_client *client)
return cy8c95x0_setup_gpiochip(chip);
}
static const struct i2c_device_id cy8c95x0_id[] = {
{ "cy8c9520", 20 },
{ "cy8c9540", 40 },
{ "cy8c9560", 60 },
{ }
};
MODULE_DEVICE_TABLE(i2c, cy8c95x0_id);
#define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio))
static const struct of_device_id cy8c95x0_dt_ids[] = {
{ .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20) },
{ .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40) },
{ .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60) },
{ }
};
MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids);
static const struct acpi_device_id cy8c95x0_acpi_ids[] = {
{ "INT3490", 40, },
{ "INT3490", 40 },
{ }
};
MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids);

64
drivers/pinctrl/pinctrl-pic32.c
View File

@ -1696,7 +1696,7 @@ static inline struct pic32_gpio_bank *irqd_to_bank(struct irq_data *d)
}
static inline struct pic32_gpio_bank *pctl_to_bank(struct pic32_pinctrl *pctl,
unsigned pin)
unsigned int pin)
{
return &pctl->gpio_banks[pin / PINS_PER_BANK];
}
@ -1709,7 +1709,7 @@ static int pic32_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
}
static const char *pic32_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
unsigned int group)
{
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
@ -1717,9 +1717,9 @@ static const char *pic32_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
}
static int pic32_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group,
const unsigned **pins,
unsigned *num_pins)
unsigned int group,
const unsigned int **pins,
unsigned int *num_pins)
{
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
@ -1745,7 +1745,7 @@ static int pic32_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
}
static const char *
pic32_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned func)
pic32_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned int func)
{
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
@ -1753,9 +1753,9 @@ pic32_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned func)
}
static int pic32_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
unsigned func,
unsigned int func,
const char * const **groups,
unsigned * const num_groups)
unsigned int * const num_groups)
{
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
@ -1766,7 +1766,7 @@ static int pic32_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
}
static int pic32_pinmux_enable(struct pinctrl_dev *pctldev,
unsigned func, unsigned group)
unsigned int func, unsigned int group)
{
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
const struct pic32_pin_group *pg = &pctl->groups[group];
@ -1795,7 +1795,7 @@ static int pic32_pinmux_enable(struct pinctrl_dev *pctldev,
static int pic32_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
unsigned int offset)
{
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct pic32_gpio_bank *bank = gpiochip_get_data(range->gc);
@ -1810,7 +1810,7 @@ static int pic32_gpio_request_enable(struct pinctrl_dev *pctldev,
}
static int pic32_gpio_direction_input(struct gpio_chip *chip,
unsigned offset)
unsigned int offset)
{
struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
u32 mask = BIT(offset);
@ -1820,7 +1820,7 @@ static int pic32_gpio_direction_input(struct gpio_chip *chip,
return 0;
}
static int pic32_gpio_get(struct gpio_chip *chip, unsigned offset)
static int pic32_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
@ -1842,7 +1842,7 @@ static int pic32_gpio_set(struct gpio_chip *chip, unsigned int offset,
}
static int pic32_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
unsigned int offset, int value)
{
struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
u32 mask = BIT(offset);
@ -1855,7 +1855,7 @@ static int pic32_gpio_direction_output(struct gpio_chip *chip,
static int pic32_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset, bool input)
unsigned int offset, bool input)
{
struct gpio_chip *chip = range->gc;
@ -1876,12 +1876,12 @@ static const struct pinmux_ops pic32_pinmux_ops = {
.gpio_set_direction = pic32_gpio_set_direction,
};
static int pic32_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
static int pic32_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin);
unsigned param = pinconf_to_config_param(*config);
unsigned int param = pinconf_to_config_param(*config);
u32 mask = BIT(pin - bank->gpio_chip.base);
u32 arg;
@ -1917,12 +1917,12 @@ static int pic32_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
return 0;
}
static int pic32_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *configs, unsigned num_configs)
static int pic32_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin);
unsigned param;
unsigned int param;
u32 arg;
unsigned int i;
u32 offset = pin - bank->gpio_chip.base;
@ -1938,7 +1938,7 @@ static int pic32_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
dev_dbg(pctl->dev, " pullup\n");
writel(mask, bank->reg_base +PIC32_SET(CNPU_REG));
writel(mask, bank->reg_base + PIC32_SET(CNPU_REG));
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
dev_dbg(pctl->dev, " pulldown\n");
@ -1987,7 +1987,7 @@ static struct pinctrl_desc pic32_pinctrl_desc = {
.owner = THIS_MODULE,
};
static int pic32_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
static int pic32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
@ -2174,16 +2174,10 @@ static int pic32_pinctrl_probe(struct platform_device *pdev)
if (IS_ERR(pctl->reg_base))
return PTR_ERR(pctl->reg_base);
pctl->clk = devm_clk_get(&pdev->dev, NULL);
pctl->clk = devm_clk_get_enabled(&pdev->dev, NULL);
if (IS_ERR(pctl->clk)) {
ret = PTR_ERR(pctl->clk);
dev_err(&pdev->dev, "clk get failed\n");
return ret;
}
ret = clk_prepare_enable(pctl->clk);
if (ret) {
dev_err(&pdev->dev, "clk enable failed\n");
dev_err(&pdev->dev, "Failed to get and enable clock\n");
return ret;
}
@ -2239,16 +2233,10 @@ static int pic32_gpio_probe(struct platform_device *pdev)
if (irq < 0)
return irq;
bank->clk = devm_clk_get(&pdev->dev, NULL);
bank->clk = devm_clk_get_enabled(&pdev->dev, NULL);
if (IS_ERR(bank->clk)) {
ret = PTR_ERR(bank->clk);
dev_err(&pdev->dev, "clk get failed\n");
return ret;
}
ret = clk_prepare_enable(bank->clk);
if (ret) {
dev_err(&pdev->dev, "clk enable failed\n");
dev_err(&pdev->dev, "Failed to get and enable clock\n");
return ret;
}
@ -2265,7 +2253,7 @@ static int pic32_gpio_probe(struct platform_device *pdev)
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
girq->parents[0] = irq;
ret = gpiochip_add_data(&bank->gpio_chip, bank);
ret = devm_gpiochip_add_data(&pdev->dev, &bank->gpio_chip, bank);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n",
id, ret);

313
drivers/pinctrl/pinctrl-rockchip.c
View File

@ -467,6 +467,22 @@ static const struct pinctrl_ops rockchip_pctrl_ops = {
* Hardware access
*/
static struct rockchip_mux_recalced_data rv1103b_mux_recalced_data[] = {
{
.num = 1,
.pin = 6,
.reg = 0x10024,
.bit = 8,
.mask = 0xf
}, {
.num = 1,
.pin = 7,
.reg = 0x10024,
.bit = 12,
.mask = 0xf
},
};
static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
{
.num = 1,
@ -1172,6 +1188,9 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
else
regmap = info->regmap_base;
if (ctrl->type == RV1103B && bank->bank_num == 2 && pin >= 12)
return 0;
if (ctrl->type == RK3506) {
if (bank->bank_num == 1)
regmap = info->regmap_ioc1;
@ -1298,6 +1317,9 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
else
regmap = info->regmap_base;
if (ctrl->type == RV1103B && bank->bank_num == 2 && pin >= 12)
return 0;
if (ctrl->type == RK3506) {
if (bank->bank_num == 1)
regmap = info->regmap_ioc1;
@ -1495,6 +1517,214 @@ static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
return 0;
}
#define RV1103B_DRV_BITS_PER_PIN 8
#define RV1103B_DRV_PINS_PER_REG 2
#define RV1103B_DRV_GPIO0_A_OFFSET 0x40100
#define RV1103B_DRV_GPIO0_B_OFFSET 0x50110
#define RV1103B_DRV_GPIO1_A01_OFFSET 0x140
#define RV1103B_DRV_GPIO1_A67_OFFSET 0x1014C
#define RV1103B_DRV_GPIO2_OFFSET 0x30180
#define RV1103B_DRV_GPIO2_SARADC_OFFSET 0x3080C
static int rv1103b_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
int ret = 0;
*regmap = info->regmap_base;
switch (bank->bank_num) {
case 0:
if (pin_num < 7)
*reg = RV1103B_DRV_GPIO0_A_OFFSET;
else if (pin_num > 7 && pin_num < 14)
*reg = RV1103B_DRV_GPIO0_B_OFFSET - 0x10;
else
ret = -EINVAL;
break;
case 1:
if (pin_num < 6)
*reg = RV1103B_DRV_GPIO1_A01_OFFSET;
else if (pin_num >= 6 && pin_num < 23)
*reg = RV1103B_DRV_GPIO1_A67_OFFSET - 0xc;
else if (pin_num >= 24 && pin_num < 30)
*reg = RV1103B_DRV_GPIO1_A67_OFFSET - 0xc;
else
ret = -EINVAL;
break;
case 2:
if (pin_num < 12) {
*reg = RV1103B_DRV_GPIO2_OFFSET;
} else if (pin_num >= 16) {
ret = -EINVAL;
} else {
*reg = RV1103B_DRV_GPIO2_SARADC_OFFSET;
*bit = 10;
return 0;
}
break;
default:
ret = -EINVAL;
break;
}
if (ret) {
dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
return ret;
}
*reg += ((pin_num / RV1103B_DRV_PINS_PER_REG) * 4);
*bit = pin_num % RV1103B_DRV_PINS_PER_REG;
*bit *= RV1103B_DRV_BITS_PER_PIN;
return 0;
}
#define RV1103B_PULL_BITS_PER_PIN 2
#define RV1103B_PULL_PINS_PER_REG 8
#define RV1103B_PULL_GPIO0_A_OFFSET 0x40200
#define RV1103B_PULL_GPIO0_B_OFFSET 0x50204
#define RV1103B_PULL_GPIO1_A01_OFFSET 0x210
#define RV1103B_PULL_GPIO1_A67_OFFSET 0x10210
#define RV1103B_PULL_GPIO2_OFFSET 0x30220
#define RV1103B_PULL_GPIO2_SARADC_OFFSET 0x3080C
static int rv1103b_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
int ret = 0;
*regmap = info->regmap_base;
switch (bank->bank_num) {
case 0:
if (pin_num < 7)
*reg = RV1103B_PULL_GPIO0_A_OFFSET;
else if (pin_num > 7 && pin_num < 14)
*reg = RV1103B_PULL_GPIO0_B_OFFSET - 0x4;
else
ret = -EINVAL;
break;
case 1:
if (pin_num < 6)
*reg = RV1103B_PULL_GPIO1_A01_OFFSET;
else if (pin_num >= 6 && pin_num < 23)
*reg = RV1103B_PULL_GPIO1_A67_OFFSET;
else if (pin_num >= 24 && pin_num < 30)
*reg = RV1103B_PULL_GPIO1_A67_OFFSET;
else
ret = -EINVAL;
break;
case 2:
if (pin_num < 12) {
*reg = RV1103B_PULL_GPIO2_OFFSET;
} else if (pin_num >= 16) {
ret = -EINVAL;
} else {
*reg = RV1103B_PULL_GPIO2_SARADC_OFFSET;
*bit = 13;
return 0;
}
break;
default:
ret = -EINVAL;
break;
}
if (ret) {
dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
return ret;
}
*reg += ((pin_num / RV1103B_PULL_PINS_PER_REG) * 4);
*bit = pin_num % RV1103B_PULL_PINS_PER_REG;
*bit *= RV1103B_PULL_BITS_PER_PIN;
return 0;
}
#define RV1103B_SMT_BITS_PER_PIN 1
#define RV1103B_SMT_PINS_PER_REG 8
#define RV1103B_SMT_GPIO0_A_OFFSET 0x40400
#define RV1103B_SMT_GPIO0_B_OFFSET 0x50404
#define RV1103B_SMT_GPIO1_A01_OFFSET 0x410
#define RV1103B_SMT_GPIO1_A67_OFFSET 0x10410
#define RV1103B_SMT_GPIO2_OFFSET 0x30420
#define RV1103B_SMT_GPIO2_SARADC_OFFSET 0x3080C
static int rv1103b_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
int ret = 0;
*regmap = info->regmap_base;
switch (bank->bank_num) {
case 0:
if (pin_num < 7)
*reg = RV1103B_SMT_GPIO0_A_OFFSET;
else if (pin_num > 7 && pin_num < 14)
*reg = RV1103B_SMT_GPIO0_B_OFFSET - 0x4;
else
ret = -EINVAL;
break;
case 1:
if (pin_num < 6)
*reg = RV1103B_SMT_GPIO1_A01_OFFSET;
else if (pin_num >= 6 && pin_num < 23)
*reg = RV1103B_SMT_GPIO1_A67_OFFSET;
else if (pin_num >= 24 && pin_num < 30)
*reg = RV1103B_SMT_GPIO1_A67_OFFSET;
else
ret = -EINVAL;
break;
case 2:
if (pin_num < 12) {
*reg = RV1103B_SMT_GPIO2_OFFSET;
} else if (pin_num >= 16) {
ret = -EINVAL;
} else {
*reg = RV1103B_SMT_GPIO2_SARADC_OFFSET;
*bit = 8;
return 0;
}
break;
default:
ret = -EINVAL;
break;
}
if (ret) {
dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
return ret;
}
*reg += ((pin_num / RV1103B_SMT_PINS_PER_REG) * 4);
*bit = pin_num % RV1103B_SMT_PINS_PER_REG;
*bit *= RV1103B_SMT_BITS_PER_PIN;
return 0;
}
#define RV1108_PULL_PMU_OFFSET 0x10
#define RV1108_PULL_OFFSET 0x110
#define RV1108_PULL_PINS_PER_REG 8
@ -2982,6 +3212,9 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
u8 bit;
int drv_type = bank->drv[pin_num / 8].drv_type;
if (ctrl->type == RV1103B && pin_num >= 12)
drv_type = DRV_TYPE_IO_LEVEL_2_BIT;
ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
if (ret)
return ret;
@ -3043,6 +3276,11 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
if (ret)
return ret;
if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
data = data >> 10;
return data & 0x3;
}
data >>= bit;
data &= (1 << rmask_bits) - 1;
@ -3071,7 +3309,8 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
rmask_bits = RK3588_DRV_BITS_PER_PIN;
ret = strength;
goto config;
} else if (ctrl->type == RK3506 ||
} else if (ctrl->type == RV1103B ||
ctrl->type == RK3506 ||
ctrl->type == RK3528 ||
ctrl->type == RK3562 ||
ctrl->type == RK3568) {
@ -3182,6 +3421,12 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
ret = strength;
}
}
if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
rmask_bits = 2;
ret = strength;
}
/* enable the write to the equivalent lower bits */
data = ((1 << rmask_bits) - 1) << (bit + 16);
rmask = data | (data >> 16);
@ -3236,6 +3481,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
: PIN_CONFIG_BIAS_DISABLE;
case PX30:
case RV1103B:
case RV1108:
case RK3188:
case RK3288:
@ -3251,6 +3497,9 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
pull_type = bank->pull_type[pin_num / 8];
data >>= bit;
data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12)
pull_type = 1;
/*
* In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
* where that pull up value becomes 3.
@ -3297,6 +3546,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
ret = regmap_write(regmap, reg, data);
break;
case PX30:
case RV1103B:
case RV1108:
case RV1126:
case RK3188:
@ -3312,6 +3562,8 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
case RK3576:
case RK3588:
pull_type = bank->pull_type[pin_num / 8];
if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12)
pull_type = 1;
ret = -EINVAL;
for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
i++) {
@ -3417,6 +3669,11 @@ static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
if (ret)
return ret;
if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
data >>= 8;
return data & 0x3;
}
data >>= bit;
switch (ctrl->type) {
case RK3562:
@ -3473,6 +3730,12 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
}
}
if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
data = 0x3 << (bit + 16);
rmask = data | (data >> 16);
data |= ((enable ? 0x3 : 0) << bit);
}
return regmap_update_bits(regmap, reg, rmask, data);
}
@ -3579,6 +3842,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
case RK3066B:
return pull ? false : true;
case PX30:
case RV1103B:
case RV1108:
case RV1126:
case RK3188:
@ -4314,6 +4578,51 @@ static struct rockchip_pin_ctrl px30_pin_ctrl = {
.schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rv1103b_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(0, 32, "gpio0",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
0x40000, 0x50008, 0x50010, 0x50018,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT),
PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
0x20, 0x10028, 0x10030, 0x10038,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT),
PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, "gpio2",
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
IOMUX_WIDTH_4BIT,
0x30040, 0x30048, 0x30050, 0x30058,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT,
DRV_TYPE_IO_LEVEL_8_BIT),
};
static struct rockchip_pin_ctrl rv1103b_pin_ctrl __maybe_unused = {
.pin_banks = rv1103b_pin_banks,
.nr_banks = ARRAY_SIZE(rv1103b_pin_banks),
.label = "RV1103B-GPIO",
.type = RV1103B,
.iomux_recalced = rv1103b_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rv1103b_mux_recalced_data),
.pull_calc_reg = rv1103b_calc_pull_reg_and_bit,
.drv_calc_reg = rv1103b_calc_drv_reg_and_bit,
.schmitt_calc_reg = rv1103b_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rv1108_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
@ -4950,6 +5259,8 @@ static struct rockchip_pin_ctrl rk3588_pin_ctrl = {
static const struct of_device_id rockchip_pinctrl_dt_match[] = {
{ .compatible = "rockchip,px30-pinctrl",
.data = &px30_pin_ctrl },
{ .compatible = "rockchip,rv1103b-pinctrl",
.data = &rv1103b_pin_ctrl },
{ .compatible = "rockchip,rv1108-pinctrl",
.data = &rv1108_pin_ctrl },
{ .compatible = "rockchip,rv1126-pinctrl",

1
drivers/pinctrl/pinctrl-rockchip.h
View File

@ -185,6 +185,7 @@
enum rockchip_pinctrl_type {
PX30,
RV1103B,
RV1108,
RV1126,
RK2928,

6
drivers/pinctrl/pinctrl-single.c
View File

@ -1960,7 +1960,7 @@ static const struct pcs_soc_data pinctrl_single_am654 = {
.irq_status_mask = (1 << 30), /* WKUP_EVT */
};
static const struct pcs_soc_data pinctrl_single_j7200 = {
static const struct pcs_soc_data pinctrl_single_loss_off = {
.flags = PCS_CONTEXT_LOSS_OFF,
};
@ -1972,6 +1972,7 @@ static const struct pcs_soc_data pinconf_single = {
};
static const struct of_device_id pcs_of_match[] = {
{ .compatible = "brcm,bcm7038-padconf", .data = &pinctrl_single_loss_off },
{ .compatible = "marvell,pxa1908-padconf", .data = &pinconf_single },
{ .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
{ .compatible = "ti,am654-padconf", .data = &pinctrl_single_am654 },
@ -1979,7 +1980,8 @@ static const struct of_device_id pcs_of_match[] = {
{ .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
{ .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
{ .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
{ .compatible = "ti,j7200-padconf", .data = &pinctrl_single_j7200 },
{ .compatible = "ti,j7200-padconf", .data = &pinctrl_single_loss_off },
{ .compatible = "ti,am62l-padconf", .data = &pinctrl_single_loss_off },
{ .compatible = "pinctrl-single", .data = &pinctrl_single },
{ .compatible = "pinconf-single", .data = &pinconf_single },
{ },

20
drivers/pinctrl/qcom/Kconfig
View File

@ -60,6 +60,16 @@ config PINCTRL_LPASS_LPI
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SoCs.
config PINCTRL_MILOS_LPASS_LPI
tristate "Qualcomm Technologies Inc Milos LPASS LPI pin controller driver"
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc Milos
platform.
config PINCTRL_SC7280_LPASS_LPI
tristate "Qualcomm Technologies Inc SC7280 and SM8350 LPASS LPI pin controller driver"
depends on ARM64 || COMPILE_TEST
@ -89,6 +99,16 @@ config PINCTRL_SM4250_LPASS_LPI
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SM4250 platform.
config PINCTRL_SDM670_LPASS_LPI
tristate "Qualcomm Technologies Inc SDM670 LPASS LPI pin controller driver"
depends on GPIOLIB
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SDM670 platform.
config PINCTRL_SM6115_LPASS_LPI
tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver"
depends on ARM64 || COMPILE_TEST

28
drivers/pinctrl/qcom/Kconfig.msm
View File

@ -15,6 +15,16 @@ config PINCTRL_APQ8084
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
config PINCTRL_ELIZA
tristate "Qualcomm Technologies Inc Eliza pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)
block found on the Qualcomm Technologies Inc Eliza platform.
Say Y here to compile statically, or M here to compile it as a module.
If unsure, say N.
config PINCTRL_GLYMUR
tristate "Qualcomm Technologies Inc Glymur pin controller driver"
depends on ARM64 || COMPILE_TEST
@ -25,6 +35,16 @@ config PINCTRL_GLYMUR
Say Y here to compile statically, or M here to compile it as a module.
If unsure, say N.
config PINCTRL_HAWI
tristate "Qualcomm Technologies Inc Hawi pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)
block found on the Qualcomm Technologies Inc Hawi platform.
Say Y here to compile statically, or M here to compile it as a module.
If unsure, say N.
config PINCTRL_IPQ4019
tristate "Qualcomm IPQ4019 pin controller driver"
depends on ARM || COMPILE_TEST
@ -48,6 +68,14 @@ config PINCTRL_IPQ8064
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
config PINCTRL_IPQ5210
tristate "Qualcomm Technologies Inc IPQ5210 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc IPQ5210 platform.
config PINCTRL_IPQ5332
tristate "Qualcomm Technologies Inc IPQ5332 pin controller driver"
depends on ARM64 || COMPILE_TEST

5
drivers/pinctrl/qcom/Makefile
View File

@ -3,10 +3,13 @@
obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
obj-$(CONFIG_PINCTRL_ELIZA) += pinctrl-eliza.o
obj-$(CONFIG_PINCTRL_GLYMUR) += pinctrl-glymur.o
obj-$(CONFIG_PINCTRL_HAWI) += pinctrl-hawi.o
obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
obj-$(CONFIG_PINCTRL_IPQ5210) += pinctrl-ipq5210.o
obj-$(CONFIG_PINCTRL_IPQ5332) += pinctrl-ipq5332.o
obj-$(CONFIG_PINCTRL_IPQ5424) += pinctrl-ipq5424.o
obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
@ -33,6 +36,7 @@ obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o
obj-$(CONFIG_PINCTRL_MDM9607) += pinctrl-mdm9607.o
obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o
obj-$(CONFIG_PINCTRL_MILOS) += pinctrl-milos.o
obj-$(CONFIG_PINCTRL_MILOS_LPASS_LPI) += pinctrl-milos-lpass-lpi.o
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
@ -48,6 +52,7 @@ obj-$(CONFIG_PINCTRL_SC8280XP) += pinctrl-sc8280xp.o
obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM660_LPASS_LPI) += pinctrl-sdm660-lpass-lpi.o
obj-$(CONFIG_PINCTRL_SDM670) += pinctrl-sdm670.o
obj-$(CONFIG_PINCTRL_SDM670_LPASS_LPI) += pinctrl-sdm670-lpass-lpi.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o

2
drivers/pinctrl/qcom/pinctrl-apq8084.c
View File

@ -343,7 +343,6 @@ static const unsigned int sdc2_data_pins[] = { 152 };
.io_reg = 0x1004 + 0x10 * id, \
.intr_cfg_reg = 0x1008 + 0x10 * id, \
.intr_status_reg = 0x100c + 0x10 * id, \
.intr_target_reg = 0x1008 + 0x10 * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -370,7 +369,6 @@ static const unsigned int sdc2_data_pins[] = { 152 };
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \

1545
drivers/pinctrl/qcom/pinctrl-eliza.c Normal file
View File

File diff suppressed because it is too large Load Diff

5
drivers/pinctrl/qcom/pinctrl-glymur.c
View File

@ -21,7 +21,6 @@
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -64,7 +63,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
@ -89,7 +87,6 @@
.io_reg = io, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = 3, \
.drv_bit = 0, \
@ -1812,6 +1809,6 @@ static void __exit glymur_tlmm_exit(void)
}
module_exit(glymur_tlmm_exit);
MODULE_DESCRIPTION("QTI GLYMUR TLMM driver");
MODULE_DESCRIPTION("QTI Glymur TLMM driver");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(of, glymur_tlmm_of_match);

1610
drivers/pinctrl/qcom/pinctrl-hawi.c Normal file
View File

File diff suppressed because it is too large Load Diff

1
drivers/pinctrl/qcom/pinctrl-ipq4019.c
View File

@ -242,7 +242,6 @@ DECLARE_QCA_GPIO_PINS(99);
.io_reg = 0x4 + 0x1000 * id, \
.intr_cfg_reg = 0x8 + 0x1000 * id, \
.intr_status_reg = 0xc + 0x1000 * id, \
.intr_target_reg = 0x8 + 0x1000 * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \

1
drivers/pinctrl/qcom/pinctrl-ipq5018.c
View File

@ -32,7 +32,6 @@
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \

897
drivers/pinctrl/qcom/pinctrl-ipq5210.c Normal file
View File

@ -0,0 +1,897 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "pinctrl-msm.h"
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.ctl_reg = REG_SIZE * id, \
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
.oe_bit = 9, \
.in_bit = 0, \
.out_bit = 1, \
.intr_enable_bit = 0, \
.intr_status_bit = 0, \
.intr_target_bit = 5, \
.intr_target_kpss_val = 3, \
.intr_raw_status_bit = 4, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
.intr_detection_width = 2, \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7, \
msm_mux_##f8, \
msm_mux_##f9, \
}, \
.nfuncs = 10, \
}
static const struct pinctrl_pin_desc ipq5210_pins[] = {
PINCTRL_PIN(0, "GPIO_0"),
PINCTRL_PIN(1, "GPIO_1"),
PINCTRL_PIN(2, "GPIO_2"),
PINCTRL_PIN(3, "GPIO_3"),
PINCTRL_PIN(4, "GPIO_4"),
PINCTRL_PIN(5, "GPIO_5"),
PINCTRL_PIN(6, "GPIO_6"),
PINCTRL_PIN(7, "GPIO_7"),
PINCTRL_PIN(8, "GPIO_8"),
PINCTRL_PIN(9, "GPIO_9"),
PINCTRL_PIN(10, "GPIO_10"),
PINCTRL_PIN(11, "GPIO_11"),
PINCTRL_PIN(12, "GPIO_12"),
PINCTRL_PIN(13, "GPIO_13"),
PINCTRL_PIN(14, "GPIO_14"),
PINCTRL_PIN(15, "GPIO_15"),
PINCTRL_PIN(16, "GPIO_16"),
PINCTRL_PIN(17, "GPIO_17"),
PINCTRL_PIN(18, "GPIO_18"),
PINCTRL_PIN(19, "GPIO_19"),
PINCTRL_PIN(20, "GPIO_20"),
PINCTRL_PIN(21, "GPIO_21"),
PINCTRL_PIN(22, "GPIO_22"),
PINCTRL_PIN(23, "GPIO_23"),
PINCTRL_PIN(24, "GPIO_24"),
PINCTRL_PIN(25, "GPIO_25"),
PINCTRL_PIN(26, "GPIO_26"),
PINCTRL_PIN(27, "GPIO_27"),
PINCTRL_PIN(28, "GPIO_28"),
PINCTRL_PIN(29, "GPIO_29"),
PINCTRL_PIN(30, "GPIO_30"),
PINCTRL_PIN(31, "GPIO_31"),
PINCTRL_PIN(32, "GPIO_32"),
PINCTRL_PIN(33, "GPIO_33"),
PINCTRL_PIN(34, "GPIO_34"),
PINCTRL_PIN(35, "GPIO_35"),
PINCTRL_PIN(36, "GPIO_36"),
PINCTRL_PIN(37, "GPIO_37"),
PINCTRL_PIN(38, "GPIO_38"),
PINCTRL_PIN(39, "GPIO_39"),
PINCTRL_PIN(40, "GPIO_40"),
PINCTRL_PIN(41, "GPIO_41"),
PINCTRL_PIN(42, "GPIO_42"),
PINCTRL_PIN(43, "GPIO_43"),
PINCTRL_PIN(44, "GPIO_44"),
PINCTRL_PIN(45, "GPIO_45"),
PINCTRL_PIN(46, "GPIO_46"),
PINCTRL_PIN(47, "GPIO_47"),
PINCTRL_PIN(48, "GPIO_48"),
PINCTRL_PIN(49, "GPIO_49"),
PINCTRL_PIN(50, "GPIO_50"),
PINCTRL_PIN(51, "GPIO_51"),
PINCTRL_PIN(52, "GPIO_52"),
PINCTRL_PIN(53, "GPIO_53"),
};
#define DECLARE_MSM_GPIO_PINS(pin) \
static const unsigned int gpio##pin##_pins[] = { pin }
DECLARE_MSM_GPIO_PINS(0);
DECLARE_MSM_GPIO_PINS(1);
DECLARE_MSM_GPIO_PINS(2);
DECLARE_MSM_GPIO_PINS(3);
DECLARE_MSM_GPIO_PINS(4);
DECLARE_MSM_GPIO_PINS(5);
DECLARE_MSM_GPIO_PINS(6);
DECLARE_MSM_GPIO_PINS(7);
DECLARE_MSM_GPIO_PINS(8);
DECLARE_MSM_GPIO_PINS(9);
DECLARE_MSM_GPIO_PINS(10);
DECLARE_MSM_GPIO_PINS(11);
DECLARE_MSM_GPIO_PINS(12);
DECLARE_MSM_GPIO_PINS(13);
DECLARE_MSM_GPIO_PINS(14);
DECLARE_MSM_GPIO_PINS(15);
DECLARE_MSM_GPIO_PINS(16);
DECLARE_MSM_GPIO_PINS(17);
DECLARE_MSM_GPIO_PINS(18);
DECLARE_MSM_GPIO_PINS(19);
DECLARE_MSM_GPIO_PINS(20);
DECLARE_MSM_GPIO_PINS(21);
DECLARE_MSM_GPIO_PINS(22);
DECLARE_MSM_GPIO_PINS(23);
DECLARE_MSM_GPIO_PINS(24);
DECLARE_MSM_GPIO_PINS(25);
DECLARE_MSM_GPIO_PINS(26);
DECLARE_MSM_GPIO_PINS(27);
DECLARE_MSM_GPIO_PINS(28);
DECLARE_MSM_GPIO_PINS(29);
DECLARE_MSM_GPIO_PINS(30);
DECLARE_MSM_GPIO_PINS(31);
DECLARE_MSM_GPIO_PINS(32);
DECLARE_MSM_GPIO_PINS(33);
DECLARE_MSM_GPIO_PINS(34);
DECLARE_MSM_GPIO_PINS(35);
DECLARE_MSM_GPIO_PINS(36);
DECLARE_MSM_GPIO_PINS(37);
DECLARE_MSM_GPIO_PINS(38);
DECLARE_MSM_GPIO_PINS(39);
DECLARE_MSM_GPIO_PINS(40);
DECLARE_MSM_GPIO_PINS(41);
DECLARE_MSM_GPIO_PINS(42);
DECLARE_MSM_GPIO_PINS(43);
DECLARE_MSM_GPIO_PINS(44);
DECLARE_MSM_GPIO_PINS(45);
DECLARE_MSM_GPIO_PINS(46);
DECLARE_MSM_GPIO_PINS(47);
DECLARE_MSM_GPIO_PINS(48);
DECLARE_MSM_GPIO_PINS(49);
DECLARE_MSM_GPIO_PINS(50);
DECLARE_MSM_GPIO_PINS(51);
DECLARE_MSM_GPIO_PINS(52);
DECLARE_MSM_GPIO_PINS(53);
enum ipq5210_functions {
msm_mux_atest_char_start,
msm_mux_atest_char_status0,
msm_mux_atest_char_status1,
msm_mux_atest_char_status2,
msm_mux_atest_char_status3,
msm_mux_atest_tic_en,
msm_mux_audio_pri,
msm_mux_audio_pri_mclk_out0,
msm_mux_audio_pri_mclk_in0,
msm_mux_audio_pri_mclk_out1,
msm_mux_audio_pri_mclk_in1,
msm_mux_audio_pri_mclk_out2,
msm_mux_audio_pri_mclk_in2,
msm_mux_audio_pri_mclk_out3,
msm_mux_audio_pri_mclk_in3,
msm_mux_audio_sec,
msm_mux_audio_sec_mclk_out0,
msm_mux_audio_sec_mclk_in0,
msm_mux_audio_sec_mclk_out1,
msm_mux_audio_sec_mclk_in1,
msm_mux_audio_sec_mclk_out2,
msm_mux_audio_sec_mclk_in2,
msm_mux_audio_sec_mclk_out3,
msm_mux_audio_sec_mclk_in3,
msm_mux_core_voltage_0,
msm_mux_cri_trng0,
msm_mux_cri_trng1,
msm_mux_cri_trng2,
msm_mux_cri_trng3,
msm_mux_dbg_out_clk,
msm_mux_dg_out,
msm_mux_gcc_plltest_bypassnl,
msm_mux_gcc_plltest_resetn,
msm_mux_gcc_tlmm,
msm_mux_gpio,
msm_mux_led0,
msm_mux_led1,
msm_mux_led2,
msm_mux_mdc_mst,
msm_mux_mdc_slv0,
msm_mux_mdc_slv1,
msm_mux_mdc_slv2,
msm_mux_mdio_mst,
msm_mux_mdio_slv0,
msm_mux_mdio_slv1,
msm_mux_mdio_slv2,
msm_mux_mux_tod_out,
msm_mux_pcie0_clk_req_n,
msm_mux_pcie0_wake,
msm_mux_pcie1_clk_req_n,
msm_mux_pcie1_wake,
msm_mux_pll_test,
msm_mux_pon_active_led,
msm_mux_pon_mux_sel,
msm_mux_pon_rx,
msm_mux_pon_rx_los,
msm_mux_pon_tx,
msm_mux_pon_tx_burst,
msm_mux_pon_tx_dis,
msm_mux_pon_tx_fault,
msm_mux_pon_tx_sd,
msm_mux_gpn_rx_los,
msm_mux_gpn_tx_burst,
msm_mux_gpn_tx_dis,
msm_mux_gpn_tx_fault,
msm_mux_gpn_tx_sd,
msm_mux_pps,
msm_mux_pwm0,
msm_mux_pwm1,
msm_mux_pwm2,
msm_mux_pwm3,
msm_mux_qdss_cti_trig_in_a0,
msm_mux_qdss_cti_trig_in_a1,
msm_mux_qdss_cti_trig_in_b0,
msm_mux_qdss_cti_trig_in_b1,
msm_mux_qdss_cti_trig_out_a0,
msm_mux_qdss_cti_trig_out_a1,
msm_mux_qdss_cti_trig_out_b0,
msm_mux_qdss_cti_trig_out_b1,
msm_mux_qdss_traceclk_a,
msm_mux_qdss_tracectl_a,
msm_mux_qdss_tracedata_a,
msm_mux_qrng_rosc0,
msm_mux_qrng_rosc1,
msm_mux_qrng_rosc2,
msm_mux_qspi_data,
msm_mux_qspi_clk,
msm_mux_qspi_cs_n,
msm_mux_qup_se0,
msm_mux_qup_se1,
msm_mux_qup_se2,
msm_mux_qup_se3,
msm_mux_qup_se4,
msm_mux_qup_se5,
msm_mux_qup_se5_l1,
msm_mux_resout,
msm_mux_rx_los0,
msm_mux_rx_los1,
msm_mux_rx_los2,
msm_mux_sdc_clk,
msm_mux_sdc_cmd,
msm_mux_sdc_data,
msm_mux_tsens_max,
msm_mux__,
};
static const char *const gpio_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6",
"gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13",
"gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20",
"gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27",
"gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34",
"gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
"gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
"gpio49", "gpio50", "gpio51", "gpio52", "gpio53",
};
static const char *const atest_char_start_groups[] = {
"gpio46",
};
static const char *const atest_char_status0_groups[] = {
"gpio34",
};
static const char *const atest_char_status1_groups[] = {
"gpio35",
};
static const char *const atest_char_status2_groups[] = {
"gpio36",
};
static const char *const atest_char_status3_groups[] = {
"gpio37",
};
static const char *const atest_tic_en_groups[] = {
"gpio42",
};
static const char *const audio_pri_groups[] = {
"gpio34", "gpio35", "gpio36", "gpio37",
};
static const char *const audio_pri_mclk_out0_groups[] = {
"gpio12",
};
static const char *const audio_pri_mclk_in0_groups[] = {
"gpio12",
};
static const char *const audio_pri_mclk_out1_groups[] = {
"gpio19",
};
static const char *const audio_pri_mclk_in1_groups[] = {
"gpio19",
};
static const char *const audio_pri_mclk_out2_groups[] = {
"gpio8",
};
static const char *const audio_pri_mclk_in2_groups[] = {
"gpio8",
};
static const char *const audio_pri_mclk_out3_groups[] = {
"gpio13",
};
static const char *const audio_pri_mclk_in3_groups[] = {
"gpio13",
};
static const char *const audio_sec_mclk_out0_groups[] = {
"gpio17",
};
static const char *const audio_sec_mclk_in0_groups[] = {
"gpio17",
};
static const char *const audio_sec_mclk_out1_groups[] = {
"gpio16",
};
static const char *const audio_sec_mclk_in1_groups[] = {
"gpio16",
};
static const char *const audio_sec_mclk_out2_groups[] = {
"gpio49",
};
static const char *const audio_sec_mclk_in2_groups[] = {
"gpio49",
};
static const char *const audio_sec_mclk_out3_groups[] = {
"gpio50",
};
static const char *const audio_sec_mclk_in3_groups[] = {
"gpio50",
};
static const char *const audio_sec_groups[] = {
"gpio40", "gpio41", "gpio42", "gpio43",
};
static const char *const core_voltage_0_groups[] = {
"gpio22",
};
static const char *const cri_trng0_groups[] = {
"gpio6",
};
static const char *const cri_trng1_groups[] = {
"gpio7",
};
static const char *const cri_trng2_groups[] = {
"gpio8",
};
static const char *const cri_trng3_groups[] = {
"gpio9",
};
static const char *const dbg_out_clk_groups[] = {
"gpio23",
};
static const char *const dg_out_groups[] = {
"gpio46",
};
static const char *const gcc_plltest_bypassnl_groups[] = {
"gpio38",
};
static const char *const gcc_plltest_resetn_groups[] = {
"gpio40",
};
static const char *const gcc_tlmm_groups[] = {
"gpio39",
};
static const char *const led0_groups[] = {
"gpio6", "gpio23", "gpio39",
};
static const char *const led1_groups[] = {
"gpio7", "gpio27", "gpio39",
};
static const char *const led2_groups[] = {
"gpio9", "gpio26", "gpio38",
};
static const char *const mdc_mst_groups[] = {
"gpio26",
};
static const char *const mdc_slv0_groups[] = {
"gpio31",
};
static const char *const mdc_slv1_groups[] = {
"gpio20",
};
static const char *const mdc_slv2_groups[] = {
"gpio47",
};
static const char *const mdio_mst_groups[] = {
"gpio27",
};
static const char *const mdio_slv0_groups[] = {
"gpio33",
};
static const char *const mdio_slv1_groups[] = {
"gpio21",
};
static const char *const mdio_slv2_groups[] = {
"gpio49",
};
static const char *const mux_tod_out_groups[] = {
"gpio19",
};
static const char *const pcie0_clk_req_n_groups[] = {
"gpio31",
};
static const char *const pcie0_wake_groups[] = {
"gpio33",
};
static const char *const pcie1_clk_req_n_groups[] = {
"gpio28",
};
static const char *const pcie1_wake_groups[] = {
"gpio30",
};
static const char *const pll_test_groups[] = {
"gpio18",
};
static const char *const pon_active_led_groups[] = {
"gpio11",
};
static const char *const pon_mux_sel_groups[] = {
"gpio45",
};
static const char *const pon_rx_groups[] = {
"gpio48",
};
static const char *const pon_rx_los_groups[] = {
"gpio10",
};
static const char *const pon_tx_groups[] = {
"gpio15",
};
static const char *const pon_tx_burst_groups[] = {
"gpio14",
};
static const char *const pon_tx_dis_groups[] = {
"gpio12",
};
static const char *const pon_tx_fault_groups[] = {
"gpio17",
};
static const char *const pon_tx_sd_groups[] = {
"gpio16",
};
static const char *const gpn_rx_los_groups[] = {
"gpio47",
};
static const char *const gpn_tx_burst_groups[] = {
"gpio51",
};
static const char *const gpn_tx_dis_groups[] = {
"gpio13",
};
static const char *const gpn_tx_fault_groups[] = {
"gpio49",
};
static const char *const gpn_tx_sd_groups[] = {
"gpio50",
};
static const char *const pps_groups[] = {
"gpio18",
};
static const char *const pwm0_groups[] = {
"gpio10", "gpio11", "gpio12", "gpio13",
};
static const char *const pwm1_groups[] = {
"gpio6", "gpio7", "gpio8", "gpio9",
};
static const char *const pwm2_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3",
};
static const char *const pwm3_groups[] = {
"gpio22",
};
static const char *const qdss_cti_trig_in_a0_groups[] = {
"gpio30",
};
static const char *const qdss_cti_trig_in_a1_groups[] = {
"gpio33",
};
static const char *const qdss_cti_trig_in_b0_groups[] = {
"gpio34",
};
static const char *const qdss_cti_trig_in_b1_groups[] = {
"gpio37",
};
static const char *const qdss_cti_trig_out_a0_groups[] = {
"gpio28",
};
static const char *const qdss_cti_trig_out_a1_groups[] = {
"gpio31",
};
static const char *const qdss_cti_trig_out_b0_groups[] = {
"gpio16",
};
static const char *const qdss_cti_trig_out_b1_groups[] = {
"gpio35",
};
static const char *const qdss_traceclk_a_groups[] = {
"gpio23",
};
static const char *const qdss_tracectl_a_groups[] = {
"gpio26",
};
static const char *const qdss_tracedata_a_groups[] = {
"gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
"gpio12", "gpio13", "gpio14", "gpio15", "gpio20", "gpio21",
"gpio38", "gpio39", "gpio40", "gpio41",
};
static const char *const qrng_rosc0_groups[] = {
"gpio12",
};
static const char *const qrng_rosc1_groups[] = {
"gpio13",
};
static const char *const qrng_rosc2_groups[] = {
"gpio14",
};
static const char *const qspi_data_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3",
};
static const char *const qspi_clk_groups[] = {
"gpio5",
};
static const char *const qspi_cs_n_groups[] = {
"gpio4",
};
static const char *const qup_se0_groups[] = {
"gpio6", "gpio7", "gpio8", "gpio9", "gpio14", "gpio15",
};
static const char *const qup_se1_groups[] = {
"gpio28", "gpio30", "gpio38", "gpio39",
};
static const char *const qup_se2_groups[] = {
"gpio12", "gpio13", "gpio20", "gpio21", "gpio52", "gpio53",
};
static const char *const qup_se3_groups[] = {
"gpio10", "gpio11", "gpio22", "gpio23",
};
static const char *const qup_se4_groups[] = {
"gpio40", "gpio41", "gpio42", "gpio43", "gpio52", "gpio53",
};
static const char *const qup_se5_groups[] = {
"gpio47", "gpio48", "gpio49", "gpio50", "gpio51", "gpio52",
};
static const char *const qup_se5_l1_groups[] = {
"gpio52", "gpio53",
};
static const char *const resout_groups[] = {
"gpio44",
};
static const char *const rx_los0_groups[] = {
"gpio37", "gpio42",
};
static const char *const rx_los1_groups[] = {
"gpio36", "gpio41",
};
static const char *const rx_los2_groups[] = {
"gpio35", "gpio40",
};
static const char *const sdc_clk_groups[] = {
"gpio5",
};
static const char *const sdc_cmd_groups[] = {
"gpio4",
};
static const char *const sdc_data_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3",
};
static const char *const tsens_max_groups[] = {
"gpio20",
};
static const struct pinfunction ipq5210_functions[] = {
MSM_PIN_FUNCTION(atest_char_start),
MSM_PIN_FUNCTION(atest_char_status0),
MSM_PIN_FUNCTION(atest_char_status1),
MSM_PIN_FUNCTION(atest_char_status2),
MSM_PIN_FUNCTION(atest_char_status3),
MSM_PIN_FUNCTION(atest_tic_en),
MSM_PIN_FUNCTION(audio_pri),
MSM_PIN_FUNCTION(audio_pri_mclk_out0),
MSM_PIN_FUNCTION(audio_pri_mclk_in0),
MSM_PIN_FUNCTION(audio_pri_mclk_out1),
MSM_PIN_FUNCTION(audio_pri_mclk_in1),
MSM_PIN_FUNCTION(audio_pri_mclk_out2),
MSM_PIN_FUNCTION(audio_pri_mclk_in2),
MSM_PIN_FUNCTION(audio_pri_mclk_out3),
MSM_PIN_FUNCTION(audio_pri_mclk_in3),
MSM_PIN_FUNCTION(audio_sec),
MSM_PIN_FUNCTION(audio_sec_mclk_out0),
MSM_PIN_FUNCTION(audio_sec_mclk_in0),
MSM_PIN_FUNCTION(audio_sec_mclk_out1),
MSM_PIN_FUNCTION(audio_sec_mclk_in1),
MSM_PIN_FUNCTION(audio_sec_mclk_out2),
MSM_PIN_FUNCTION(audio_sec_mclk_in2),
MSM_PIN_FUNCTION(audio_sec_mclk_out3),
MSM_PIN_FUNCTION(audio_sec_mclk_in3),
MSM_PIN_FUNCTION(core_voltage_0),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(cri_trng2),
MSM_PIN_FUNCTION(cri_trng3),
MSM_PIN_FUNCTION(dbg_out_clk),
MSM_PIN_FUNCTION(dg_out),
MSM_PIN_FUNCTION(gcc_plltest_bypassnl),
MSM_PIN_FUNCTION(gcc_plltest_resetn),
MSM_PIN_FUNCTION(gcc_tlmm),
MSM_GPIO_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(led0),
MSM_PIN_FUNCTION(led1),
MSM_PIN_FUNCTION(led2),
MSM_PIN_FUNCTION(mdc_mst),
MSM_PIN_FUNCTION(mdc_slv0),
MSM_PIN_FUNCTION(mdc_slv1),
MSM_PIN_FUNCTION(mdc_slv2),
MSM_PIN_FUNCTION(mdio_mst),
MSM_PIN_FUNCTION(mdio_slv0),
MSM_PIN_FUNCTION(mdio_slv1),
MSM_PIN_FUNCTION(mdio_slv2),
MSM_PIN_FUNCTION(mux_tod_out),
MSM_PIN_FUNCTION(pcie0_clk_req_n),
MSM_PIN_FUNCTION(pcie0_wake),
MSM_PIN_FUNCTION(pcie1_clk_req_n),
MSM_PIN_FUNCTION(pcie1_wake),
MSM_PIN_FUNCTION(pll_test),
MSM_PIN_FUNCTION(pon_active_led),
MSM_PIN_FUNCTION(pon_mux_sel),
MSM_PIN_FUNCTION(pon_rx),
MSM_PIN_FUNCTION(pon_rx_los),
MSM_PIN_FUNCTION(pon_tx),
MSM_PIN_FUNCTION(pon_tx_burst),
MSM_PIN_FUNCTION(pon_tx_dis),
MSM_PIN_FUNCTION(pon_tx_fault),
MSM_PIN_FUNCTION(pon_tx_sd),
MSM_PIN_FUNCTION(gpn_rx_los),
MSM_PIN_FUNCTION(gpn_tx_burst),
MSM_PIN_FUNCTION(gpn_tx_dis),
MSM_PIN_FUNCTION(gpn_tx_fault),
MSM_PIN_FUNCTION(gpn_tx_sd),
MSM_PIN_FUNCTION(pps),
MSM_PIN_FUNCTION(pwm0),
MSM_PIN_FUNCTION(pwm1),
MSM_PIN_FUNCTION(pwm2),
MSM_PIN_FUNCTION(pwm3),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
MSM_PIN_FUNCTION(qdss_traceclk_a),
MSM_PIN_FUNCTION(qdss_tracectl_a),
MSM_PIN_FUNCTION(qdss_tracedata_a),
MSM_PIN_FUNCTION(qrng_rosc0),
MSM_PIN_FUNCTION(qrng_rosc1),
MSM_PIN_FUNCTION(qrng_rosc2),
MSM_PIN_FUNCTION(qspi_data),
MSM_PIN_FUNCTION(qspi_clk),
MSM_PIN_FUNCTION(qspi_cs_n),
MSM_PIN_FUNCTION(qup_se0),
MSM_PIN_FUNCTION(qup_se1),
MSM_PIN_FUNCTION(qup_se2),
MSM_PIN_FUNCTION(qup_se3),
MSM_PIN_FUNCTION(qup_se4),
MSM_PIN_FUNCTION(qup_se5),
MSM_PIN_FUNCTION(qup_se5_l1),
MSM_PIN_FUNCTION(resout),
MSM_PIN_FUNCTION(rx_los0),
MSM_PIN_FUNCTION(rx_los1),
MSM_PIN_FUNCTION(rx_los2),
MSM_PIN_FUNCTION(sdc_clk),
MSM_PIN_FUNCTION(sdc_cmd),
MSM_PIN_FUNCTION(sdc_data),
MSM_PIN_FUNCTION(tsens_max),
};
static const struct msm_pingroup ipq5210_groups[] = {
[0] = PINGROUP(0, sdc_data, qspi_data, pwm2, _, _, _, _, _, _),
[1] = PINGROUP(1, sdc_data, qspi_data, pwm2, _, _, _, _, _, _),
[2] = PINGROUP(2, sdc_data, qspi_data, pwm2, _, _, _, _, _, _),
[3] = PINGROUP(3, sdc_data, qspi_data, pwm2, _, _, _, _, _, _),
[4] = PINGROUP(4, sdc_cmd, qspi_cs_n, _, _, _, _, _, _, _),
[5] = PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _),
[6] = PINGROUP(6, qup_se0, led0, pwm1, _, cri_trng0, qdss_tracedata_a, _, _, _),
[7] = PINGROUP(7, qup_se0, led1, pwm1, _, cri_trng1, qdss_tracedata_a, _, _, _),
[8] = PINGROUP(8, qup_se0, pwm1, audio_pri_mclk_out2, audio_pri_mclk_in2, _, cri_trng2, qdss_tracedata_a, _, _),
[9] = PINGROUP(9, qup_se0, led2, pwm1, _, cri_trng3, qdss_tracedata_a, _, _, _),
[10] = PINGROUP(10, pon_rx_los, qup_se3, pwm0, _, _, qdss_tracedata_a, _, _, _),
[11] = PINGROUP(11, pon_active_led, qup_se3, pwm0, _, _, qdss_tracedata_a, _, _, _),
[12] = PINGROUP(12, pon_tx_dis, qup_se2, pwm0, audio_pri_mclk_out0, audio_pri_mclk_in0, _, qrng_rosc0, qdss_tracedata_a, _),
[13] = PINGROUP(13, gpn_tx_dis, qup_se2, pwm0, audio_pri_mclk_out3, audio_pri_mclk_in3, _, qrng_rosc1, qdss_tracedata_a, _),
[14] = PINGROUP(14, pon_tx_burst, qup_se0, _, qrng_rosc2, qdss_tracedata_a, _, _, _, _),
[15] = PINGROUP(15, pon_tx, qup_se0, _, qdss_tracedata_a, _, _, _, _, _),
[16] = PINGROUP(16, pon_tx_sd, audio_sec_mclk_out1, audio_sec_mclk_in1, qdss_cti_trig_out_b0, _, _, _, _, _),
[17] = PINGROUP(17, pon_tx_fault, audio_sec_mclk_out0, audio_sec_mclk_in0, _, _, _, _, _, _),
[18] = PINGROUP(18, pps, pll_test, _, _, _, _, _, _, _),
[19] = PINGROUP(19, mux_tod_out, audio_pri_mclk_out1, audio_pri_mclk_in1, _, _, _, _, _, _),
[20] = PINGROUP(20, qup_se2, mdc_slv1, tsens_max, qdss_tracedata_a, _, _, _, _, _),
[21] = PINGROUP(21, qup_se2, mdio_slv1, qdss_tracedata_a, _, _, _, _, _, _),
[22] = PINGROUP(22, core_voltage_0, qup_se3, pwm3, _, _, _, _, _, _),
[23] = PINGROUP(23, led0, qup_se3, dbg_out_clk, qdss_traceclk_a, _, _, _, _, _),
[24] = PINGROUP(24, _, _, _, _, _, _, _, _, _),
[25] = PINGROUP(25, _, _, _, _, _, _, _, _, _),
[26] = PINGROUP(26, mdc_mst, led2, _, qdss_tracectl_a, _, _, _, _, _),
[27] = PINGROUP(27, mdio_mst, led1, _, _, _, _, _, _, _),
[28] = PINGROUP(28, pcie1_clk_req_n, qup_se1, _, _, qdss_cti_trig_out_a0, _, _, _, _),
[29] = PINGROUP(29, _, _, _, _, _, _, _, _, _),
[30] = PINGROUP(30, pcie1_wake, qup_se1, _, _, qdss_cti_trig_in_a0, _, _, _, _),
[31] = PINGROUP(31, pcie0_clk_req_n, mdc_slv0, _, qdss_cti_trig_out_a1, _, _, _, _, _),
[32] = PINGROUP(32, _, _, _, _, _, _, _, _, _),
[33] = PINGROUP(33, pcie0_wake, mdio_slv0, qdss_cti_trig_in_a1, _, _, _, _, _, _),
[34] = PINGROUP(34, audio_pri, atest_char_status0, qdss_cti_trig_in_b0, _, _, _, _, _, _),
[35] = PINGROUP(35, audio_pri, rx_los2, atest_char_status1, qdss_cti_trig_out_b1, _, _, _, _, _),
[36] = PINGROUP(36, audio_pri, _, rx_los1, atest_char_status2, _, _, _, _, _),
[37] = PINGROUP(37, audio_pri, rx_los0, atest_char_status3, _, qdss_cti_trig_in_b1, _, _, _, _),
[38] = PINGROUP(38, qup_se1, led2, gcc_plltest_bypassnl, qdss_tracedata_a, _, _, _, _, _),
[39] = PINGROUP(39, qup_se1, led1, led0, gcc_tlmm, qdss_tracedata_a, _, _, _, _),
[40] = PINGROUP(40, qup_se4, rx_los2, audio_sec, gcc_plltest_resetn, qdss_tracedata_a, _, _, _, _),
[41] = PINGROUP(41, qup_se4, rx_los1, audio_sec, qdss_tracedata_a, _, _, _, _, _),
[42] = PINGROUP(42, qup_se4, rx_los0, audio_sec, atest_tic_en, _, _, _, _, _),
[43] = PINGROUP(43, qup_se4, audio_sec, _, _, _, _, _, _, _),
[44] = PINGROUP(44, resout, _, _, _, _, _, _, _, _),
[45] = PINGROUP(45, pon_mux_sel, _, _, _, _, _, _, _, _),
[46] = PINGROUP(46, dg_out, atest_char_start, _, _, _, _, _, _, _),
[47] = PINGROUP(47, gpn_rx_los, mdc_slv2, qup_se5, _, _, _, _, _, _),
[48] = PINGROUP(48, pon_rx, qup_se5, _, _, _, _, _, _, _),
[49] = PINGROUP(49, gpn_tx_fault, mdio_slv2, qup_se5, audio_sec_mclk_out2, audio_sec_mclk_in2, _, _, _, _),
[50] = PINGROUP(50, gpn_tx_sd, qup_se5, audio_sec_mclk_out3, audio_sec_mclk_in3, _, _, _, _, _),
[51] = PINGROUP(51, gpn_tx_burst, qup_se5, _, _, _, _, _, _, _),
[52] = PINGROUP(52, qup_se2, qup_se5, qup_se4, qup_se5_l1, _, _, _, _, _),
[53] = PINGROUP(53, qup_se2, qup_se4, qup_se5_l1, _, _, _, _, _, _),
};
static const struct msm_pinctrl_soc_data ipq5210_tlmm = {
.pins = ipq5210_pins,
.npins = ARRAY_SIZE(ipq5210_pins),
.functions = ipq5210_functions,
.nfunctions = ARRAY_SIZE(ipq5210_functions),
.groups = ipq5210_groups,
.ngroups = ARRAY_SIZE(ipq5210_groups),
.ngpios = 54,
};
static const struct of_device_id ipq5210_tlmm_of_match[] = {
{ .compatible = "qcom,ipq5210-tlmm", },
{ },
};
static int ipq5210_tlmm_probe(struct platform_device *pdev)
{
return msm_pinctrl_probe(pdev, &ipq5210_tlmm);
}
static struct platform_driver ipq5210_tlmm_driver = {
.driver = {
.name = "ipq5210-tlmm",
.of_match_table = ipq5210_tlmm_of_match,
},
.probe = ipq5210_tlmm_probe,
};
static int __init ipq5210_tlmm_init(void)
{
return platform_driver_register(&ipq5210_tlmm_driver);
}
arch_initcall(ipq5210_tlmm_init);
static void __exit ipq5210_tlmm_exit(void)
{
platform_driver_unregister(&ipq5210_tlmm_driver);
}
module_exit(ipq5210_tlmm_exit);
MODULE_DESCRIPTION("QTI IPQ5210 TLMM driver");
MODULE_LICENSE("GPL");

1
drivers/pinctrl/qcom/pinctrl-ipq5332.c
View File

@ -32,7 +32,6 @@
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \

1
drivers/pinctrl/qcom/pinctrl-ipq5424.c
View File

@ -33,7 +33,6 @@
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \

1
drivers/pinctrl/qcom/pinctrl-ipq6018.c
View File

@ -32,7 +32,6 @@
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \

1
drivers/pinctrl/qcom/pinctrl-ipq8074.c
View File

@ -32,7 +32,6 @@
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \

1
drivers/pinctrl/qcom/pinctrl-ipq9574.c
View File

@ -32,7 +32,6 @@
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \

3
drivers/pinctrl/qcom/pinctrl-kaanapali.c
View File

@ -34,7 +34,6 @@
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -64,7 +63,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
@ -89,7 +87,6 @@
.io_reg = io, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = 3, \
.drv_bit = 0, \

2
drivers/pinctrl/qcom/pinctrl-mdm9607.c
View File

@ -225,7 +225,6 @@ static const unsigned int qdsd_data3_pins[] = { 91 };
.io_reg = 0x4 + 0x1000 * id, \
.intr_cfg_reg = 0x8 + 0x1000 * id, \
.intr_status_reg = 0xc + 0x1000 * id, \
.intr_target_reg = 0x8 + 0x1000 * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -251,7 +250,6 @@ static const unsigned int qdsd_data3_pins[] = { 91 };
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \

217
drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c Normal file
View File

@ -0,0 +1,217 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022-2023 Linaro Ltd.
* Copyright (c) 2026 Luca Weiss <luca.weiss@fairphone.com>
*/
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "pinctrl-lpass-lpi.h"
enum lpass_lpi_functions {
LPI_MUX_dmic1_clk,
LPI_MUX_dmic1_data,
LPI_MUX_dmic2_clk,
LPI_MUX_dmic2_data,
LPI_MUX_dmic3_clk,
LPI_MUX_dmic3_data,
LPI_MUX_dmic4_clk,
LPI_MUX_dmic4_data,
LPI_MUX_i2s0_clk,
LPI_MUX_i2s0_data,
LPI_MUX_i2s0_ws,
LPI_MUX_i2s1_clk,
LPI_MUX_i2s1_data,
LPI_MUX_i2s1_ws,
LPI_MUX_i2s2_clk,
LPI_MUX_i2s2_data,
LPI_MUX_i2s2_ws,
LPI_MUX_i2s3_clk,
LPI_MUX_i2s3_data,
LPI_MUX_i2s3_ws,
LPI_MUX_qca_swr_clk,
LPI_MUX_qca_swr_data,
LPI_MUX_slimbus_clk,
LPI_MUX_slimbus_data,
LPI_MUX_swr_rx_clk,
LPI_MUX_swr_rx_data,
LPI_MUX_swr_tx_clk,
LPI_MUX_swr_tx_data,
LPI_MUX_wsa_swr_clk,
LPI_MUX_wsa_swr_data,
LPI_MUX_ext_mclk1_a,
LPI_MUX_ext_mclk1_b,
LPI_MUX_ext_mclk1_c,
LPI_MUX_ext_mclk1_d,
LPI_MUX_ext_mclk1_e,
LPI_MUX_gpio,
LPI_MUX__,
};
static const struct pinctrl_pin_desc milos_lpi_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
PINCTRL_PIN(14, "gpio14"),
PINCTRL_PIN(15, "gpio15"),
PINCTRL_PIN(16, "gpio16"),
PINCTRL_PIN(17, "gpio17"),
PINCTRL_PIN(18, "gpio18"),
PINCTRL_PIN(19, "gpio19"),
PINCTRL_PIN(20, "gpio20"),
PINCTRL_PIN(21, "gpio21"),
PINCTRL_PIN(22, "gpio22"),
};
static const char * const gpio_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
"gpio22",
};
static const char * const dmic1_clk_groups[] = { "gpio6" };
static const char * const dmic1_data_groups[] = { "gpio7" };
static const char * const dmic2_clk_groups[] = { "gpio8" };
static const char * const dmic2_data_groups[] = { "gpio9" };
static const char * const dmic3_clk_groups[] = { "gpio12" };
static const char * const dmic3_data_groups[] = { "gpio13" };
static const char * const dmic4_clk_groups[] = { "gpio21" };
static const char * const dmic4_data_groups[] = { "gpio22" };
static const char * const i2s0_clk_groups[] = { "gpio0" };
static const char * const i2s0_ws_groups[] = { "gpio1" };
static const char * const i2s0_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" };
static const char * const i2s1_clk_groups[] = { "gpio6" };
static const char * const i2s1_ws_groups[] = { "gpio7" };
static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
static const char * const i2s2_clk_groups[] = { "gpio10" };
static const char * const i2s2_ws_groups[] = { "gpio11" };
static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" };
static const char * const i2s3_clk_groups[] = { "gpio19" };
static const char * const i2s3_ws_groups[] = { "gpio20" };
static const char * const i2s3_data_groups[] = { "gpio21", "gpio22" };
static const char * const qca_swr_clk_groups[] = { "gpio19" };
static const char * const qca_swr_data_groups[] = { "gpio20" };
static const char * const slimbus_clk_groups[] = { "gpio19" };
static const char * const slimbus_data_groups[] = { "gpio20" };
static const char * const swr_rx_clk_groups[] = { "gpio3" };
static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
static const char * const swr_tx_clk_groups[] = { "gpio0" };
static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" };
static const char * const wsa_swr_clk_groups[] = { "gpio10" };
static const char * const wsa_swr_data_groups[] = { "gpio11" };
static const char * const ext_mclk1_a_groups[] = { "gpio13" };
static const char * const ext_mclk1_b_groups[] = { "gpio9" };
static const char * const ext_mclk1_c_groups[] = { "gpio5" };
static const char * const ext_mclk1_d_groups[] = { "gpio14" };
static const char * const ext_mclk1_e_groups[] = { "gpio22" };
static const struct lpi_pingroup milos_groups[] = {
LPI_PINGROUP(0, 0, swr_tx_clk, i2s0_clk, _, _),
LPI_PINGROUP(1, 2, swr_tx_data, i2s0_ws, _, _),
LPI_PINGROUP(2, 4, swr_tx_data, i2s0_data, _, _),
LPI_PINGROUP(3, 8, swr_rx_clk, i2s0_data, _, _),
LPI_PINGROUP(4, 10, swr_rx_data, i2s0_data, _, _),
LPI_PINGROUP(5, 12, swr_rx_data, ext_mclk1_c, i2s0_data, _),
LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _),
LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _),
LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _),
LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, ext_mclk1_b, _),
LPI_PINGROUP(10, 16, wsa_swr_clk, i2s2_clk, _, _),
LPI_PINGROUP(11, 18, wsa_swr_data, i2s2_ws, _, _),
LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _),
LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, ext_mclk1_a, _),
LPI_PINGROUP(14, 6, swr_tx_data, ext_mclk1_d, _, _),
/* gpio15 - gpio18 do not really exist */
LPI_PINGROUP(15, 20, _, _, _, _),
LPI_PINGROUP(16, 22, _, _, _, _),
LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(18, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(19, LPI_NO_SLEW, i2s3_clk, slimbus_clk, qca_swr_clk, _),
LPI_PINGROUP(20, LPI_NO_SLEW, i2s3_ws, slimbus_data, qca_swr_data, _),
LPI_PINGROUP(21, LPI_NO_SLEW, i2s3_data, dmic4_clk, _, _),
LPI_PINGROUP(22, LPI_NO_SLEW, i2s3_data, dmic4_data, ext_mclk1_e, _),
};
static const struct lpi_function milos_functions[] = {
LPI_FUNCTION(gpio),
LPI_FUNCTION(dmic1_clk),
LPI_FUNCTION(dmic1_data),
LPI_FUNCTION(dmic2_clk),
LPI_FUNCTION(dmic2_data),
LPI_FUNCTION(dmic3_clk),
LPI_FUNCTION(dmic3_data),
LPI_FUNCTION(dmic4_clk),
LPI_FUNCTION(dmic4_data),
LPI_FUNCTION(i2s0_clk),
LPI_FUNCTION(i2s0_data),
LPI_FUNCTION(i2s0_ws),
LPI_FUNCTION(i2s1_clk),
LPI_FUNCTION(i2s1_data),
LPI_FUNCTION(i2s1_ws),
LPI_FUNCTION(i2s2_clk),
LPI_FUNCTION(i2s2_data),
LPI_FUNCTION(i2s2_ws),
LPI_FUNCTION(i2s3_clk),
LPI_FUNCTION(i2s3_data),
LPI_FUNCTION(i2s3_ws),
LPI_FUNCTION(qca_swr_clk),
LPI_FUNCTION(qca_swr_data),
LPI_FUNCTION(slimbus_clk),
LPI_FUNCTION(slimbus_data),
LPI_FUNCTION(swr_rx_clk),
LPI_FUNCTION(swr_rx_data),
LPI_FUNCTION(swr_tx_clk),
LPI_FUNCTION(swr_tx_data),
LPI_FUNCTION(wsa_swr_clk),
LPI_FUNCTION(wsa_swr_data),
LPI_FUNCTION(ext_mclk1_a),
LPI_FUNCTION(ext_mclk1_b),
LPI_FUNCTION(ext_mclk1_c),
LPI_FUNCTION(ext_mclk1_d),
LPI_FUNCTION(ext_mclk1_e),
};
static const struct lpi_pinctrl_variant_data milos_lpi_data = {
.pins = milos_lpi_pins,
.npins = ARRAY_SIZE(milos_lpi_pins),
.groups = milos_groups,
.ngroups = ARRAY_SIZE(milos_groups),
.functions = milos_functions,
.nfunctions = ARRAY_SIZE(milos_functions),
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
{
.compatible = "qcom,milos-lpass-lpi-pinctrl",
.data = &milos_lpi_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
static struct platform_driver lpi_pinctrl_driver = {
.driver = {
.name = "qcom-milos-lpass-lpi-pinctrl",
.of_match_table = lpi_pinctrl_of_match,
},
.probe = lpi_pinctrl_probe,
.remove = lpi_pinctrl_remove,
};
module_platform_driver(lpi_pinctrl_driver);
MODULE_DESCRIPTION("Qualcomm Milos LPI GPIO pin control driver");
MODULE_LICENSE("GPL");

3
drivers/pinctrl/qcom/pinctrl-milos.c
View File

@ -36,7 +36,6 @@
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -67,7 +66,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
@ -92,7 +90,6 @@
.io_reg = io, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = 3, \
.drv_bit = 0, \

20
drivers/pinctrl/qcom/pinctrl-msm.c
View File

@ -98,7 +98,22 @@ MSM_ACCESSOR(ctl)
MSM_ACCESSOR(io)
MSM_ACCESSOR(intr_cfg)
MSM_ACCESSOR(intr_status)
MSM_ACCESSOR(intr_target)
static u32 msm_readl_intr_target(struct msm_pinctrl *pctrl,
const struct msm_pingroup *g)
{
u32 reg = g->intr_target_reg ? g->intr_target_reg : g->intr_cfg_reg;
return readl(pctrl->regs[g->tile] + reg);
}
static void msm_writel_intr_target(u32 val, struct msm_pinctrl *pctrl,
const struct msm_pingroup *g)
{
u32 reg = g->intr_target_reg ? g->intr_target_reg : g->intr_cfg_reg;
writel(val, pctrl->regs[g->tile] + reg);
}
static void msm_ack_intr_status(struct msm_pinctrl *pctrl,
const struct msm_pingroup *g)
@ -1078,7 +1093,8 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
intr_target_mask = GENMASK(g->intr_target_width - 1, 0);
if (pctrl->intr_target_use_scm) {
u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
u32 reg = g->intr_target_reg ? g->intr_target_reg : g->intr_cfg_reg;
u32 addr = pctrl->phys_base[0] + reg;
int ret;
qcom_scm_io_readl(addr, &val);

6
drivers/pinctrl/qcom/pinctrl-msm.h
View File

@ -52,7 +52,11 @@ struct pinctrl_pin_desc;
* @intr_cfg_reg: Offset of the register holding interrupt configuration bits.
* @intr_status_reg: Offset of the register holding the status bits for this group.
* @intr_target_reg: Offset of the register specifying routing of the interrupts
* from this group.
* from this group. On most SoCs this register is the same as
* @intr_cfg_reg; leaving this field as zero causes the driver
* to fall back to @intr_cfg_reg automatically. Only set this
* explicitly on older SoCs where the interrupt target routing
* lives in a separate register (e.g. APQ8064, MSM8960).
* @mux_bit: Offset in @ctl_reg for the pinmux function selection.
* @pull_bit: Offset in @ctl_reg for the bias configuration.
* @drv_bit: Offset in @ctl_reg for the drive strength configuration.

2
drivers/pinctrl/qcom/pinctrl-msm8226.c
View File

@ -282,7 +282,6 @@ static const unsigned int sdc2_data_pins[] = { 122 };
.io_reg = 0x1004 + 0x10 * id, \
.intr_cfg_reg = 0x1008 + 0x10 * id, \
.intr_status_reg = 0x100c + 0x10 * id, \
.intr_target_reg = 0x1008 + 0x10 * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -308,7 +307,6 @@ static const unsigned int sdc2_data_pins[] = { 122 };
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \

2
drivers/pinctrl/qcom/pinctrl-msm8909.c
View File

@ -33,7 +33,6 @@
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -59,7 +58,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \

2
drivers/pinctrl/qcom/pinctrl-msm8916.c
View File

@ -307,7 +307,6 @@ static const unsigned int qdsd_data3_pins[] = { 133 };
.io_reg = 0x4 + 0x1000 * id, \
.intr_cfg_reg = 0x8 + 0x1000 * id, \
.intr_status_reg = 0xc + 0x1000 * id, \
.intr_target_reg = 0x8 + 0x1000 * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -333,7 +332,6 @@ static const unsigned int qdsd_data3_pins[] = { 133 };
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \

2
drivers/pinctrl/qcom/pinctrl-msm8917.c
View File

@ -333,7 +333,6 @@ static const unsigned int qdsd_data3_pins[] = { 146 };
.io_reg = 0x4 + 0x1000 * id, \
.intr_cfg_reg = 0x8 + 0x1000 * id, \
.intr_status_reg = 0xc + 0x1000 * id, \
.intr_target_reg = 0x8 + 0x1000 * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -359,7 +358,6 @@ static const unsigned int qdsd_data3_pins[] = { 146 };
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \

2
drivers/pinctrl/qcom/pinctrl-msm8953.c
View File

@ -29,7 +29,6 @@
.io_reg = 0x4 + 0x1000 * id, \
.intr_cfg_reg = 0x8 + 0x1000 * id, \
.intr_status_reg = 0xc + 0x1000 * id, \
.intr_target_reg = 0x8 + 0x1000 * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -55,7 +54,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \

2
drivers/pinctrl/qcom/pinctrl-msm8976.c
View File

@ -35,7 +35,6 @@
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -61,7 +60,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \

2
drivers/pinctrl/qcom/pinctrl-msm8994.c
View File

@ -33,7 +33,6 @@
.io_reg = 0x1004 + 0x10 * id, \
.intr_cfg_reg = 0x1008 + 0x10 * id, \
.intr_status_reg = 0x100c + 0x10 * id, \
.intr_target_reg = 0x1008 + 0x10 * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -59,7 +58,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \

2
drivers/pinctrl/qcom/pinctrl-msm8996.c
View File

@ -33,7 +33,6 @@
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -59,7 +58,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \

3
drivers/pinctrl/qcom/pinctrl-msm8998.c
View File

@ -35,7 +35,6 @@
.io_reg = base + 0x4 + 0x1000 * id, \
.intr_cfg_reg = base + 0x8 + 0x1000 * id, \
.intr_status_reg = base + 0xc + 0x1000 * id, \
.intr_target_reg = base + 0x8 + 0x1000 * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -61,7 +60,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
@ -86,7 +84,6 @@
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = 3, \
.drv_bit = 0, \

3
drivers/pinctrl/qcom/pinctrl-msm8x74.c
View File

@ -344,7 +344,6 @@ static const unsigned int hsic_data_pins[] = { 153 };
.io_reg = 0x1004 + 0x10 * id, \
.intr_cfg_reg = 0x1008 + 0x10 * id, \
.intr_status_reg = 0x100c + 0x10 * id, \
.intr_target_reg = 0x1008 + 0x10 * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -370,7 +369,6 @@ static const unsigned int hsic_data_pins[] = { 153 };
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
@ -401,7 +399,6 @@ static const unsigned int hsic_data_pins[] = { 153 };
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = 25, \
.pull_bit = -1, \
.drv_bit = -1, \

3
drivers/pinctrl/qcom/pinctrl-qcm2290.c
View File

@ -33,7 +33,6 @@
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -61,7 +60,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
@ -86,7 +84,6 @@
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = 3, \
.drv_bit = 0, \

2
drivers/pinctrl/qcom/pinctrl-qcs404.c
View File

@ -43,7 +43,6 @@ enum {
.io_reg = 0x1000 * id + 0x4, \
.intr_cfg_reg = 0x1000 * id + 0x8, \
.intr_status_reg = 0x1000 * id + 0xc, \
.intr_target_reg = 0x1000 * id + 0x8, \
.tile = _tile, \
.mux_bit = 2, \
.pull_bit = 0, \
@ -70,7 +69,6 @@ enum {
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = SOUTH, \
.mux_bit = -1, \
.pull_bit = pull, \

3
drivers/pinctrl/qcom/pinctrl-qcs615.c
View File

@ -43,7 +43,6 @@ static const char * const qcs615_tiles[] = {
.io_reg = 0x1000 * id + 0x4, \
.intr_cfg_reg = 0x1000 * id + 0x8, \
.intr_status_reg = 0x1000 * id + 0xc, \
.intr_target_reg = 0x1000 * id + 0x8, \
.tile = _tile, \
.mux_bit = 2, \
.pull_bit = 0, \
@ -70,7 +69,6 @@ static const char * const qcs615_tiles[] = {
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = _tile, \
.mux_bit = -1, \
.pull_bit = pull, \
@ -96,7 +94,6 @@ static const char * const qcs615_tiles[] = {
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = WEST, \
.mux_bit = -1, \
.pull_bit = 3, \

3
drivers/pinctrl/qcom/pinctrl-qcs8300.c
View File

@ -34,7 +34,6 @@
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -62,7 +61,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
@ -87,7 +85,6 @@
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = 3, \
.drv_bit = 0, \

1
drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
View File

@ -106,7 +106,6 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;
groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;
groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;
groups[gpio].mux_bit = 2;
groups[gpio].pull_bit = 0;

3
drivers/pinctrl/qcom/pinctrl-qdu1000.c
View File

@ -35,7 +35,6 @@
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -61,7 +60,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
@ -86,7 +84,6 @@
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = 3, \
.drv_bit = 0, \

3
drivers/pinctrl/qcom/pinctrl-sa8775p.c
View File

@ -34,7 +34,6 @@
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -63,7 +62,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
@ -88,7 +86,6 @@
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = 3, \
.drv_bit = 0, \

2
drivers/pinctrl/qcom/pinctrl-sar2130p.c
View File

@ -34,7 +34,6 @@
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -62,7 +61,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \

3
drivers/pinctrl/qcom/pinctrl-sc7180.c
View File

@ -41,7 +41,6 @@ enum {
.io_reg = 0x1000 * id + 0x4, \
.intr_cfg_reg = 0x1000 * id + 0x8, \
.intr_status_reg = 0x1000 * id + 0xc, \
.intr_target_reg = 0x1000 * id + 0x8, \
.tile = _tile, \
.mux_bit = 2, \
.pull_bit = 0, \
@ -68,7 +67,6 @@ enum {
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = SOUTH, \
.mux_bit = -1, \
.pull_bit = pull, \
@ -94,7 +92,6 @@ enum {
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = SOUTH, \
.mux_bit = -1, \
.pull_bit = 3, \

3
drivers/pinctrl/qcom/pinctrl-sc7280.c
View File

@ -31,7 +31,6 @@
.io_reg = 0x1000 * id + 0x4, \
.intr_cfg_reg = 0x1000 * id + 0x8, \
.intr_status_reg = 0x1000 * id + 0xc, \
.intr_target_reg = 0x1000 * id + 0x8, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -59,7 +58,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
@ -84,7 +82,6 @@
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = 3, \
.drv_bit = 0, \

3
drivers/pinctrl/qcom/pinctrl-sc8180x.c
View File

@ -60,7 +60,6 @@ static const struct tile_info sc8180x_tile_info[] = {
.io_reg = REG_SIZE * id + 0x4 + offset, \
.intr_cfg_reg = REG_SIZE * id + 0x8 + offset, \
.intr_status_reg = REG_SIZE * id + 0xc + offset,\
.intr_target_reg = REG_SIZE * id + 0x8 + offset,\
.tile = _tile, \
.mux_bit = 2, \
.pull_bit = 0, \
@ -90,7 +89,6 @@ static const struct tile_info sc8180x_tile_info[] = {
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = EAST, \
.mux_bit = -1, \
.pull_bit = pull, \
@ -116,7 +114,6 @@ static const struct tile_info sc8180x_tile_info[] = {
.io_reg = 0xb6004, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = SOUTH, \
.mux_bit = -1, \
.pull_bit = 3, \

3
drivers/pinctrl/qcom/pinctrl-sc8280xp.c
View File

@ -31,7 +31,6 @@
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -59,7 +58,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
@ -84,7 +82,6 @@
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = 3, \
.drv_bit = 0, \

2
drivers/pinctrl/qcom/pinctrl-sdm660.c
View File

@ -46,7 +46,6 @@ enum {
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.tile = _tile, \
.mux_bit = 2, \
.pull_bit = 0, \
@ -73,7 +72,6 @@ enum {
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = NORTH, \
.mux_bit = -1, \
.pull_bit = pull, \

166
drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c Normal file
View File

@ -0,0 +1,166 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023-2026, Richard Acayan. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-lpass-lpi.h"
enum lpass_lpi_functions {
LPI_MUX_comp_rx,
LPI_MUX_dmic1_clk,
LPI_MUX_dmic1_data,
LPI_MUX_dmic2_clk,
LPI_MUX_dmic2_data,
LPI_MUX_i2s1_clk,
LPI_MUX_i2s1_data,
LPI_MUX_i2s1_ws,
LPI_MUX_lpi_cdc_rst,
LPI_MUX_mclk0,
LPI_MUX_pdm_rx,
LPI_MUX_pdm_sync,
LPI_MUX_pdm_tx,
LPI_MUX_slimbus_clk,
LPI_MUX_gpio,
LPI_MUX__,
};
static const struct pinctrl_pin_desc sdm670_lpi_pinctrl_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
PINCTRL_PIN(14, "gpio14"),
PINCTRL_PIN(15, "gpio15"),
PINCTRL_PIN(16, "gpio16"),
PINCTRL_PIN(17, "gpio17"),
PINCTRL_PIN(18, "gpio18"),
PINCTRL_PIN(19, "gpio19"),
PINCTRL_PIN(20, "gpio20"),
PINCTRL_PIN(21, "gpio21"),
PINCTRL_PIN(22, "gpio22"),
PINCTRL_PIN(23, "gpio23"),
PINCTRL_PIN(24, "gpio24"),
PINCTRL_PIN(25, "gpio25"),
PINCTRL_PIN(26, "gpio26"),
PINCTRL_PIN(27, "gpio27"),
PINCTRL_PIN(28, "gpio28"),
PINCTRL_PIN(29, "gpio29"),
PINCTRL_PIN(30, "gpio30"),
PINCTRL_PIN(31, "gpio31"),
};
static const char * const comp_rx_groups[] = { "gpio22", "gpio24" };
static const char * const dmic1_clk_groups[] = { "gpio26" };
static const char * const dmic1_data_groups[] = { "gpio27" };
static const char * const dmic2_clk_groups[] = { "gpio28" };
static const char * const dmic2_data_groups[] = { "gpio29" };
static const char * const i2s1_clk_groups[] = { "gpio8" };
static const char * const i2s1_ws_groups[] = { "gpio9" };
static const char * const i2s1_data_groups[] = { "gpio10", "gpio11" };
static const char * const lpi_cdc_rst_groups[] = { "gpio29" };
static const char * const mclk0_groups[] = { "gpio19" };
static const char * const pdm_rx_groups[] = { "gpio21", "gpio23", "gpio25" };
static const char * const pdm_sync_groups[] = { "gpio19" };
static const char * const pdm_tx_groups[] = { "gpio20" };
static const char * const slimbus_clk_groups[] = { "gpio18" };
static const struct lpi_pingroup sdm670_lpi_pinctrl_groups[] = {
LPI_PINGROUP(0, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(1, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(2, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(3, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(4, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(5, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(6, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(7, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(8, LPI_NO_SLEW, _, _, i2s1_clk, _),
LPI_PINGROUP(9, LPI_NO_SLEW, _, _, i2s1_ws, _),
LPI_PINGROUP(10, LPI_NO_SLEW, _, _, _, i2s1_data),
LPI_PINGROUP(11, LPI_NO_SLEW, _, i2s1_data, _, _),
LPI_PINGROUP(12, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(13, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(14, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(15, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(16, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(18, LPI_NO_SLEW, _, slimbus_clk, _, _),
LPI_PINGROUP(19, LPI_NO_SLEW, mclk0, _, pdm_sync, _),
LPI_PINGROUP(20, LPI_NO_SLEW, _, pdm_tx, _, _),
LPI_PINGROUP(21, LPI_NO_SLEW, _, pdm_rx, _, _),
LPI_PINGROUP(22, LPI_NO_SLEW, _, comp_rx, _, _),
LPI_PINGROUP(23, LPI_NO_SLEW, pdm_rx, _, _, _),
LPI_PINGROUP(24, LPI_NO_SLEW, comp_rx, _, _, _),
LPI_PINGROUP(25, LPI_NO_SLEW, pdm_rx, _, _, _),
LPI_PINGROUP(26, LPI_NO_SLEW, dmic1_clk, _, _, _),
LPI_PINGROUP(27, LPI_NO_SLEW, dmic1_data, _, _, _),
LPI_PINGROUP(28, LPI_NO_SLEW, dmic2_clk, _, _, _),
LPI_PINGROUP(29, LPI_NO_SLEW, dmic2_data, lpi_cdc_rst, _, _),
LPI_PINGROUP(30, LPI_NO_SLEW, _, _, _, _),
LPI_PINGROUP(31, LPI_NO_SLEW, _, _, _, _),
};
static const struct lpi_function sdm670_lpi_pinctrl_functions[] = {
LPI_FUNCTION(comp_rx),
LPI_FUNCTION(dmic1_clk),
LPI_FUNCTION(dmic1_data),
LPI_FUNCTION(dmic2_clk),
LPI_FUNCTION(dmic2_data),
LPI_FUNCTION(i2s1_clk),
LPI_FUNCTION(i2s1_data),
LPI_FUNCTION(i2s1_ws),
LPI_FUNCTION(lpi_cdc_rst),
LPI_FUNCTION(mclk0),
LPI_FUNCTION(pdm_tx),
LPI_FUNCTION(pdm_rx),
LPI_FUNCTION(pdm_sync),
LPI_FUNCTION(slimbus_clk),
};
static const struct lpi_pinctrl_variant_data sdm670_lpi_pinctrl_data = {
.pins = sdm670_lpi_pinctrl_pins,
.npins = ARRAY_SIZE(sdm670_lpi_pinctrl_pins),
.groups = sdm670_lpi_pinctrl_groups,
.ngroups = ARRAY_SIZE(sdm670_lpi_pinctrl_groups),
.functions = sdm670_lpi_pinctrl_functions,
.nfunctions = ARRAY_SIZE(sdm670_lpi_pinctrl_functions),
.flags = LPI_FLAG_SLEW_RATE_SAME_REG,
};
static const struct of_device_id sdm670_lpi_pinctrl_of_match[] = {
{
.compatible = "qcom,sdm670-lpass-lpi-pinctrl",
.data = &sdm670_lpi_pinctrl_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, sdm670_lpi_pinctrl_of_match);
static struct platform_driver sdm670_lpi_pinctrl_driver = {
.driver = {
.name = "qcom-sdm670-lpass-lpi-pinctrl",
.of_match_table = sdm670_lpi_pinctrl_of_match,
},
.probe = lpi_pinctrl_probe,
.remove = lpi_pinctrl_remove,
};
module_platform_driver(sdm670_lpi_pinctrl_driver);
MODULE_AUTHOR("Richard Acayan <mailingradian@gmail.com>");
MODULE_DESCRIPTION("QTI SDM670 LPI GPIO pin control driver");
MODULE_LICENSE("GPL");

4
drivers/pinctrl/qcom/pinctrl-sdm670.c
View File

@ -37,7 +37,6 @@
.io_reg = base + 0x4 + REG_SIZE * id, \
.intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
.intr_status_reg = base + 0xc + REG_SIZE * id, \
.intr_target_reg = base + 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -67,7 +66,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = -1, \
.drv_bit = -1, \
@ -92,7 +90,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
@ -117,7 +114,6 @@
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = 3, \
.drv_bit = 0, \

3
drivers/pinctrl/qcom/pinctrl-sdm845.c
View File

@ -37,7 +37,6 @@
.io_reg = base + 0x4 + REG_SIZE * id, \
.intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
.intr_status_reg = base + 0xc + REG_SIZE * id, \
.intr_target_reg = base + 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -63,7 +62,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
@ -88,7 +86,6 @@
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = 3, \
.drv_bit = 0, \

2
drivers/pinctrl/qcom/pinctrl-sdx55.c
View File

@ -33,7 +33,6 @@
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -59,7 +58,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \

3
drivers/pinctrl/qcom/pinctrl-sdx65.c
View File

@ -33,7 +33,6 @@
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -59,7 +58,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
@ -84,7 +82,6 @@
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = 3, \
.drv_bit = 0, \

2
drivers/pinctrl/qcom/pinctrl-sdx75.c
View File

@ -19,7 +19,6 @@
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -60,7 +59,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \

3
drivers/pinctrl/qcom/pinctrl-sm4450.c
View File

@ -33,7 +33,6 @@
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -61,7 +60,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
@ -86,7 +84,6 @@
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = 3, \
.drv_bit = 0, \

3
drivers/pinctrl/qcom/pinctrl-sm6115.c
View File

@ -43,7 +43,6 @@ enum {
.io_reg = 0x4 + 0x1000 * id, \
.intr_cfg_reg = 0x8 + 0x1000 * id, \
.intr_status_reg = 0xc + 0x1000 * id, \
.intr_target_reg = 0x8 + 0x1000 * id, \
.tile = _tile, \
.mux_bit = 2, \
.pull_bit = 0, \
@ -70,7 +69,6 @@ enum {
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = _tile, \
.mux_bit = -1, \
.pull_bit = pull, \
@ -96,7 +94,6 @@ enum {
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = WEST, \
.mux_bit = -1, \
.pull_bit = 3, \

3
drivers/pinctrl/qcom/pinctrl-sm6125.c
View File

@ -40,7 +40,6 @@ enum {
.io_reg = 0x4 + 0x1000 * id, \
.intr_cfg_reg = 0x8 + 0x1000 * id, \
.intr_status_reg = 0xc + 0x1000 * id, \
.intr_target_reg = 0x8 + 0x1000 * id, \
.tile = _tile, \
.mux_bit = 2, \
.pull_bit = 0, \
@ -67,7 +66,6 @@ enum {
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = _tile, \
.mux_bit = -1, \
.pull_bit = pull, \
@ -93,7 +91,6 @@ enum {
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = WEST, \
.mux_bit = -1, \
.pull_bit = 3, \

3
drivers/pinctrl/qcom/pinctrl-sm6350.c
View File

@ -33,7 +33,6 @@
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -59,7 +58,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
@ -84,7 +82,6 @@
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = 3, \
.drv_bit = 0, \

3
drivers/pinctrl/qcom/pinctrl-sm6375.c
View File

@ -34,7 +34,6 @@
.io_reg = REG_SIZE * id + 0x4, \
.intr_cfg_reg = REG_SIZE * id + 0x8, \
.intr_status_reg = REG_SIZE * id + 0xc, \
.intr_target_reg = REG_SIZE * id + 0x8, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -62,7 +61,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
@ -87,7 +85,6 @@
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = 3, \
.drv_bit = 0, \

3
drivers/pinctrl/qcom/pinctrl-sm7150.c
View File

@ -47,7 +47,6 @@ enum {
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.tile = _tile, \
.mux_bit = 2, \
.pull_bit = 0, \
@ -74,7 +73,6 @@ enum {
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = _tile, \
.mux_bit = -1, \
.pull_bit = pull, \
@ -100,7 +98,6 @@ enum {
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = WEST, \
.mux_bit = -1, \
.pull_bit = 3, \

3
drivers/pinctrl/qcom/pinctrl-sm8150.c
View File

@ -43,7 +43,6 @@ enum {
.io_reg = 0x1000 * id + 0x4, \
.intr_cfg_reg = 0x1000 * id + 0x8, \
.intr_status_reg = 0x1000 * id + 0xc, \
.intr_target_reg = 0x1000 * id + 0x8, \
.tile = _tile, \
.mux_bit = 2, \
.pull_bit = 0, \
@ -70,7 +69,6 @@ enum {
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = NORTH, \
.mux_bit = -1, \
.pull_bit = pull, \
@ -96,7 +94,6 @@ enum {
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = SOUTH, \
.mux_bit = -1, \
.pull_bit = 3, \

3
drivers/pinctrl/qcom/pinctrl-sm8250.c
View File

@ -44,7 +44,6 @@ enum {
.io_reg = REG_SIZE * id + 0x4, \
.intr_cfg_reg = REG_SIZE * id + 0x8, \
.intr_status_reg = REG_SIZE * id + 0xc, \
.intr_target_reg = REG_SIZE * id + 0x8, \
.tile = _tile, \
.mux_bit = 2, \
.pull_bit = 0, \
@ -73,7 +72,6 @@ enum {
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = NORTH, \
.mux_bit = -1, \
.pull_bit = pull, \
@ -99,7 +97,6 @@ enum {
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.tile = SOUTH, \
.mux_bit = -1, \
.pull_bit = 3, \

3
drivers/pinctrl/qcom/pinctrl-sm8350.c
View File

@ -34,7 +34,6 @@
.io_reg = REG_SIZE * id + 0x4, \
.intr_cfg_reg = REG_SIZE * id + 0x8, \
.intr_status_reg = REG_SIZE * id + 0xc, \
.intr_target_reg = REG_SIZE * id + 0x8, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@ -60,7 +59,6 @@
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
@ -85,7 +83,6 @@
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = 3, \
.drv_bit = 0, \

Some files were not shown because too many files have changed in this diff Show More