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The Top Level Mode Multiplexer (TLMM) in the Qualcomm Hawi SoC provides GPIO and pinctrl functionality for UFS, SDC and 226 GPIO pins. Add a DeviceTree binding to describe the TLMM block on Qualcomm's Hawi SoC. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
121 lines
3.8 KiB
YAML
121 lines
3.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,hawi-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. Hawi TLMM block
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maintainers:
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- Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm Hawi SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,hawi-tlmm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 113
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gpio-line-names:
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maxItems: 226
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-hawi-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-hawi-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-hawi-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-9]|22[0-5])$"
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- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk,
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audio_ref_clk, cam_mclk, cci_async_in, cci_i2c0, cci_i2c1,
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cci_i2c2, cci_i2c3, cci_i2c4, cci_i2c5, cci_timer, coex_espmi,
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coex_uart1_rx, coex_uart1_tx, dbg_out_clk, ddr_bist, ddr_pxi,
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dp_hot, egpio, gcc_gp, gnss_adc, host_rst, i2chub0_se0,
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i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4, i2s0, i2s1,
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ibi_i3c, jitter_bist, mdp_esync0, mdp_esync1, mdp_esync2,
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mdp_vsync, mdp_vsync_e, mdp_vsync_p, mdp_vsync0_out,
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mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out,
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modem_pps_in, modem_pps_out, nav_gpio, nav_gpio0, nav_gpio3,
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nav_rffe, pcie0_clk_req_n, pcie0_rst_n, pcie1_clk_req_n,
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phase_flag, pll_bist_sync, pll_clk_aux, qdss_cti, qlink,
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qspi, qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2,
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qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0,
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qup2_se1, qup2_se2, qup2_se3, qup2_se4_01, qup2_se4_23,
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qup3_se0_01, qup3_se0_23, qup3_se1, qup3_se2, qup3_se3,
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qup3_se4, qup3_se5, qup4_se0, qup4_se1, qup4_se2, qup4_se3_01,
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qup4_se3_23, qup4_se3_l3, qup4_se4_01, qup4_se4_23, qup4_se4_l3,
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rng_rosc, sd_write_protect, sdc4_clk, sdc4_cmd, sdc4_data,
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sys_throttle, tb_trig_sdc, tmess_rng, tsense_clm, tsense_pwm,
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uim0, uim1, usb0_hs, usb_phy, vfr, vsense_trigger_mirnat,
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wcn_sw_ctrl ]
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required:
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- pins
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@f100000 {
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compatible = "qcom,hawi-tlmm";
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reg = <0x0f100000 0x300000>;
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interrupts = <GIC_ESPI 272 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 227>;
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interrupt-controller;
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#interrupt-cells = <2>;
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qup-uart7-state {
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pins = "gpio62", "gpio63";
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function = "qup1_se7";
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};
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};
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...
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