From 540e666a7662dc570f0eca451f75ba3cc31445bb Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 7 Feb 2026 10:06:41 -0300 Subject: [PATCH 01/84] dt-bindings: pinctrl: rockchip: Add RV1103B compatible Document the compatible string for the RV1103B SoC. Signed-off-by: Fabio Estevam Acked-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml index 76e607281716..9b3cbeb54fed 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml @@ -50,6 +50,7 @@ properties: - rockchip,rk3568-pinctrl - rockchip,rk3576-pinctrl - rockchip,rk3588-pinctrl + - rockchip,rv1103b-pinctrl - rockchip,rv1108-pinctrl - rockchip,rv1126-pinctrl From 6d3ea3120eaa51432c1788b0a48cfab3ab77d697 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 7 Feb 2026 10:06:42 -0300 Subject: [PATCH 02/84] pinctrl: rockchip: Add RV1103B pinctrl support Add pinctrl support for the RV1103B. Based on the 5.10 Rockchip vendor kernel driver. Signed-off-by: Fabio Estevam Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 313 ++++++++++++++++++++++++++++- drivers/pinctrl/pinctrl-rockchip.h | 1 + 2 files changed, 313 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index d87c0b1de616..d801dc64eb7f 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -467,6 +467,22 @@ static const struct pinctrl_ops rockchip_pctrl_ops = { * Hardware access */ +static struct rockchip_mux_recalced_data rv1103b_mux_recalced_data[] = { + { + .num = 1, + .pin = 6, + .reg = 0x10024, + .bit = 8, + .mask = 0xf + }, { + .num = 1, + .pin = 7, + .reg = 0x10024, + .bit = 12, + .mask = 0xf + }, +}; + static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { { .num = 1, @@ -1172,6 +1188,9 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) else regmap = info->regmap_base; + if (ctrl->type == RV1103B && bank->bank_num == 2 && pin >= 12) + return 0; + if (ctrl->type == RK3506) { if (bank->bank_num == 1) regmap = info->regmap_ioc1; @@ -1298,6 +1317,9 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) else regmap = info->regmap_base; + if (ctrl->type == RV1103B && bank->bank_num == 2 && pin >= 12) + return 0; + if (ctrl->type == RK3506) { if (bank->bank_num == 1) regmap = info->regmap_ioc1; @@ -1495,6 +1517,214 @@ static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, return 0; } +#define RV1103B_DRV_BITS_PER_PIN 8 +#define RV1103B_DRV_PINS_PER_REG 2 +#define RV1103B_DRV_GPIO0_A_OFFSET 0x40100 +#define RV1103B_DRV_GPIO0_B_OFFSET 0x50110 +#define RV1103B_DRV_GPIO1_A01_OFFSET 0x140 +#define RV1103B_DRV_GPIO1_A67_OFFSET 0x1014C +#define RV1103B_DRV_GPIO2_OFFSET 0x30180 +#define RV1103B_DRV_GPIO2_SARADC_OFFSET 0x3080C + +static int rv1103b_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + int ret = 0; + + *regmap = info->regmap_base; + switch (bank->bank_num) { + case 0: + if (pin_num < 7) + *reg = RV1103B_DRV_GPIO0_A_OFFSET; + else if (pin_num > 7 && pin_num < 14) + *reg = RV1103B_DRV_GPIO0_B_OFFSET - 0x10; + else + ret = -EINVAL; + break; + + case 1: + if (pin_num < 6) + *reg = RV1103B_DRV_GPIO1_A01_OFFSET; + else if (pin_num >= 6 && pin_num < 23) + *reg = RV1103B_DRV_GPIO1_A67_OFFSET - 0xc; + else if (pin_num >= 24 && pin_num < 30) + *reg = RV1103B_DRV_GPIO1_A67_OFFSET - 0xc; + else + ret = -EINVAL; + break; + + case 2: + if (pin_num < 12) { + *reg = RV1103B_DRV_GPIO2_OFFSET; + } else if (pin_num >= 16) { + ret = -EINVAL; + } else { + *reg = RV1103B_DRV_GPIO2_SARADC_OFFSET; + *bit = 10; + + return 0; + } + break; + + default: + ret = -EINVAL; + break; + } + + if (ret) { + dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); + + return ret; + } + + *reg += ((pin_num / RV1103B_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RV1103B_DRV_PINS_PER_REG; + *bit *= RV1103B_DRV_BITS_PER_PIN; + + return 0; +} + +#define RV1103B_PULL_BITS_PER_PIN 2 +#define RV1103B_PULL_PINS_PER_REG 8 +#define RV1103B_PULL_GPIO0_A_OFFSET 0x40200 +#define RV1103B_PULL_GPIO0_B_OFFSET 0x50204 +#define RV1103B_PULL_GPIO1_A01_OFFSET 0x210 +#define RV1103B_PULL_GPIO1_A67_OFFSET 0x10210 +#define RV1103B_PULL_GPIO2_OFFSET 0x30220 +#define RV1103B_PULL_GPIO2_SARADC_OFFSET 0x3080C + +static int rv1103b_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + int ret = 0; + + *regmap = info->regmap_base; + switch (bank->bank_num) { + case 0: + if (pin_num < 7) + *reg = RV1103B_PULL_GPIO0_A_OFFSET; + else if (pin_num > 7 && pin_num < 14) + *reg = RV1103B_PULL_GPIO0_B_OFFSET - 0x4; + else + ret = -EINVAL; + break; + + case 1: + if (pin_num < 6) + *reg = RV1103B_PULL_GPIO1_A01_OFFSET; + else if (pin_num >= 6 && pin_num < 23) + *reg = RV1103B_PULL_GPIO1_A67_OFFSET; + else if (pin_num >= 24 && pin_num < 30) + *reg = RV1103B_PULL_GPIO1_A67_OFFSET; + else + ret = -EINVAL; + break; + + case 2: + if (pin_num < 12) { + *reg = RV1103B_PULL_GPIO2_OFFSET; + } else if (pin_num >= 16) { + ret = -EINVAL; + } else { + *reg = RV1103B_PULL_GPIO2_SARADC_OFFSET; + *bit = 13; + + return 0; + } + break; + + default: + ret = -EINVAL; + break; + } + + if (ret) { + dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); + + return ret; + } + + *reg += ((pin_num / RV1103B_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RV1103B_PULL_PINS_PER_REG; + *bit *= RV1103B_PULL_BITS_PER_PIN; + + return 0; +} + +#define RV1103B_SMT_BITS_PER_PIN 1 +#define RV1103B_SMT_PINS_PER_REG 8 +#define RV1103B_SMT_GPIO0_A_OFFSET 0x40400 +#define RV1103B_SMT_GPIO0_B_OFFSET 0x50404 +#define RV1103B_SMT_GPIO1_A01_OFFSET 0x410 +#define RV1103B_SMT_GPIO1_A67_OFFSET 0x10410 +#define RV1103B_SMT_GPIO2_OFFSET 0x30420 +#define RV1103B_SMT_GPIO2_SARADC_OFFSET 0x3080C + +static int rv1103b_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + int ret = 0; + + *regmap = info->regmap_base; + switch (bank->bank_num) { + case 0: + if (pin_num < 7) + *reg = RV1103B_SMT_GPIO0_A_OFFSET; + else if (pin_num > 7 && pin_num < 14) + *reg = RV1103B_SMT_GPIO0_B_OFFSET - 0x4; + else + ret = -EINVAL; + break; + + case 1: + if (pin_num < 6) + *reg = RV1103B_SMT_GPIO1_A01_OFFSET; + else if (pin_num >= 6 && pin_num < 23) + *reg = RV1103B_SMT_GPIO1_A67_OFFSET; + else if (pin_num >= 24 && pin_num < 30) + *reg = RV1103B_SMT_GPIO1_A67_OFFSET; + else + ret = -EINVAL; + break; + + case 2: + if (pin_num < 12) { + *reg = RV1103B_SMT_GPIO2_OFFSET; + } else if (pin_num >= 16) { + ret = -EINVAL; + } else { + *reg = RV1103B_SMT_GPIO2_SARADC_OFFSET; + *bit = 8; + + return 0; + } + break; + + default: + ret = -EINVAL; + break; + } + + if (ret) { + dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); + + return ret; + } + + *reg += ((pin_num / RV1103B_SMT_PINS_PER_REG) * 4); + *bit = pin_num % RV1103B_SMT_PINS_PER_REG; + *bit *= RV1103B_SMT_BITS_PER_PIN; + + return 0; +} + #define RV1108_PULL_PMU_OFFSET 0x10 #define RV1108_PULL_OFFSET 0x110 #define RV1108_PULL_PINS_PER_REG 8 @@ -2982,6 +3212,9 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, u8 bit; int drv_type = bank->drv[pin_num / 8].drv_type; + if (ctrl->type == RV1103B && pin_num >= 12) + drv_type = DRV_TYPE_IO_LEVEL_2_BIT; + ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); if (ret) return ret; @@ -3043,6 +3276,11 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, if (ret) return ret; + if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) { + data = data >> 10; + return data & 0x3; + } + data >>= bit; data &= (1 << rmask_bits) - 1; @@ -3071,7 +3309,8 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, rmask_bits = RK3588_DRV_BITS_PER_PIN; ret = strength; goto config; - } else if (ctrl->type == RK3506 || + } else if (ctrl->type == RV1103B || + ctrl->type == RK3506 || ctrl->type == RK3528 || ctrl->type == RK3562 || ctrl->type == RK3568) { @@ -3182,6 +3421,12 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, ret = strength; } } + + if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) { + rmask_bits = 2; + ret = strength; + } + /* enable the write to the equivalent lower bits */ data = ((1 << rmask_bits) - 1) << (bit + 16); rmask = data | (data >> 16); @@ -3236,6 +3481,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT : PIN_CONFIG_BIAS_DISABLE; case PX30: + case RV1103B: case RV1108: case RK3188: case RK3288: @@ -3251,6 +3497,9 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) pull_type = bank->pull_type[pin_num / 8]; data >>= bit; data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; + + if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) + pull_type = 1; /* * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, * where that pull up value becomes 3. @@ -3297,6 +3546,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, ret = regmap_write(regmap, reg, data); break; case PX30: + case RV1103B: case RV1108: case RV1126: case RK3188: @@ -3312,6 +3562,8 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, case RK3576: case RK3588: pull_type = bank->pull_type[pin_num / 8]; + if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) + pull_type = 1; ret = -EINVAL; for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); i++) { @@ -3417,6 +3669,11 @@ static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) if (ret) return ret; + if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) { + data >>= 8; + return data & 0x3; + } + data >>= bit; switch (ctrl->type) { case RK3562: @@ -3473,6 +3730,12 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, } } + if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) { + data = 0x3 << (bit + 16); + rmask = data | (data >> 16); + data |= ((enable ? 0x3 : 0) << bit); + } + return regmap_update_bits(regmap, reg, rmask, data); } @@ -3579,6 +3842,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, case RK3066B: return pull ? false : true; case PX30: + case RV1103B: case RV1108: case RV1126: case RK3188: @@ -4318,6 +4582,51 @@ static struct rockchip_pin_ctrl px30_pin_ctrl = { .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, }; +static struct rockchip_pin_bank rv1103b_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(0, 32, "gpio0", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x40000, 0x50008, 0x50010, 0x50018, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20, 0x10028, 0x10030, 0x10038, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x30040, 0x30048, 0x30050, 0x30058, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), +}; + +static struct rockchip_pin_ctrl rv1103b_pin_ctrl __maybe_unused = { + .pin_banks = rv1103b_pin_banks, + .nr_banks = ARRAY_SIZE(rv1103b_pin_banks), + .label = "RV1103B-GPIO", + .type = RV1103B, + .iomux_recalced = rv1103b_mux_recalced_data, + .niomux_recalced = ARRAY_SIZE(rv1103b_mux_recalced_data), + .pull_calc_reg = rv1103b_calc_pull_reg_and_bit, + .drv_calc_reg = rv1103b_calc_drv_reg_and_bit, + .schmitt_calc_reg = rv1103b_calc_schmitt_reg_and_bit, +}; + static struct rockchip_pin_bank rv1108_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU, @@ -4954,6 +5263,8 @@ static struct rockchip_pin_ctrl rk3588_pin_ctrl = { static const struct of_device_id rockchip_pinctrl_dt_match[] = { { .compatible = "rockchip,px30-pinctrl", .data = &px30_pin_ctrl }, + { .compatible = "rockchip,rv1103b-pinctrl", + .data = &rv1103b_pin_ctrl }, { .compatible = "rockchip,rv1108-pinctrl", .data = &rv1108_pin_ctrl }, { .compatible = "rockchip,rv1126-pinctrl", diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index 4f4aff42a80a..bb0e803e3b8a 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -185,6 +185,7 @@ enum rockchip_pinctrl_type { PX30, + RV1103B, RV1108, RV1126, RK2928, From 1c5986eefde922cccaa9f74567ddf4cf468d8400 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Mon, 9 Feb 2026 19:15:29 +0530 Subject: [PATCH 03/84] dt-bindings: pinctrl: qcom,sm8450-lpass-lpi-pinctrl: Add SA8775P and QCS8300 pinctrl Document compatible for Qualcomm SA8775P and QCS8300 SoC LPASS TLMM pin controller, fully compatible with previous SM8450 generation (same amount of pins and functions). Signed-off-by: Mohammad Rafi Shaik Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml index e7565592da86..541c1c54ddb0 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml @@ -15,7 +15,13 @@ description: properties: compatible: - const: qcom,sm8450-lpass-lpi-pinctrl + oneOf: + - const: qcom,sm8450-lpass-lpi-pinctrl + - items: + - enum: + - qcom,qcs8300-lpass-lpi-pinctrl + - qcom,sa8775p-lpass-lpi-pinctrl + - const: qcom,sm8450-lpass-lpi-pinctrl reg: items: From 38e8cc1c79385c6317f3416519d8beff481c175b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 10 Feb 2026 17:02:29 +0100 Subject: [PATCH 04/84] pinctrl: Fix spelling problem The grammar is off. This fixes it. Fixes: 6e4f3db8dfcf ("pinctrl: just return if no valid maps") Reviewed-by: Bartosz Golaszewski Signed-off-by: Linus Walleij --- drivers/pinctrl/devicetree.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c index d0c3e26409a8..02a271dd292f 100644 --- a/drivers/pinctrl/devicetree.c +++ b/drivers/pinctrl/devicetree.c @@ -175,7 +175,7 @@ static int dt_to_map_one_config(struct pinctrl *p, * return. */ dev_info(p->dev, - "there is not valid maps for state %s\n", statename); + "there are no valid maps for state %s\n", statename); return 0; } From 0e129487c36b271e279eeafc186bd9a3e5756ac6 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Thu, 12 Feb 2026 15:38:09 -0600 Subject: [PATCH 05/84] pinctrl: pinctrl-single: add ti,am62l-padconf compatible string Add "ti,am62l-padconf" compatible string for the AM62L SoC, which requires register configurations to be restored during system resume after suspend to RAM (RTC only + DDR mode). This reuses the j7200 configuration which includes the PCS_CONTEXT_LOSS_OFF flag needed for proper restoration. Signed-off-by: Vignesh Raghavendra Signed-off-by: Kendall Willis Reviewed-by: Dhruva Gole Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index d85e6c1f6321..288c9c9bce9a 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1980,6 +1980,7 @@ static const struct of_device_id pcs_of_match[] = { { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup }, { .compatible = "ti,j7200-padconf", .data = &pinctrl_single_j7200 }, + { .compatible = "ti,am62l-padconf", .data = &pinctrl_single_j7200 }, { .compatible = "pinctrl-single", .data = &pinctrl_single }, { .compatible = "pinconf-single", .data = &pinconf_single }, { }, From a7f8f004c6e61a584d1b42c74849af2db44db801 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Mon, 16 Feb 2026 15:44:03 +0200 Subject: [PATCH 06/84] dt-bindings: pinctrl: document the Eliza Top Level Mode Multiplexer Document the Top Level Mode Multiplexer on the Eliza Platform. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bjorn Andersson Signed-off-by: Abel Vesa Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,eliza-tlmm.yaml | 138 ++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml new file mode 100644 index 000000000000..282650426487 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,eliza-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Eliza TLMM block + +maintainers: + - Abel Vesa + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Eliza SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,eliza-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 93 + + gpio-line-names: + maxItems: 185 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-eliza-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-eliza-tlmm-state" + additionalProperties: false + +$defs: + qcom-eliza-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-4])$" + - enum: [ ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0, + audio_ref_clk, cam_mclk, cci_async_in, cci_i2c_scl, + cci_i2c_sda, cci_timer, coex_uart1_rx, coex_uart1_tx, + coex_uart2_rx, coex_uart2_tx, dbg_out_clk, + ddr_bist_complete, ddr_bist_fail, ddr_bist_start, + ddr_bist_stop, ddr_pxi0, ddr_pxi1, dp0_hot, egpio, + gcc_gp1, gcc_gp2, gcc_gp3, gnss_adc0, gnss_adc1, + hdmi_ddc_scl, hdmi_ddc_sda, hdmi_dtest0, hdmi_dtest1, + hdmi_hot_plug, hdmi_pixel_clk, hdmi_rcv_det, hdmi_tx_cec, + host2wlan_sol, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, + ibi_i3c, jitter_bist, mdp_esync0_out, mdp_esync1_out, + mdp_vsync, mdp_vsync0_out, mdp_vsync11_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, + mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3, + pcie0_clk_req_n, pcie1_clk_req_n, phase_flag, + pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio_traceclk, + qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable, + qlink_big_request, qlink_little_enable, + qlink_little_request, qlink_wmss, qspi0, qspi_clk, + qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, + qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, + qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, + qup2_se7, resout_gpio, sd_write_protect, sdc1, sdc2, + sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tmess_prng0, + tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1, + tsense_pwm2, tsense_pwm3, tsense_pwm4, uim0_clk, + uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data, + uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1, + vsense_trigger_mirnat, wcn_sw_ctrl ] + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@f100000 { + compatible = "qcom,eliza-tlmm"; + reg = <0x0f100000 0x300000>; + + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&tlmm 0 0 186>; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + qup-uart14-default-state { + pins = "gpio18", "gpio19"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + }; +... From 6f26989e15fbabe3cdcc9afd25fca6ef99ed4dc4 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Mon, 16 Feb 2026 15:44:04 +0200 Subject: [PATCH 07/84] pinctrl: qcom: Add Eliza pinctrl driver Add pinctrl driver for TLMM block found in the Eliza SoC. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Signed-off-by: Abel Vesa Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig.msm | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-eliza.c | 1548 ++++++++++++++++++++++++++ 3 files changed, 1559 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-eliza.c diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm index 3e9e02774001..6df6159fa5f8 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -15,6 +15,16 @@ config PINCTRL_APQ8084 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm APQ8084 platform. +config PINCTRL_ELIZA + tristate "Qualcomm Technologies Inc Eliza pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM) + block found on the Qualcomm Technologies Inc Eliza platform. + Say Y here to compile statically, or M here to compile it as a module. + If unsure, say N. + config PINCTRL_GLYMUR tristate "Qualcomm Technologies Inc Glymur pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 4269d1781015..831103b3827b 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o +obj-$(CONFIG_PINCTRL_ELIZA) += pinctrl-eliza.o obj-$(CONFIG_PINCTRL_GLYMUR) += pinctrl-glymur.o obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pinctrl-eliza.c new file mode 100644 index 000000000000..1a2e6461a69b --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-eliza.c @@ -0,0 +1,1548 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 /* egpio mode */ \ + }, \ + .nfuncs = 12, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_wakeup_present_bit = 6, \ + .intr_wakeup_enable_bit = 7, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, ctl, io) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = io, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc eliza_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "UFS_RESET"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); + +static const unsigned int ufs_reset_pins[] = { 185 }; + +enum eliza_functions { + msm_mux_gpio, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ext_mclk0, + msm_mux_audio_ref_clk, + msm_mux_cam_mclk, + msm_mux_cci_async_in, + msm_mux_cci_i2c_scl, + msm_mux_cci_i2c_sda, + msm_mux_cci_timer, + msm_mux_coex_uart1_rx, + msm_mux_coex_uart1_tx, + msm_mux_coex_uart2_rx, + msm_mux_coex_uart2_tx, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist_complete, + msm_mux_ddr_bist_fail, + msm_mux_ddr_bist_start, + msm_mux_ddr_bist_stop, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_dp0_hot, + msm_mux_egpio, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gnss_adc0, + msm_mux_gnss_adc1, + msm_mux_hdmi_ddc_scl, + msm_mux_hdmi_ddc_sda, + msm_mux_hdmi_dtest0, + msm_mux_hdmi_dtest1, + msm_mux_hdmi_hot_plug, + msm_mux_hdmi_pixel_clk, + msm_mux_hdmi_rcv_det, + msm_mux_hdmi_tx_cec, + msm_mux_host2wlan_sol, + msm_mux_i2s0_data0, + msm_mux_i2s0_data1, + msm_mux_i2s0_sck, + msm_mux_i2s0_ws, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_mdp_esync0_out, + msm_mux_mdp_esync1_out, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0_out, + msm_mux_mdp_vsync11_out, + msm_mux_mdp_vsync1_out, + msm_mux_mdp_vsync2_out, + msm_mux_mdp_vsync3_out, + msm_mux_mdp_vsync_e, + msm_mux_nav_gpio0, + msm_mux_nav_gpio1, + msm_mux_nav_gpio2, + msm_mux_nav_gpio3, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie1_clk_req_n, + msm_mux_phase_flag, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_qdss_cti, + msm_mux_qdss_gpio_traceclk, + msm_mux_qdss_gpio_tracectl, + msm_mux_qdss_gpio_tracedata, + msm_mux_qlink_big_enable, + msm_mux_qlink_big_request, + msm_mux_qlink_little_enable, + msm_mux_qlink_little_request, + msm_mux_qlink_wmss, + msm_mux_qspi0, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup1_se0, + msm_mux_qup1_se1, + msm_mux_qup1_se2, + msm_mux_qup1_se3, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_qup1_se7, + msm_mux_qup2_se0, + msm_mux_qup2_se1, + msm_mux_qup2_se2, + msm_mux_qup2_se3, + msm_mux_qup2_se4, + msm_mux_qup2_se5, + msm_mux_qup2_se6, + msm_mux_qup2_se7, + msm_mux_resout_gpio, + msm_mux_sd_write_protect, + msm_mux_sdc1, + msm_mux_sdc2, + msm_mux_sdc2_fb_clk, + msm_mux_tb_trig_sdc1, + msm_mux_tb_trig_sdc2, + msm_mux_tmess_prng0, + msm_mux_tmess_prng1, + msm_mux_tmess_prng2, + msm_mux_tmess_prng3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsense_pwm3, + msm_mux_tsense_pwm4, + msm_mux_uim0_clk, + msm_mux_uim0_data, + msm_mux_uim0_present, + msm_mux_uim0_reset, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_usb0_hs, + msm_mux_usb_phy, + msm_mux_vfr_0, + msm_mux_vfr_1, + msm_mux_vsense_trigger_mirnat, + msm_mux_wcn_sw_ctrl, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", "gpio26", "gpio27", + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", + "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", + "gpio40", "gpio42", "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", + "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", + "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", + "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", + "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", + "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", + "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", + "gpio133", "gpio134", "gpio135", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", + "gpio184", +}; + +static const char *const aoss_cti_groups[] = { + "gpio0", "gpio1", "gpio26", "gpio27", +}; + +static const char *const atest_char_groups[] = { + "gpio71", "gpio70", "gpio72", "gpio74", "gpio73", +}; + +static const char *const atest_usb_groups[] = { + "gpio55", "gpio54", +}; + +static const char *const audio_ext_mclk0_groups[] = { + "gpio69", +}; + +static const char *const audio_ref_clk_groups[] = { + "gpio32", +}; + +static const char *const cam_mclk_groups[] = { + "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", +}; + +static const char *const cci_async_in_groups[] = { + "gpio115", "gpio31", "gpio30", +}; + +static const char *const cci_i2c_scl_groups[] = { + "gpio71", "gpio73", "gpio75", "gpio77", +}; + +static const char *const cci_i2c_sda_groups[] = { + "gpio70", "gpio72", "gpio74", "gpio76", +}; + +static const char *const cci_timer_groups[] = { + "gpio76", "gpio63", "gpio125", "gpio126", "gpio127", +}; + +static const char *const coex_uart1_rx_groups[] = { + "gpio112", +}; + +static const char *const coex_uart1_tx_groups[] = { + "gpio111", +}; + +static const char *const coex_uart2_rx_groups[] = { + "gpio116", +}; + +static const char *const coex_uart2_tx_groups[] = { + "gpio100", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio81", +}; + +static const char *const ddr_bist_complete_groups[] = { + "gpio52", +}; + +static const char *const ddr_bist_fail_groups[] = { + "gpio147", +}; + +static const char *const ddr_bist_start_groups[] = { + "gpio34", +}; + +static const char *const ddr_bist_stop_groups[] = { + "gpio53", +}; + +static const char *const ddr_pxi0_groups[] = { + "gpio54", "gpio55", +}; + +static const char *const ddr_pxi1_groups[] = { + "gpio40", "gpio42", +}; + +static const char *const dp0_hot_groups[] = { + "gpio55", +}; + +static const char *const egpio_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", "gpio138", "gpio139", + "gpio140", "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", + "gpio146", "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", + "gpio152", "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", + "gpio158", "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", + "gpio164", "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", + "gpio170", "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", + "gpio176", "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", + "gpio182", "gpio184", +}; + +static const char *const gcc_gp1_groups[] = { + "gpio27", "gpio53", +}; + +static const char *const gcc_gp2_groups[] = { + "gpio32", "gpio35", +}; + +static const char *const gcc_gp3_groups[] = { + "gpio30", "gpio33", +}; + +static const char *const gnss_adc0_groups[] = { + "gpio42", "gpio55", +}; + +static const char *const gnss_adc1_groups[] = { + "gpio40", "gpio54", +}; + +static const char *const hdmi_ddc_scl_groups[] = { + "gpio6", +}; + +static const char *const hdmi_ddc_sda_groups[] = { + "gpio7", +}; + +static const char *const hdmi_dtest0_groups[] = { + "gpio132", +}; + +static const char *const hdmi_dtest1_groups[] = { + "gpio133", +}; + +static const char *const hdmi_hot_plug_groups[] = { + "gpio47", +}; + +static const char *const hdmi_pixel_clk_groups[] = { + "gpio18", +}; + +static const char *const hdmi_rcv_det_groups[] = { + "gpio19", +}; + +static const char *const hdmi_tx_cec_groups[] = { + "gpio46", +}; + +static const char *const host2wlan_sol_groups[] = { + "gpio33", +}; + +static const char *const i2s0_data0_groups[] = { + "gpio64", +}; + +static const char *const i2s0_data1_groups[] = { + "gpio63", +}; + +static const char *const i2s0_sck_groups[] = { + "gpio60", +}; + +static const char *const i2s0_ws_groups[] = { + "gpio61", +}; + +static const char *const ibi_i3c_groups[] = { + "gpio0", "gpio1", "gpio4", "gpio5", "gpio12", "gpio13", + "gpio28", "gpio29", "gpio32", "gpio33", "gpio36", "gpio37", +}; + +static const char *const jitter_bist_groups[] = { + "gpio77", +}; + +static const char *const mdp_esync0_out_groups[] = { + "gpio13", +}; + +static const char *const mdp_esync1_out_groups[] = { + "gpio12", +}; + +static const char *const mdp_vsync_groups[] = { + "gpio16", "gpio17", "gpio79", "gpio100", "gpio120", "gpio121", +}; + +static const char *const mdp_vsync0_out_groups[] = { + "gpio17", +}; + +static const char *const mdp_vsync11_out_groups[] = { + "gpio27", +}; + +static const char *const mdp_vsync1_out_groups[] = { + "gpio17", +}; + +static const char *const mdp_vsync2_out_groups[] = { + "gpio16", +}; + +static const char *const mdp_vsync3_out_groups[] = { + "gpio16", +}; + +static const char *const mdp_vsync_e_groups[] = { + "gpio13", +}; + +static const char *const nav_gpio0_groups[] = { + "gpio119", +}; + +static const char *const nav_gpio1_groups[] = { + "gpio117", +}; + +static const char *const nav_gpio2_groups[] = { + "gpio118", +}; + +static const char *const nav_gpio3_groups[] = { + "gpio113", +}; + +static const char *const pcie0_clk_req_n_groups[] = { + "gpio80", +}; + +static const char *const pcie1_clk_req_n_groups[] = { + "gpio52", +}; + +static const char *const phase_flag_groups[] = { + "gpio71", "gpio70", "gpio174", "gpio175", "gpio172", "gpio171", + "gpio170", "gpio169", "gpio168", "gpio167", "gpio166", "gpio165", + "gpio182", "gpio164", "gpio163", "gpio162", "gpio161", "gpio160", + "gpio159", "gpio158", "gpio157", "gpio80", "gpio78", "gpio181", + "gpio76", "gpio75", "gpio180", "gpio179", "gpio178", "gpio177", + "gpio176", "gpio173", +}; + +static const char *const pll_bist_sync_groups[] = { + "gpio184", +}; + +static const char *const pll_clk_aux_groups[] = { + "gpio135", +}; + +static const char *const prng_rosc0_groups[] = { + "gpio67", +}; + +static const char *const prng_rosc1_groups[] = { + "gpio69", +}; + +static const char *const prng_rosc2_groups[] = { + "gpio76", +}; + +static const char *const prng_rosc3_groups[] = { + "gpio74", +}; + +static const char *const qdss_cti_groups[] = { + "gpio18", "gpio19", "gpio32", "gpio73", + "gpio74", "gpio154", "gpio176", "gpio184", +}; + +static const char *const qdss_gpio_traceclk_groups[] = { + "gpio54", "gpio147", +}; + +static const char *const qdss_gpio_tracectl_groups[] = { + "gpio72", "gpio144", +}; + +static const char *const qdss_gpio_tracedata_groups[] = { + "gpio30", "gpio31", "gpio34", "gpio35", "gpio40", "gpio42", + "gpio52", "gpio53", "gpio65", "gpio66", "gpio67", "gpio114", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio145", "gpio146", + "gpio155", "gpio156", "gpio163", "gpio164", "gpio167", "gpio168", + "gpio169", "gpio170", "gpio178", "gpio179", "gpio180", "gpio181", + "gpio182", +}; + +static const char *const qlink_big_enable_groups[] = { + "gpio96", +}; + +static const char *const qlink_big_request_groups[] = { + "gpio95", +}; + +static const char *const qlink_little_enable_groups[] = { + "gpio93", +}; + +static const char *const qlink_little_request_groups[] = { + "gpio92", +}; + +static const char *const qlink_wmss_groups[] = { + "gpio94", +}; + +static const char *const qspi0_groups[] = { + "gpio79", "gpio116", "gpio115", "gpio97", "gpio98", +}; + +static const char *const qspi_clk_groups[] = { + "gpio99", +}; + +static const char *const qspi_cs_groups[] = { + "gpio100", +}; + +static const char *const qup1_se0_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char *const qup1_se1_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char *const qup1_se2_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio52", "gpio55", "gpio53", "gpio40", "gpio42", "gpio30", +}; + +static const char *const qup1_se3_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char *const qup1_se4_groups[] = { + "gpio36", "gpio37", "gpio37", "gpio36", +}; + +static const char *const qup1_se5_groups[] = { + "gpio132", "gpio133", "gpio134", "gpio135", "gpio34", "gpio35", +}; + +static const char *const qup1_se6_groups[] = { + "gpio40", "gpio42", "gpio54", "gpio42", "gpio40", "gpio55", +}; + +static const char *const qup1_se7_groups[] = { + "gpio81", "gpio78", "gpio80", "gpio114", "gpio114", "gpio78", +}; + +static const char *const qup2_se0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const qup2_se1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char *const qup2_se2_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio16", "gpio17", "gpio18", +}; + +static const char *const qup2_se3_groups[] = { + "gpio79", "gpio116", "gpio97", "gpio100", "gpio100", "gpio116", +}; + +static const char *const qup2_se4_groups[] = { + "gpio12", "gpio13", "gpio26", "gpio27", +}; + +static const char *const qup2_se5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char *const qup2_se6_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char *const qup2_se7_groups[] = { + "gpio27", "gpio26", "gpio13", "gpio12", +}; + +static const char *const resout_gpio_groups[] = { + "gpio63", + "gpio69", + "gpio175", +}; + +static const char *const sd_write_protect_groups[] = { + "gpio57", +}; + +static const char *const sdc1_groups[] = { + "gpio121", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", + "gpio130", "gpio131", "gpio120", +}; + +static const char *const sdc2_groups[] = { + "gpio38", "gpio39", "gpio48", "gpio49", + "gpio51", "gpio62", +}; + +static const char *const sdc2_fb_clk_groups[] = { + "gpio50", +}; + +static const char *const tb_trig_sdc1_groups[] = { + "gpio34", +}; + +static const char *const tb_trig_sdc2_groups[] = { + "gpio35", +}; + +static const char *const tmess_prng0_groups[] = { + "gpio73", +}; + +static const char *const tmess_prng1_groups[] = { + "gpio72", +}; + +static const char *const tmess_prng2_groups[] = { + "gpio70", +}; + +static const char *const tmess_prng3_groups[] = { + "gpio71", +}; + +static const char *const tsense_pwm1_groups[] = { + "gpio56", +}; + +static const char *const tsense_pwm2_groups[] = { + "gpio56", +}; + +static const char *const tsense_pwm3_groups[] = { + "gpio56", +}; + +static const char *const tsense_pwm4_groups[] = { + "gpio56", +}; + +static const char *const uim0_clk_groups[] = { + "gpio85", +}; + +static const char *const uim0_data_groups[] = { + "gpio84", +}; + +static const char *const uim0_present_groups[] = { + "gpio87", +}; + +static const char *const uim0_reset_groups[] = { + "gpio86", +}; + +static const char *const uim1_clk_groups[] = { + "gpio98", "gpio89", +}; + +static const char *const uim1_data_groups[] = { + "gpio97", "gpio88", +}; + +static const char *const uim1_present_groups[] = { + "gpio100", "gpio91", +}; + +static const char *const uim1_reset_groups[] = { + "gpio99", "gpio90", +}; + +static const char *const usb0_hs_groups[] = { + "gpio56", +}; + +static const char *const usb_phy_groups[] = { + "gpio122", +}; + +static const char *const vfr_0_groups[] = { + "gpio63", +}; + +static const char *const vfr_1_groups[] = { + "gpio117", +}; + +static const char *const vsense_trigger_mirnat_groups[] = { + "gpio52", +}; + +static const char *const wcn_sw_ctrl_groups[] = { + "gpio81", +}; + +static const struct pinfunction eliza_functions[] = { + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(audio_ext_mclk0), + MSM_PIN_FUNCTION(audio_ref_clk), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async_in), + MSM_PIN_FUNCTION(cci_i2c_scl), + MSM_PIN_FUNCTION(cci_i2c_sda), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(coex_uart1_rx), + MSM_PIN_FUNCTION(coex_uart1_tx), + MSM_PIN_FUNCTION(coex_uart2_rx), + MSM_PIN_FUNCTION(coex_uart2_tx), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist_complete), + MSM_PIN_FUNCTION(ddr_bist_fail), + MSM_PIN_FUNCTION(ddr_bist_start), + MSM_PIN_FUNCTION(ddr_bist_stop), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(dp0_hot), + MSM_PIN_FUNCTION(egpio), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gnss_adc0), + MSM_PIN_FUNCTION(gnss_adc1), + MSM_PIN_FUNCTION(hdmi_ddc_scl), + MSM_PIN_FUNCTION(hdmi_ddc_sda), + MSM_PIN_FUNCTION(hdmi_dtest0), + MSM_PIN_FUNCTION(hdmi_dtest1), + MSM_PIN_FUNCTION(hdmi_hot_plug), + MSM_PIN_FUNCTION(hdmi_pixel_clk), + MSM_PIN_FUNCTION(hdmi_rcv_det), + MSM_PIN_FUNCTION(hdmi_tx_cec), + MSM_PIN_FUNCTION(host2wlan_sol), + MSM_PIN_FUNCTION(i2s0_data0), + MSM_PIN_FUNCTION(i2s0_data1), + MSM_PIN_FUNCTION(i2s0_sck), + MSM_PIN_FUNCTION(i2s0_ws), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(mdp_esync0_out), + MSM_PIN_FUNCTION(mdp_esync1_out), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0_out), + MSM_PIN_FUNCTION(mdp_vsync11_out), + MSM_PIN_FUNCTION(mdp_vsync1_out), + MSM_PIN_FUNCTION(mdp_vsync2_out), + MSM_PIN_FUNCTION(mdp_vsync3_out), + MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(nav_gpio0), + MSM_PIN_FUNCTION(nav_gpio1), + MSM_PIN_FUNCTION(nav_gpio2), + MSM_PIN_FUNCTION(nav_gpio3), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(prng_rosc2), + MSM_PIN_FUNCTION(prng_rosc3), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio_traceclk), + MSM_PIN_FUNCTION(qdss_gpio_tracectl), + MSM_PIN_FUNCTION(qdss_gpio_tracedata), + MSM_PIN_FUNCTION(qlink_big_enable), + MSM_PIN_FUNCTION(qlink_big_request), + MSM_PIN_FUNCTION(qlink_little_enable), + MSM_PIN_FUNCTION(qlink_little_request), + MSM_PIN_FUNCTION(qlink_wmss), + MSM_PIN_FUNCTION(qspi0), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qup1_se0), + MSM_PIN_FUNCTION(qup1_se1), + MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se3), + MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se5), + MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup1_se7), + MSM_PIN_FUNCTION(qup2_se0), + MSM_PIN_FUNCTION(qup2_se1), + MSM_PIN_FUNCTION(qup2_se2), + MSM_PIN_FUNCTION(qup2_se3), + MSM_PIN_FUNCTION(qup2_se4), + MSM_PIN_FUNCTION(qup2_se5), + MSM_PIN_FUNCTION(qup2_se6), + MSM_PIN_FUNCTION(qup2_se7), + MSM_PIN_FUNCTION(resout_gpio), + MSM_PIN_FUNCTION(sd_write_protect), + MSM_PIN_FUNCTION(sdc1), + MSM_PIN_FUNCTION(sdc2), + MSM_PIN_FUNCTION(sdc2_fb_clk), + MSM_PIN_FUNCTION(tb_trig_sdc1), + MSM_PIN_FUNCTION(tb_trig_sdc2), + MSM_PIN_FUNCTION(tmess_prng0), + MSM_PIN_FUNCTION(tmess_prng1), + MSM_PIN_FUNCTION(tmess_prng2), + MSM_PIN_FUNCTION(tmess_prng3), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(tsense_pwm3), + MSM_PIN_FUNCTION(tsense_pwm4), + MSM_PIN_FUNCTION(uim0_clk), + MSM_PIN_FUNCTION(uim0_data), + MSM_PIN_FUNCTION(uim0_present), + MSM_PIN_FUNCTION(uim0_reset), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(usb0_hs), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_0), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), + MSM_PIN_FUNCTION(wcn_sw_ctrl), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup eliza_groups[] = { + [0] = PINGROUP(0, qup2_se0, ibi_i3c, aoss_cti, _, _, _, _, _, _, _, _), + [1] = PINGROUP(1, qup2_se0, ibi_i3c, aoss_cti, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, qup2_se0, _, _, _, _, _, _, _, _, _, _), + [3] = PINGROUP(3, qup2_se0, _, _, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, qup2_se1, hdmi_ddc_scl, _, _, _, _, _, _, _, _, _), + [7] = PINGROUP(7, qup2_se1, hdmi_ddc_sda, _, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup2_se4, ibi_i3c, mdp_esync1_out, qup2_se7, _, _, _, _, _, _, _), + [13] = PINGROUP(13, qup2_se4, ibi_i3c, mdp_vsync_e, mdp_esync0_out, qup2_se7, _, _, _, _, _, _), + [14] = PINGROUP(14, _, _, _, _, _, _, _, _, _, _, _), + [15] = PINGROUP(15, _, _, _, _, _, _, _, _, _, _, _), + [16] = PINGROUP(16, qup2_se5, qup2_se2, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, _, _, _, _, _, _), + [17] = PINGROUP(17, qup2_se5, qup2_se2, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, _, _, _, _, _, _), + [18] = PINGROUP(18, qup2_se5, qup2_se2, hdmi_pixel_clk, _, qdss_cti, _, _, _, _, _, _), + [19] = PINGROUP(19, qup2_se5, hdmi_rcv_det, _, qdss_cti, _, _, _, _, _, _, _), + [20] = PINGROUP(20, qup2_se6, _, _, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, qup2_se6, _, _, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, qup2_se6, _, _, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, qup2_se6, _, _, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, _, _, _, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, _, _, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, qup2_se4, aoss_cti, qup2_se7, _, _, _, _, _, _, _, _), + [27] = PINGROUP(27, qup2_se4, aoss_cti, mdp_vsync11_out, qup2_se7, gcc_gp1, _, _, _, _, _, _), + [28] = PINGROUP(28, qup1_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [29] = PINGROUP(29, qup1_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [30] = PINGROUP(30, qup1_se0, qup1_se2, cci_async_in, gcc_gp3, qdss_gpio_tracedata, _, _, _, _, _, egpio), + [31] = PINGROUP(31, qup1_se0, cci_async_in, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio), + [32] = PINGROUP(32, qup1_se1, ibi_i3c, audio_ref_clk, gcc_gp2, qdss_cti, _, _, _, _, _, _), + [33] = PINGROUP(33, qup1_se1, ibi_i3c, host2wlan_sol, gcc_gp3, _, _, _, _, _, _, _), + [34] = PINGROUP(34, qup1_se1, qup1_se5, tb_trig_sdc1, ddr_bist_start, qdss_gpio_tracedata, _, _, _, _, _, _), + [35] = PINGROUP(35, qup1_se1, qup1_se5, tb_trig_sdc2, gcc_gp2, qdss_gpio_tracedata, _, _, _, _, _, _), + [36] = PINGROUP(36, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _), + [37] = PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _), + [41] = PINGROUP(41, _, _, _, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc0, ddr_pxi1, _, _, _, _, _), + [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, qup1_se3, _, _, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, qup1_se3, _, _, _, _, _, _, _, _, _, _), + [46] = PINGROUP(46, qup1_se3, hdmi_tx_cec, _, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, qup1_se3, hdmi_hot_plug, _, _, _, _, _, _, _, _, _), + [48] = PINGROUP(48, _, _, _, _, _, _, _, _, _, _, _), + [49] = PINGROUP(49, _, _, _, _, _, _, _, _, _, _, _), + [50] = PINGROUP(50, sdc2_fb_clk, _, _, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2, ddr_bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _), + [53] = PINGROUP(53, qup1_se2, qup1_se2, gcc_gp1, ddr_bist_stop, _, qdss_gpio_tracedata, _, _, _, _, _), + [54] = PINGROUP(54, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _), + [55] = PINGROUP(55, qup1_se2, dp0_hot, qup1_se6, _, gnss_adc0, atest_usb, ddr_pxi0, _, _, _, _), + [56] = PINGROUP(56, usb0_hs, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, _, _, _, _, _, _), + [57] = PINGROUP(57, sd_write_protect, _, _, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, _, _, _, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, i2s0_sck, _, _, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, i2s0_ws, _, _, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, _, _, _, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, resout_gpio, i2s0_data1, cci_timer, vfr_0, _, _, _, _, _, _, _), + [64] = PINGROUP(64, i2s0_data0, _, _, _, _, _, _, _, _, _, _), + [65] = PINGROUP(65, cam_mclk, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _), + [66] = PINGROUP(66, cam_mclk, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, cam_mclk, prng_rosc0, _, qdss_gpio_tracedata, _, _, _, _, _, _, _), + [68] = PINGROUP(68, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, cam_mclk, audio_ext_mclk0, resout_gpio, prng_rosc1, _, _, _, _, _, _, _), + [70] = PINGROUP(70, cci_i2c_sda, tmess_prng2, _, phase_flag, atest_char, _, _, _, _, _, _), + [71] = PINGROUP(71, cci_i2c_scl, tmess_prng3, _, phase_flag, atest_char, _, _, _, _, _, _), + [72] = PINGROUP(72, cci_i2c_sda, tmess_prng1, qdss_gpio_tracedata, atest_char, _, _, _, _, _, _, _), + [73] = PINGROUP(73, cci_i2c_scl, tmess_prng0, qdss_cti, atest_char, _, _, _, _, _, _, _), + [74] = PINGROUP(74, cci_i2c_sda, prng_rosc3, qdss_cti, atest_char, _, _, _, _, _, _, _), + [75] = PINGROUP(75, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, cci_i2c_sda, cci_timer, prng_rosc2, _, phase_flag, _, _, _, _, _, _), + [77] = PINGROUP(77, cci_i2c_scl, jitter_bist, _, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, qup1_se7, qup1_se7, _, phase_flag, _, _, _, _, _, _, _), + [79] = PINGROUP(79, qspi0, mdp_vsync, qup2_se3, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, pcie0_clk_req_n, qup1_se7, _, phase_flag, _, _, _, _, _, _, _), + [81] = PINGROUP(81, wcn_sw_ctrl, qup1_se7, dbg_out_clk, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, _, _, _, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, _, _, _, _, _, _, _, _, _, _, _), + [84] = PINGROUP(84, uim0_data, _, _, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, uim0_clk, _, _, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, uim0_reset, _, _, _, _, _, _, _, _, _, _), + [87] = PINGROUP(87, uim0_present, _, _, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, uim1_data, _, _, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, uim1_clk, _, _, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, uim1_reset, _, _, _, _, _, _, _, _, _, _), + [91] = PINGROUP(91, uim1_present, _, _, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, qlink_little_request, _, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, qlink_little_enable, _, _, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, qlink_wmss, _, _, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, qlink_big_request, _, _, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, qlink_big_enable, _, _, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, uim1_data, qspi0, qup2_se3, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, uim1_clk, qspi0, _, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, uim1_reset, qspi0, _, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup2_se3, mdp_vsync, _, _, _, _, _), + [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, _, _, _, _, _, _, _, _, _, _, _), + [103] = PINGROUP(103, _, _, _, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, _, _, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, _, _, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, _, _, _, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, _, _, _, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, _, _, _, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, _, _, _, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, _, _, _, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, coex_uart1_tx, _, _, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, coex_uart1_rx, _, _, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, _, nav_gpio3, _, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, qup1_se7, qup1_se7, _, qdss_gpio_tracedata, _, _, _, _, _, _, _), + [115] = PINGROUP(115, _, qspi0, cci_async_in, _, _, _, _, _, _, _, _), + [116] = PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3, _, _, _, _, _, _, _), + [117] = PINGROUP(117, nav_gpio1, _, vfr_1, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, nav_gpio2, _, _, _, _, _, _, _, _, _, _), + [119] = PINGROUP(119, nav_gpio0, _, _, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, sdc1, mdp_vsync, _, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, sdc1, mdp_vsync, _, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, usb_phy, _, _, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, sdc1, _, _, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, sdc1, _, _, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, sdc1, cci_timer, _, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, sdc1, cci_timer, _, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, sdc1, cci_timer, _, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, sdc1, _, _, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, sdc1, _, _, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, sdc1, _, _, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, sdc1, _, _, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, qup1_se5, _, qdss_gpio_tracedata, hdmi_dtest0, _, _, _, _, _, _, _), + [133] = PINGROUP(133, qup1_se5, _, qdss_gpio_tracedata, hdmi_dtest1, _, _, _, _, _, _, _), + [134] = PINGROUP(134, qup1_se5, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, qup1_se5, _, pll_clk_aux, qdss_gpio_tracedata, _, _, _, _, _, _, _), + [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _, _, _), + [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, _, _, _, _, _, _, _, _, _, _, egpio), + [139] = PINGROUP(139, _, _, _, _, _, _, _, _, _, _, egpio), + [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _, _, egpio), + [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _, _, egpio), + [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _, _, egpio), + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _, _, egpio), + [144] = PINGROUP(144, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, egpio), + [145] = PINGROUP(145, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _, egpio), + [146] = PINGROUP(146, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, egpio), + [147] = PINGROUP(147, ddr_bist_fail, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio), + [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _, _, egpio), + [149] = PINGROUP(149, _, _, _, _, _, _, _, _, _, _, egpio), + [150] = PINGROUP(150, _, _, _, _, _, _, _, _, _, _, egpio), + [151] = PINGROUP(151, _, _, _, _, _, _, _, _, _, _, egpio), + [152] = PINGROUP(152, _, _, _, _, _, _, _, _, _, _, egpio), + [153] = PINGROUP(153, _, _, _, _, _, _, _, _, _, _, egpio), + [154] = PINGROUP(154, qdss_cti, _, _, _, _, _, _, _, _, _, egpio), + [155] = PINGROUP(155, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, egpio), + [156] = PINGROUP(156, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, egpio), + [157] = PINGROUP(157, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [158] = PINGROUP(158, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [159] = PINGROUP(159, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [160] = PINGROUP(160, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [161] = PINGROUP(161, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [162] = PINGROUP(162, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [163] = PINGROUP(163, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio), + [164] = PINGROUP(164, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio), + [165] = PINGROUP(165, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [166] = PINGROUP(166, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [167] = PINGROUP(167, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio), + [168] = PINGROUP(168, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio), + [169] = PINGROUP(169, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio), + [170] = PINGROUP(170, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio), + [171] = PINGROUP(171, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [172] = PINGROUP(172, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [173] = PINGROUP(173, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [174] = PINGROUP(174, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [175] = PINGROUP(175, resout_gpio, _, phase_flag, _, _, _, _, _, _, _, egpio), + [176] = PINGROUP(176, _, phase_flag, qdss_cti, _, _, _, _, _, _, _, egpio), + [177] = PINGROUP(177, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio), + [178] = PINGROUP(178, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio), + [179] = PINGROUP(179, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio), + [180] = PINGROUP(180, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio), + [181] = PINGROUP(181, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio), + [182] = PINGROUP(182, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio), + [183] = PINGROUP(183, _, _, _, _, _, _, _, _, _, _, _), + [184] = PINGROUP(184, pll_bist_sync, qdss_cti, _, _, _, _, _, _, _, _, egpio), + [185] = UFS_RESET(ufs_reset, 0xc9004, 0xca000), +}; + +static const struct msm_gpio_wakeirq_map eliza_pdc_map[] = { + { 0, 82 }, { 3, 87 }, { 4, 90 }, { 6, 68 }, { 7, 153 }, + { 11, 85 }, { 12, 107 }, { 13, 106 }, { 16, 88 }, { 17, 70 }, + { 18, 134 }, { 19, 79 }, { 23, 80 }, { 26, 91 }, { 27, 74 }, + { 28, 137 }, { 29, 138 }, { 30, 139 }, { 31, 140 }, { 32, 117 }, + { 34, 100 }, { 35, 98 }, { 36, 141 }, { 39, 89 }, { 40, 142 }, + { 42, 143 }, { 44, 101 }, { 45, 144 }, { 46, 145 }, { 47, 146 }, + { 49, 75 }, { 51, 147 }, { 52, 148 }, { 53, 149 }, { 54, 150 }, + { 55, 151 }, { 56, 152 }, { 58, 71 }, { 59, 155 }, { 63, 99 }, + { 78, 156 }, { 79, 76 }, { 80, 157 }, { 81, 69 }, { 87, 158 }, + { 91, 67 }, { 92, 159 }, { 95, 160 }, { 98, 161 }, { 99, 162 }, + { 100, 83 }, { 108, 154 }, { 109, 84 }, { 112, 86 }, { 113, 92 }, + { 114, 93 }, { 115, 110 }, { 116, 94 }, { 117, 77 }, { 118, 108 }, + { 119, 95 }, { 120, 81 }, { 121, 96 }, { 122, 97 }, { 123, 102 }, + { 125, 103 }, { 127, 104 }, { 128, 105 }, { 129, 78 }, { 130, 112 }, + { 131, 113 }, { 133, 114 }, { 135, 115 }, { 139, 116 }, { 142, 118 }, + { 145, 109 }, { 147, 72 }, { 149, 111 }, { 154, 122 }, { 157, 119 }, + { 159, 120 }, { 161, 121 }, { 164, 123 }, { 165, 124 }, { 167, 125 }, + { 170, 126 }, { 171, 73 }, { 172, 127 }, { 173, 128 }, { 174, 129 }, + { 175, 130 }, { 176, 131 }, { 177, 132 }, { 179, 133 }, { 182, 135 }, + { 184, 136 }, +}; + +static const struct msm_pinctrl_soc_data eliza_tlmm = { + .pins = eliza_pins, + .npins = ARRAY_SIZE(eliza_pins), + .functions = eliza_functions, + .nfunctions = ARRAY_SIZE(eliza_functions), + .groups = eliza_groups, + .ngroups = ARRAY_SIZE(eliza_groups), + .ngpios = 186, + .wakeirq_map = eliza_pdc_map, + .nwakeirq_map = ARRAY_SIZE(eliza_pdc_map), + .egpio_func = 11, +}; + +static int eliza_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &eliza_tlmm); +} + +static const struct of_device_id eliza_tlmm_of_match[] = { + { .compatible = "qcom,eliza-tlmm", }, + {}, +}; + +static struct platform_driver eliza_tlmm_driver = { + .driver = { + .name = "eliza-tlmm", + .of_match_table = eliza_tlmm_of_match, + }, + .probe = eliza_tlmm_probe, +}; + +static int __init eliza_tlmm_init(void) +{ + return platform_driver_register(&eliza_tlmm_driver); +} +arch_initcall(eliza_tlmm_init); + +static void __exit eliza_tlmm_exit(void) +{ + platform_driver_unregister(&eliza_tlmm_driver); +} +module_exit(eliza_tlmm_exit); + +MODULE_DESCRIPTION("QTI Eliza TLMM driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, eliza_tlmm_of_match); From 7a29f373251e4d722a883184d4eab3bd763bb628 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 17 Feb 2026 13:57:36 +0100 Subject: [PATCH 08/84] pinctrl: qcom: De-acronymize Glymur SoC name Glymur is a codename of Qualcomm SoC, not an acronym. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-glymur.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-glymur.c b/drivers/pinctrl/qcom/pinctrl-glymur.c index 44f9745325b7..2da3b513d31b 100644 --- a/drivers/pinctrl/qcom/pinctrl-glymur.c +++ b/drivers/pinctrl/qcom/pinctrl-glymur.c @@ -1812,6 +1812,6 @@ static void __exit glymur_tlmm_exit(void) } module_exit(glymur_tlmm_exit); -MODULE_DESCRIPTION("QTI GLYMUR TLMM driver"); +MODULE_DESCRIPTION("QTI Glymur TLMM driver"); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(of, glymur_tlmm_of_match); From 8dba7a13a4142069b3586c5514453fa460cc8b6c Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 11 Feb 2026 16:00:00 -0500 Subject: [PATCH 09/84] dt-bindings: pinctrl: convert fsl,imx27-pinctrl.txt to YAML Convert fsl,imx27-pinctrl.txt to YAML format. Additional changes: - Add the compatible string "fsl,imx1-iomuxc". - Add gpio@... child nodes. - Add ranges property. - Remove the redundant intermediate node between pinmux and group nodes. Signed-off-by: Frank Li Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../bindings/pinctrl/fsl,imx27-iomuxc.yaml | 126 ++++++++++++++++++ .../bindings/pinctrl/fsl,imx27-pinctrl.txt | 121 ----------------- 2 files changed, 126 insertions(+), 121 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx27-iomuxc.yaml delete mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-iomuxc.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-iomuxc.yaml new file mode 100644 index 000000000000..1254bfcaa7cb --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-iomuxc.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx27-iomuxc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX1/i.MX25/i.MX27 IOMUX Controller + +maintainers: + - Frank Li + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + enum: + - fsl,imx1-iomuxc + - fsl,imx27-iomuxc + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + +patternProperties: + '^gpio@[0-9a-f]+$': + type: object + $ref: /schemas/gpio/fsl-imx-gpio.yaml + unevaluatedProperties: false + + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + three integers array, represents a group of pins mux and config + setting. The format is fsl,pins = . + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: + PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 + configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN + is the pin number on the specific port (between 0 and 31) + - description: | + MUX_ID is function + (direction << 2) + (gpio_oconf << 4) + + (gpio_iconfa << 8) + (gpio_iconfb << 10) + + function value is used to select the pin function. + Possible values: + 0 - Primary function + 1 - Alternate function + 2 - GPIO + Registers: GIUS (GPIO In Use), GPR (General Purpose Register) + + direction defines the data direction of the pin. + Possible values: + 0 - Input + 1 - Output + Register: DDIR + + gpio_oconf configures the gpio submodule output signal. + This does not have any effect unless GPIO function is + selected. A/B/C_IN are output signals of function blocks + A,B and C. Specific function blocks are described in the + reference manual. + Possible values: + 0 - A_IN + 1 - B_IN + 2 - C_IN + 3 - Data Register + Registers: OCR1, OCR2 + + gpio_iconfa/b configures the gpio submodule input to + functionblocks A and B. GPIO function should be selected if + this is configured. + Possible values: + 0 - GPIO_IN + 1 - Interrupt Status Register + 2 - Pulldown + 3 - Pullup + Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2 + + - description: + CONFIG can be 0 or 1, meaning Pullup disable/enable. + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +allOf: + - $ref: pinctrl.yaml# + +unevaluatedProperties: false + +examples: + - | + pinmux@10015000 { + compatible = "fsl,imx27-iomuxc"; + reg = <0x10015000 0x600>; + + uartgrp { + fsl,pins = < + 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */ + 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */ + 0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */ + 0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */ + >; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt deleted file mode 100644 index d1706ea82572..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt +++ /dev/null @@ -1,121 +0,0 @@ -* Freescale IMX27 IOMUX Controller - -Required properties: -- compatible: "fsl,imx27-iomuxc" - -The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes. - -Required properties for pin configuration node: -- fsl,pins: three integers array, represents a group of pins mux and config - setting. The format is fsl,pins = . - - PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable - configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin - number on the specific port (between 0 and 31). - - MUX_ID is - function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10) - - function value is used to select the pin function. - Possible values: - 0 - Primary function - 1 - Alternate function - 2 - GPIO - Registers: GIUS (GPIO In Use), GPR (General Purpose Register) - - direction defines the data direction of the pin. - Possible values: - 0 - Input - 1 - Output - Register: DDIR - - gpio_oconf configures the gpio submodule output signal. This does not - have any effect unless GPIO function is selected. A/B/C_IN are output - signals of function blocks A,B and C. Specific function blocks are - described in the reference manual. - Possible values: - 0 - A_IN - 1 - B_IN - 2 - C_IN - 3 - Data Register - Registers: OCR1, OCR2 - - gpio_iconfa/b configures the gpio submodule input to functionblocks A and - B. GPIO function should be selected if this is configured. - Possible values: - 0 - GPIO_IN - 1 - Interrupt Status Register - 2 - Pulldown - 3 - Pullup - Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2 - - CONFIG can be 0 or 1, meaning Pullup disable/enable. - - -The iomux controller has gpio child nodes which are embedded in the iomux -control registers. They have to be defined as child nodes of the iomux device -node. If gpio subnodes are defined "#address-cells", "#size-cells" and "ranges" -properties for the iomux device node are required. - -Example: - -iomuxc: iomuxc@10015000 { - compatible = "fsl,imx27-iomuxc"; - reg = <0x10015000 0x600>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio1: gpio@10015000 { - ... - }; - - ... - - uart { - pinctrl_uart1: uart-1 { - fsl,pins = < - 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */ - 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */ - 0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */ - 0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */ - >; - }; - - ... - }; -}; - - -For convenience there are macros defined in imx27-pinfunc.h which provide PIN -and MUX_ID. They are structured as MX27_PAD___. The names -are defined in the i.MX27 reference manual. - -The above example using macros: - -iomuxc: iomuxc@10015000 { - compatible = "fsl,imx27-iomuxc"; - reg = <0x10015000 0x600>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio1: gpio@10015000 { - ... - }; - - ... - - uart { - pinctrl_uart1: uart-1 { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - ... - }; -}; From af5e323bd9a94756c5b2b4e200d0232cf85431cd Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 11 Feb 2026 16:00:01 -0500 Subject: [PATCH 10/84] dt-bindings: pinctrl: imx35: add compatible string fsl,imx25-iomuxc Add compatible string fsl,imx25-iomuxc. Signed-off-by: Frank Li Acked-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml index 265c43ab76f4..846e110062b2 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml @@ -20,6 +20,7 @@ properties: compatible: oneOf: - enum: + - fsl,imx25-iomuxc - fsl,imx35-iomuxc - fsl,imx51-iomuxc - fsl,imx53-iomuxc From f10f6fca875e8360de7dd40652f5076234ea7a9d Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Sun, 22 Feb 2026 18:33:29 -0500 Subject: [PATCH 11/84] pinctrl: pic32: change all cases of bare 'unsigned' to 'unsigned int' Address the following warning from checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' Fixes: 2ba384e6c3810 ("pinctrl: pinctrl-pic32: Add PIC32 pin control driver") Signed-off-by: Brian Masney Reviewed-by: Bartosz Golaszewski Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-pic32.c | 40 ++++++++++++++++----------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/pinctrl-pic32.c b/drivers/pinctrl/pinctrl-pic32.c index 16bbbcf72062..e97727a799d5 100644 --- a/drivers/pinctrl/pinctrl-pic32.c +++ b/drivers/pinctrl/pinctrl-pic32.c @@ -1696,7 +1696,7 @@ static inline struct pic32_gpio_bank *irqd_to_bank(struct irq_data *d) } static inline struct pic32_gpio_bank *pctl_to_bank(struct pic32_pinctrl *pctl, - unsigned pin) + unsigned int pin) { return &pctl->gpio_banks[pin / PINS_PER_BANK]; } @@ -1709,7 +1709,7 @@ static int pic32_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) } static const char *pic32_pinctrl_get_group_name(struct pinctrl_dev *pctldev, - unsigned group) + unsigned int group) { struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); @@ -1717,9 +1717,9 @@ static const char *pic32_pinctrl_get_group_name(struct pinctrl_dev *pctldev, } static int pic32_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, - unsigned group, - const unsigned **pins, - unsigned *num_pins) + unsigned int group, + const unsigned int **pins, + unsigned int *num_pins) { struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); @@ -1745,7 +1745,7 @@ static int pic32_pinmux_get_functions_count(struct pinctrl_dev *pctldev) } static const char * -pic32_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned func) +pic32_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned int func) { struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); @@ -1753,9 +1753,9 @@ pic32_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned func) } static int pic32_pinmux_get_function_groups(struct pinctrl_dev *pctldev, - unsigned func, + unsigned int func, const char * const **groups, - unsigned * const num_groups) + unsigned int * const num_groups) { struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); @@ -1766,7 +1766,7 @@ static int pic32_pinmux_get_function_groups(struct pinctrl_dev *pctldev, } static int pic32_pinmux_enable(struct pinctrl_dev *pctldev, - unsigned func, unsigned group) + unsigned int func, unsigned int group) { struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); const struct pic32_pin_group *pg = &pctl->groups[group]; @@ -1795,7 +1795,7 @@ static int pic32_pinmux_enable(struct pinctrl_dev *pctldev, static int pic32_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, - unsigned offset) + unsigned int offset) { struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct pic32_gpio_bank *bank = gpiochip_get_data(range->gc); @@ -1810,7 +1810,7 @@ static int pic32_gpio_request_enable(struct pinctrl_dev *pctldev, } static int pic32_gpio_direction_input(struct gpio_chip *chip, - unsigned offset) + unsigned int offset) { struct pic32_gpio_bank *bank = gpiochip_get_data(chip); u32 mask = BIT(offset); @@ -1820,7 +1820,7 @@ static int pic32_gpio_direction_input(struct gpio_chip *chip, return 0; } -static int pic32_gpio_get(struct gpio_chip *chip, unsigned offset) +static int pic32_gpio_get(struct gpio_chip *chip, unsigned int offset) { struct pic32_gpio_bank *bank = gpiochip_get_data(chip); @@ -1842,7 +1842,7 @@ static int pic32_gpio_set(struct gpio_chip *chip, unsigned int offset, } static int pic32_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) + unsigned int offset, int value) { struct pic32_gpio_bank *bank = gpiochip_get_data(chip); u32 mask = BIT(offset); @@ -1855,7 +1855,7 @@ static int pic32_gpio_direction_output(struct gpio_chip *chip, static int pic32_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, - unsigned offset, bool input) + unsigned int offset, bool input) { struct gpio_chip *chip = range->gc; @@ -1876,12 +1876,12 @@ static const struct pinmux_ops pic32_pinmux_ops = { .gpio_set_direction = pic32_gpio_set_direction, }; -static int pic32_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, +static int pic32_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) { struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin); - unsigned param = pinconf_to_config_param(*config); + unsigned int param = pinconf_to_config_param(*config); u32 mask = BIT(pin - bank->gpio_chip.base); u32 arg; @@ -1917,12 +1917,12 @@ static int pic32_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, return 0; } -static int pic32_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long *configs, unsigned num_configs) +static int pic32_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) { struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin); - unsigned param; + unsigned int param; u32 arg; unsigned int i; u32 offset = pin - bank->gpio_chip.base; @@ -1987,7 +1987,7 @@ static struct pinctrl_desc pic32_pinctrl_desc = { .owner = THIS_MODULE, }; -static int pic32_gpio_get_direction(struct gpio_chip *chip, unsigned offset) +static int pic32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { struct pic32_gpio_bank *bank = gpiochip_get_data(chip); From 8932547b4b28d2d1ec95f7d0bb5f9011a24dcfc7 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Sun, 22 Feb 2026 18:33:30 -0500 Subject: [PATCH 12/84] pinctrl: pic32: use consistent spacing around '+' Address the following warning from checkpatch.pl: ERROR: need consistent spacing around '+' (ctx:WxV) Fixes: 2ba384e6c3810 ("pinctrl: pinctrl-pic32: Add PIC32 pin control driver") Signed-off-by: Brian Masney Reviewed-by: Bartosz Golaszewski Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-pic32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-pic32.c b/drivers/pinctrl/pinctrl-pic32.c index e97727a799d5..eb438c9d9667 100644 --- a/drivers/pinctrl/pinctrl-pic32.c +++ b/drivers/pinctrl/pinctrl-pic32.c @@ -1938,7 +1938,7 @@ static int pic32_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, switch (param) { case PIN_CONFIG_BIAS_PULL_UP: dev_dbg(pctl->dev, " pullup\n"); - writel(mask, bank->reg_base +PIC32_SET(CNPU_REG)); + writel(mask, bank->reg_base + PIC32_SET(CNPU_REG)); break; case PIN_CONFIG_BIAS_PULL_DOWN: dev_dbg(pctl->dev, " pulldown\n"); From 575f0bcd2d64e12bbe8f1f28d4f287a8872f2012 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Sun, 22 Feb 2026 18:33:31 -0500 Subject: [PATCH 13/84] pinctrl: pic32: allow driver to be compiled with COMPILE_TEST This driver currently only supports builds against a PIC32 target. Now that commit b8694faa1a0f ("pinctrl: pic32: update include to use pic32.h from platform_data") is merged, it's possible to compile this driver on other architectures. To avoid future breakage of this driver in the future, let's update the Kconfig so that it can be built with COMPILE_TEST enabled on all architectures. Signed-off-by: Brian Masney Reviewed-by: Bartosz Golaszewski Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index afecd9407f53..1965d4fb461d 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -478,7 +478,7 @@ config PINCTRL_PEF2256 config PINCTRL_PIC32 bool "Microchip PIC32 pin controller driver" depends on OF - depends on MACH_PIC32 + depends on MACH_PIC32 || COMPILE_TEST select PINMUX select GENERIC_PINCONF select GPIOLIB_IRQCHIP From 5ffb2da4a38fd85cc8f71fca7c04be28897d2354 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 23 Feb 2026 19:06:52 +0100 Subject: [PATCH 14/84] pinctrl: cy8c95x0: Use devm_mutex_init() for mutex initialization Use devm_mutex_init() since it brings some benefits when CONFIG_DEBUG_MUTEXES is enabled. Signed-off-by: Andy Shevchenko Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-cy8c95x0.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index a4b04bf6d081..a562c5307de8 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -1312,7 +1312,9 @@ static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq) DECLARE_BITMAP(pending_irqs, MAX_LINE); int ret; - mutex_init(&chip->irq_lock); + ret = devm_mutex_init(chip->dev, &chip->irq_lock); + if (ret) + return ret; bitmap_zero(pending_irqs, MAX_LINE); @@ -1474,7 +1476,9 @@ static int cy8c95x0_probe(struct i2c_client *client) bitmap_fill(chip->map, MAX_LINE); bitmap_clear(chip->map, 20, 4); - mutex_init(&chip->i2c_lock); + ret = devm_mutex_init(dev, &chip->i2c_lock); + if (ret) + return ret; if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) { ret = cy8c95x0_acpi_get_irq(&client->dev); From 970dacb3b9f0fedbbbcfd7dbf1f4f22340b3f359 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 23 Feb 2026 19:06:53 +0100 Subject: [PATCH 15/84] pinctrl: cy8c95x0: remove duplicate error message The pin control core is covered to report any error via message. The devm_request_threaded_irq() already prints an error message. Remove the duplicates. While at it, drop the info message as the same information about an IRQ in use can be retrieved differently. Signed-off-by: Andy Shevchenko Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-cy8c95x0.c | 21 +++++---------------- 1 file changed, 5 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index a562c5307de8..86d65c51dd9b 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -1310,6 +1310,7 @@ static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq) { struct gpio_irq_chip *girq = &chip->gpio_chip.irq; DECLARE_BITMAP(pending_irqs, MAX_LINE); + struct device *dev = chip->dev; int ret; ret = devm_mutex_init(chip->dev, &chip->irq_lock); @@ -1338,17 +1339,9 @@ static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq) girq->handler = handle_simple_irq; girq->threaded = true; - ret = devm_request_threaded_irq(chip->dev, irq, - NULL, cy8c95x0_irq_handler, - IRQF_ONESHOT | IRQF_SHARED, - dev_name(chip->dev), chip); - if (ret) { - dev_err(chip->dev, "failed to request irq %d\n", irq); - return ret; - } - dev_info(chip->dev, "Registered threaded IRQ\n"); - - return 0; + return devm_request_threaded_irq(dev, irq, NULL, cy8c95x0_irq_handler, + IRQF_ONESHOT | IRQF_SHARED, + dev_name(chip->dev), chip); } static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip) @@ -1364,11 +1357,7 @@ static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip) pd->owner = THIS_MODULE; chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip); - if (IS_ERR(chip->pctldev)) - return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev), - "can't register controller\n"); - - return 0; + return PTR_ERR_OR_ZERO(chip->pctldev); } static int cy8c95x0_detect(struct i2c_client *client, From 014884732095b982412d13d3220c3fe8483b9b3e Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 23 Feb 2026 19:06:54 +0100 Subject: [PATCH 16/84] pinctrl: cy8c95x0: Unify messages with help of dev_err_probe() Unify error messages that might appear during probe phase by switching to use dev_err_probe(). Signed-off-by: Andy Shevchenko Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-cy8c95x0.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 86d65c51dd9b..3b262cf2c6f8 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -1321,10 +1321,8 @@ static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq) /* Read IRQ status register to clear all pending interrupts */ ret = cy8c95x0_irq_pending(chip, pending_irqs); - if (ret) { - dev_err(chip->dev, "failed to clear irq status register\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to clear irq status register\n"); /* Mask all interrupts */ bitmap_fill(chip->irq_mask, MAX_LINE); From 8434c691193b9f812a446833c657fb2431aa94fd Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 23 Feb 2026 19:06:55 +0100 Subject: [PATCH 17/84] pinctrl: cy8c95x0: Move driver data to the local variable in ->probe() For all these years of driver existence the driver_data has been used only as a raw material for other fields in the struct cy8c95x0_pinctrl. Move it from the structure to be just a local variable in ->probe(). Later, if ever need arises, we may reconsider that. While at it, drop an unneeded validation and replace uintptr_t with plain unsigned long which is more readable and works in the same way. Signed-off-by: Andy Shevchenko Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-cy8c95x0.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 3b262cf2c6f8..cd1c5cedfeda 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -144,7 +144,6 @@ static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = { * @map: Mask used to compensate for Gport2 width * @nport: Number of Gports in this chip * @gpio_chip: gpiolib chip - * @driver_data: private driver data * @dev: struct device * @pctldev: pin controller device * @pinctrl_desc: pin controller description @@ -165,7 +164,6 @@ struct cy8c95x0_pinctrl { DECLARE_BITMAP(map, MAX_LINE); unsigned int nport; struct gpio_chip gpio_chip; - unsigned long driver_data; struct device *dev; struct pinctrl_dev *pctldev; struct pinctrl_desc pinctrl_desc; @@ -1397,6 +1395,7 @@ static int cy8c95x0_probe(struct i2c_client *client) struct cy8c95x0_pinctrl *chip; struct regmap_config regmap_conf; struct regmap_range_cfg regmap_range_conf; + unsigned long driver_data; int ret; chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); @@ -1406,11 +1405,9 @@ static int cy8c95x0_probe(struct i2c_client *client) chip->dev = dev; /* Set the device type */ - chip->driver_data = (uintptr_t)i2c_get_match_data(client); - if (!chip->driver_data) - return -ENODEV; + driver_data = (unsigned long)i2c_get_match_data(client); - chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK; + chip->tpin = driver_data & CY8C95X0_GPIO_MASK; chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ); memcpy(®map_range_conf, &cy8c95x0_ranges[0], sizeof(regmap_range_conf)); From a603cf701f94f233032dd66bbc6e1b03d866550f Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 23 Feb 2026 19:06:56 +0100 Subject: [PATCH 18/84] pinctrl: cy8c95x0: Drop unused 'name' in struct cy8c95x0_pinctrl The 'name' is only assigned and never used. Drop it for good. Signed-off-by: Andy Shevchenko Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-cy8c95x0.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index cd1c5cedfeda..7b35b86c6d46 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -147,7 +147,6 @@ static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = { * @dev: struct device * @pctldev: pin controller device * @pinctrl_desc: pin controller description - * @name: Chip controller name * @tpin: Total number of pins * @gpio_reset: GPIO line handler that can reset the IC */ @@ -167,7 +166,6 @@ struct cy8c95x0_pinctrl { struct device *dev; struct pinctrl_dev *pctldev; struct pinctrl_desc pinctrl_desc; - char name[32]; unsigned int tpin; struct gpio_desc *gpio_reset; }; @@ -1414,15 +1412,12 @@ static int cy8c95x0_probe(struct i2c_client *client) switch (chip->tpin) { case 20: - strscpy(chip->name, cy8c95x0_id[0].name); regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE - 1; break; case 40: - strscpy(chip->name, cy8c95x0_id[1].name); regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE - 1; break; case 60: - strscpy(chip->name, cy8c95x0_id[2].name); regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE - 1; break; default: From 04fcdb3a34d66a2848f5c7073f85071eeb1e5fae Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 23 Feb 2026 19:06:57 +0100 Subject: [PATCH 19/84] =?UTF-8?q?pinctrl:=20cy8c95x0:=20Eliminate=20fragil?= =?UTF-8?q?e=20use=20of=20I=C2=B2C=20ID=20table?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The I²C ID table is a subject to new entries that may potentially break the order of the existing ones. Avoid this by using string literals for the chip naming. Note, linker will deduplicate same string literals and use only a single copy, hence it won't be the change in size in data section. Signed-off-by: Andy Shevchenko Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-cy8c95x0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 7b35b86c6d46..9130e50d3220 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -1369,13 +1369,13 @@ static int cy8c95x0_detect(struct i2c_client *client, return ret; switch (ret & GENMASK(7, 4)) { case 0x20: - name = cy8c95x0_id[0].name; + name = "cy8c9520"; break; case 0x40: - name = cy8c95x0_id[1].name; + name = "cy8c9540"; break; case 0x60: - name = cy8c95x0_id[2].name; + name = "cy8c9560"; break; default: return -ENODEV; From 41c78b33e96f9ac4abb618d36625e6e7f7e7aeb7 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 23 Feb 2026 19:06:58 +0100 Subject: [PATCH 20/84] pinctrl: cy8c95x0: Gather ID tables in one place We have three ID tables spread over the driver code. Move all of them closer to the end of the file where the first user appears to be. With that done, drop unneeded trailing commas. Signed-off-by: Andy Shevchenko Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-cy8c95x0.c | 38 +++++++++++++++--------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 9130e50d3220..b88a627708ff 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -72,24 +72,6 @@ #define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) \ (CY8C95X0_VIRTUAL + (x) - CY8C95X0_PORTSEL + (p) * MUXED_STRIDE) -static const struct i2c_device_id cy8c95x0_id[] = { - { "cy8c9520", 20, }, - { "cy8c9540", 40, }, - { "cy8c9560", 60, }, - { } -}; -MODULE_DEVICE_TABLE(i2c, cy8c95x0_id); - -#define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio)) - -static const struct of_device_id cy8c95x0_dt_ids[] = { - { .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), }, - { .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), }, - { .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), }, - { } -}; -MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids); - static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true }; static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = { @@ -1478,8 +1460,26 @@ static int cy8c95x0_probe(struct i2c_client *client) return cy8c95x0_setup_gpiochip(chip); } +static const struct i2c_device_id cy8c95x0_id[] = { + { "cy8c9520", 20 }, + { "cy8c9540", 40 }, + { "cy8c9560", 60 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, cy8c95x0_id); + +#define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio)) + +static const struct of_device_id cy8c95x0_dt_ids[] = { + { .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20) }, + { .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40) }, + { .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60) }, + { } +}; +MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids); + static const struct acpi_device_id cy8c95x0_acpi_ids[] = { - { "INT3490", 40, }, + { "INT3490", 40 }, { } }; MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids); From 9c105255108b57f0b0241ee488e5b84d6196789c Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 24 Feb 2026 13:39:04 +0000 Subject: [PATCH 21/84] pinctrl: pinconf-generic: perform basic checks on pincfg properties Some pinconf properties are mutually exclusive, either because they convey the same information in different units or represent incompatible configurations of the same pin. Attempt, in two ways, to prevent these situations. Firstly, for enable/disable properties, produce an error if both are set. Since enable/disable properties share the same enum value, they can be trivially checked via the newly added bitmap. Having both enable and disable for the same config makes no sense at all, so produce an error in this case. For interactions between properties, doing them outside the loop makes more sense as it can be evaluated once. In case there are some edge cases that would be broken by producing an error, only warn for now. Signed-off-by: Conor Dooley Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf-generic.c | 39 ++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 94b1d057197c..901a225f3531 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -222,7 +222,10 @@ static int parse_dt_cfg(struct device_node *np, unsigned int count, unsigned long *cfg, unsigned int *ncfg) { - int i; + unsigned long *properties; + int i, test; + + properties = bitmap_zalloc(count, GFP_KERNEL); for (i = 0; i < count; i++) { u32 val; @@ -251,11 +254,45 @@ static int parse_dt_cfg(struct device_node *np, if (ret) val = par->default_value; + /* if param is greater than count, these are custom properties */ + if (par->param <= count) { + ret = test_and_set_bit(par->param, properties); + if (ret) { + pr_err("%s: conflicting setting detected for %s\n", + np->name, par->property); + bitmap_free(properties); + return -EINVAL; + } + } + pr_debug("found %s with value %u\n", par->property, val); cfg[*ncfg] = pinconf_to_config_packed(par->param, val); (*ncfg)++; } + if (test_bit(PIN_CONFIG_DRIVE_STRENGTH, properties) && + test_bit(PIN_CONFIG_DRIVE_STRENGTH_UA, properties)) + pr_err("%s: cannot have multiple drive strength properties\n", + np->name); + + test = test_bit(PIN_CONFIG_BIAS_BUS_HOLD, properties) + + test_bit(PIN_CONFIG_BIAS_DISABLE, properties) + + test_bit(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, properties) + + test_bit(PIN_CONFIG_BIAS_PULL_UP, properties) + + test_bit(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, properties) + + test_bit(PIN_CONFIG_BIAS_PULL_DOWN, properties); + if (test > 1) + pr_err("%s: cannot have multiple bias configurations\n", + np->name); + + test = test_bit(PIN_CONFIG_DRIVE_OPEN_DRAIN, properties) + + test_bit(PIN_CONFIG_DRIVE_OPEN_SOURCE, properties) + + test_bit(PIN_CONFIG_DRIVE_PUSH_PULL, properties); + if (test > 1) + pr_err("%s: cannot have multiple drive configurations\n", + np->name); + + bitmap_free(properties); return 0; } From a901e8705f89f3616fad3bb6aeddba33be86b08a Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 24 Feb 2026 13:39:05 +0000 Subject: [PATCH 22/84] dt-bindings: pinctrl: pincfg-node: add restrictions on conflicting properties Many of the possible pincfg properties are not compatible with one another, either because they represent mutually exclusive states for a pin or because they provide the same information in different units. Add some simple restrictions to prevent invalid configurations. Signed-off-by: Conor Dooley Signed-off-by: Linus Walleij --- .../bindings/pinctrl/pincfg-node.yaml | 105 ++++++++++++++++-- 1 file changed, 98 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml b/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml index a916d0fc79a9..fe936ab09104 100644 --- a/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml @@ -162,12 +162,103 @@ properties: this affects the expected delay in ps before latching a value to an output pin. -if: - required: - - skew-delay -then: - properties: - skew-delay-input-ps: false - skew-delay-output-ps: false +allOf: + - if: + required: + - skew-delay + then: + properties: + skew-delay-input-ps: false + skew-delay-output-ps: false + + - if: + required: + - input-disable + then: + properties: + input-enable: false + + - if: + required: + - output-disable + then: + properties: + output-enable: false + output-impedance-ohms: false + + - if: + required: + - output-low + then: + properties: + output-high: false + + - if: + required: + - low-power-enable + then: + properties: + low-power-disable: false + + - if: + required: + - input-schmitt-disable + then: + properties: + input-schmitt-enable: false + input-schmitt-microvolt: false + + - if: + required: + - drive-strength + then: + properties: + drive-strength-microamp: false + + - if: + anyOf: + - required: + - drive-open-source + - required: + - drive-open-drain + - required: + - drive-push-pull + then: + oneOf: + - required: + - drive-open-source + - required: + - drive-open-drain + - required: + - drive-push-pull + + - if: + anyOf: + - required: + - bias-disable + - required: + - bias-high-impedance + - required: + - bias-bus-hold + - required: + - bias-pull-up + - required: + - bias-pull-down + - required: + - bias-pull-pin-default + then: + oneOf: + - required: + - bias-disable + - required: + - bias-high-impedance + - required: + - bias-bus-hold + - required: + - bias-pull-up + - required: + - bias-pull-down + - required: + - bias-pull-pin-default additionalProperties: true From 27a2ef20c0ae458d3dd6a19070dad662d0769001 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Monin?= Date: Thu, 26 Feb 2026 14:33:49 +0100 Subject: [PATCH 23/84] pinctrl: eyeq5: Use match data MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of using the pin descriptions, pin functions and register offsets of the EyeQ5 directly, access those via a pointer to a newly introduced struct eq5p_match_data. This structure contains, in addition to the pin descriptions and pin functions, an array of pin banks. Each bank holds the number of pins and the register offsets. All functions accessing a pin now use a pointer to a bank structure and an offset inside that bank. The conversion from a pin number to a bank and an offset is done in the new function eq5p_pin_to_bank_offset(), which replace eq5p_pin_to_bank() and eq5p_pin_to_offset(). All the data related to the EyeQ5 is declared with the eq5p_eyeq5_ prefix to distinguish it from the common code. During the probe, we use the parent OF node to get the match data. We cannot directly use an OF node since pinctrl-eyeq5 is an auxiliary device of clk-eyeq. Signed-off-by: Benoît Monin Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-eyeq5.c | 342 ++++++++++++++++++++------------ 1 file changed, 213 insertions(+), 129 deletions(-) diff --git a/drivers/pinctrl/pinctrl-eyeq5.c b/drivers/pinctrl/pinctrl-eyeq5.c index 5f6af934a516..c780af09cde9 100644 --- a/drivers/pinctrl/pinctrl-eyeq5.c +++ b/drivers/pinctrl/pinctrl-eyeq5.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -38,18 +39,6 @@ #include "core.h" #include "pinctrl-utils.h" -struct eq5p_pinctrl { - struct pinctrl_desc desc; - void __iomem *base; -}; - -enum eq5p_bank { - EQ5P_BANK_A, - EQ5P_BANK_B, - - EQ5P_BANK_COUNT, -}; - enum eq5p_regs { EQ5P_PD, EQ5P_PU, @@ -60,9 +49,24 @@ enum eq5p_regs { EQ5P_REG_COUNT, }; -static const unsigned int eq5p_regs[EQ5P_BANK_COUNT][EQ5P_REG_COUNT] = { - [EQ5P_BANK_A] = {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0}, - [EQ5P_BANK_B] = {0x0C8, 0x0CC, 0x0D8, 0x0DC, 0x0B4}, +struct eq5p_bank { + const unsigned int npins; + const unsigned int regs[EQ5P_REG_COUNT]; +}; + +struct eq5p_match_data { + const unsigned int npins; + const unsigned int nfunctions; + const unsigned int nbanks; + const struct pinctrl_pin_desc *pins; + const struct pinfunction *functions; + const struct eq5p_bank *banks; +}; + +struct eq5p_pinctrl { + struct pinctrl_desc desc; + void __iomem *base; + const struct eq5p_match_data *data; }; /* @@ -70,10 +74,18 @@ static const unsigned int eq5p_regs[EQ5P_BANK_COUNT][EQ5P_REG_COUNT] = { */ #define EQ5P_DS_MASK GENMASK(1, 0) +/* + * The GPIO function is always the first function + */ +#define EQ5P_GPIO_FUNC_SELECTOR 0 + +/* Helper to declare pinfunction */ +#define EQ5P_PINFUNCTION(func, groups) PINCTRL_PINFUNCTION(func, groups, ARRAY_SIZE(groups)) + /* * Comments to the right of each pin are the "signal name" in the datasheet. */ -static const struct pinctrl_pin_desc eq5p_pins[] = { +static const struct pinctrl_pin_desc eq5p_eyeq5_pins[] = { /* Bank A */ PINCTRL_PIN(0, "PA0"), /* A0_TIMER0_CK */ PINCTRL_PIN(1, "PA1"), /* A1_TIMER0_EOC */ @@ -105,35 +117,35 @@ static const struct pinctrl_pin_desc eq5p_pins[] = { PINCTRL_PIN(27, "PA27"), /* A27_SPI_1_CS1 */ PINCTRL_PIN(28, "PA28"), /* A28_REF_CLK0 */ -#define EQ5P_PIN_OFFSET_BANK_B 29 +#define EQ5P_EYEQ5_PIN_OFFSET_BANK_B 29 /* Bank B */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 0, "PB0"), /* B0_TIMER3_CK */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 1, "PB1"), /* B1_TIMER3_EOC */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 2, "PB2"), /* B2_TIMER4_CK */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 3, "PB3"), /* B3_TIMER4_EOC */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 4, "PB4"), /* B4_TIMER6_EXT_INCAP1 */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 5, "PB5"), /* B5_TIMER6_EXT_INCAP2 */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 6, "PB6"), /* B6_TIMER6_EXT_OUTCMP1 */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 7, "PB7"), /* B7_TIMER6_EXT_OUTCMP2 */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 8, "PB8"), /* B8_UART_2_TX */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 9, "PB9"), /* B9_UART_2_RX */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 10, "PB10"), /* B10_CAN_2_TX */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 11, "PB11"), /* B11_CAN_2_RX */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 12, "PB12"), /* B12_SPI_2_DO */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 13, "PB13"), /* B13_SPI_2_DI */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 14, "PB14"), /* B14_SPI_2_CK */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 15, "PB15"), /* B15_SPI_2_CS0 */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 16, "PB16"), /* B16_SPI_2_CS1 */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 17, "PB17"), /* B17_SPI_3_DO */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 18, "PB18"), /* B18_SPI_3_DI */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 19, "PB19"), /* B19_SPI_3_CK */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 20, "PB20"), /* B20_SPI_3_CS0 */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 21, "PB21"), /* B21_SPI_3_CS1 */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 22, "PB22"), /* B22_MCLK0 */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 0, "PB0"), /* B0_TIMER3_CK */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 1, "PB1"), /* B1_TIMER3_EOC */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 2, "PB2"), /* B2_TIMER4_CK */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 3, "PB3"), /* B3_TIMER4_EOC */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 4, "PB4"), /* B4_TIMER6_EXT_INCAP1 */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 5, "PB5"), /* B5_TIMER6_EXT_INCAP2 */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 6, "PB6"), /* B6_TIMER6_EXT_OUTCMP1 */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 7, "PB7"), /* B7_TIMER6_EXT_OUTCMP2 */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 8, "PB8"), /* B8_UART_2_TX */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 9, "PB9"), /* B9_UART_2_RX */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 10, "PB10"), /* B10_CAN_2_TX */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 11, "PB11"), /* B11_CAN_2_RX */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 12, "PB12"), /* B12_SPI_2_DO */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 13, "PB13"), /* B13_SPI_2_DI */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 14, "PB14"), /* B14_SPI_2_CK */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 15, "PB15"), /* B15_SPI_2_CS0 */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 16, "PB16"), /* B16_SPI_2_CS1 */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 17, "PB17"), /* B17_SPI_3_DO */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 18, "PB18"), /* B18_SPI_3_DI */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 19, "PB19"), /* B19_SPI_3_CK */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 20, "PB20"), /* B20_SPI_3_CS0 */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 21, "PB21"), /* B21_SPI_3_CS1 */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 22, "PB22"), /* B22_MCLK0 */ }; -static const char * const gpio_groups[] = { +static const char * const eq5p_eyeq5_gpio_groups[] = { /* Bank A */ "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA9", "PA10", "PA11", "PA12", "PA13", "PA14", "PA15", @@ -147,70 +159,90 @@ static const char * const gpio_groups[] = { }; /* Groups of functions on bank A */ -static const char * const timer0_groups[] = { "PA0", "PA1" }; -static const char * const timer1_groups[] = { "PA2", "PA3" }; -static const char * const timer2_groups[] = { "PA4", "PA5" }; -static const char * const timer5_groups[] = { "PA6", "PA7", "PA8", "PA9" }; -static const char * const uart0_groups[] = { "PA10", "PA11" }; -static const char * const uart1_groups[] = { "PA12", "PA13" }; -static const char * const can0_groups[] = { "PA14", "PA15" }; -static const char * const can1_groups[] = { "PA16", "PA17" }; -static const char * const spi0_groups[] = { "PA18", "PA19", "PA20", "PA21", "PA22" }; -static const char * const spi1_groups[] = { "PA23", "PA24", "PA25", "PA26", "PA27" }; -static const char * const refclk0_groups[] = { "PA28" }; +static const char * const eq5p_eyeq5_timer0_groups[] = { "PA0", "PA1" }; +static const char * const eq5p_eyeq5_timer1_groups[] = { "PA2", "PA3" }; +static const char * const eq5p_eyeq5_timer2_groups[] = { "PA4", "PA5" }; +static const char * const eq5p_eyeq5_timer5_groups[] = { "PA6", "PA7", "PA8", "PA9" }; +static const char * const eq5p_eyeq5_uart0_groups[] = { "PA10", "PA11" }; +static const char * const eq5p_eyeq5_uart1_groups[] = { "PA12", "PA13" }; +static const char * const eq5p_eyeq5_can0_groups[] = { "PA14", "PA15" }; +static const char * const eq5p_eyeq5_can1_groups[] = { "PA16", "PA17" }; +static const char * const eq5p_eyeq5_spi0_groups[] = { "PA18", "PA19", "PA20", "PA21", "PA22" }; +static const char * const eq5p_eyeq5_spi1_groups[] = { "PA23", "PA24", "PA25", "PA26", "PA27" }; +static const char * const eq5p_eyeq5_refclk0_groups[] = { "PA28" }; /* Groups of functions on bank B */ -static const char * const timer3_groups[] = { "PB0", "PB1" }; -static const char * const timer4_groups[] = { "PB2", "PB3" }; -static const char * const timer6_groups[] = { "PB4", "PB5", "PB6", "PB7" }; -static const char * const uart2_groups[] = { "PB8", "PB9" }; -static const char * const can2_groups[] = { "PB10", "PB11" }; -static const char * const spi2_groups[] = { "PB12", "PB13", "PB14", "PB15", "PB16" }; -static const char * const spi3_groups[] = { "PB17", "PB18", "PB19", "PB20", "PB21" }; -static const char * const mclk0_groups[] = { "PB22" }; +static const char * const eq5p_eyeq5_timer3_groups[] = { "PB0", "PB1" }; +static const char * const eq5p_eyeq5_timer4_groups[] = { "PB2", "PB3" }; +static const char * const eq5p_eyeq5_timer6_groups[] = { "PB4", "PB5", "PB6", "PB7" }; +static const char * const eq5p_eyeq5_uart2_groups[] = { "PB8", "PB9" }; +static const char * const eq5p_eyeq5_can2_groups[] = { "PB10", "PB11" }; +static const char * const eq5p_eyeq5_spi2_groups[] = { "PB12", "PB13", "PB14", "PB15", "PB16" }; +static const char * const eq5p_eyeq5_spi3_groups[] = { "PB17", "PB18", "PB19", "PB20", "PB21" }; +static const char * const eq5p_eyeq5_mclk0_groups[] = { "PB22" }; -static const struct pinfunction eq5p_functions[] = { - /* GPIO having a fixed index is depended upon, see GPIO_FUNC_SELECTOR. */ - PINCTRL_PINFUNCTION("gpio", gpio_groups, ARRAY_SIZE(gpio_groups)), -#define GPIO_FUNC_SELECTOR 0 +static const struct pinfunction eq5p_eyeq5_functions[] = { + /* GPIO having a fixed index is depended upon, see EQ5P_GPIO_FUNC_SELECTOR. */ + EQ5P_PINFUNCTION("gpio", eq5p_eyeq5_gpio_groups), /* Bank A functions */ - PINCTRL_PINFUNCTION("timer0", timer0_groups, ARRAY_SIZE(timer0_groups)), - PINCTRL_PINFUNCTION("timer1", timer1_groups, ARRAY_SIZE(timer1_groups)), - PINCTRL_PINFUNCTION("timer2", timer2_groups, ARRAY_SIZE(timer2_groups)), - PINCTRL_PINFUNCTION("timer5", timer5_groups, ARRAY_SIZE(timer5_groups)), - PINCTRL_PINFUNCTION("uart0", uart0_groups, ARRAY_SIZE(uart0_groups)), - PINCTRL_PINFUNCTION("uart1", uart1_groups, ARRAY_SIZE(uart1_groups)), - PINCTRL_PINFUNCTION("can0", can0_groups, ARRAY_SIZE(can0_groups)), - PINCTRL_PINFUNCTION("can1", can1_groups, ARRAY_SIZE(can1_groups)), - PINCTRL_PINFUNCTION("spi0", spi0_groups, ARRAY_SIZE(spi0_groups)), - PINCTRL_PINFUNCTION("spi1", spi1_groups, ARRAY_SIZE(spi1_groups)), - PINCTRL_PINFUNCTION("refclk0", refclk0_groups, ARRAY_SIZE(refclk0_groups)), + EQ5P_PINFUNCTION("timer0", eq5p_eyeq5_timer0_groups), + EQ5P_PINFUNCTION("timer1", eq5p_eyeq5_timer1_groups), + EQ5P_PINFUNCTION("timer2", eq5p_eyeq5_timer2_groups), + EQ5P_PINFUNCTION("timer5", eq5p_eyeq5_timer5_groups), + EQ5P_PINFUNCTION("uart0", eq5p_eyeq5_uart0_groups), + EQ5P_PINFUNCTION("uart1", eq5p_eyeq5_uart1_groups), + EQ5P_PINFUNCTION("can0", eq5p_eyeq5_can0_groups), + EQ5P_PINFUNCTION("can1", eq5p_eyeq5_can1_groups), + EQ5P_PINFUNCTION("spi0", eq5p_eyeq5_spi0_groups), + EQ5P_PINFUNCTION("spi1", eq5p_eyeq5_spi1_groups), + EQ5P_PINFUNCTION("refclk0", eq5p_eyeq5_refclk0_groups), /* Bank B functions */ - PINCTRL_PINFUNCTION("timer3", timer3_groups, ARRAY_SIZE(timer3_groups)), - PINCTRL_PINFUNCTION("timer4", timer4_groups, ARRAY_SIZE(timer4_groups)), - PINCTRL_PINFUNCTION("timer6", timer6_groups, ARRAY_SIZE(timer6_groups)), - PINCTRL_PINFUNCTION("uart2", uart2_groups, ARRAY_SIZE(uart2_groups)), - PINCTRL_PINFUNCTION("can2", can2_groups, ARRAY_SIZE(can2_groups)), - PINCTRL_PINFUNCTION("spi2", spi2_groups, ARRAY_SIZE(spi2_groups)), - PINCTRL_PINFUNCTION("spi3", spi3_groups, ARRAY_SIZE(spi3_groups)), - PINCTRL_PINFUNCTION("mclk0", mclk0_groups, ARRAY_SIZE(mclk0_groups)), + EQ5P_PINFUNCTION("timer3", eq5p_eyeq5_timer3_groups), + EQ5P_PINFUNCTION("timer4", eq5p_eyeq5_timer4_groups), + EQ5P_PINFUNCTION("timer6", eq5p_eyeq5_timer6_groups), + EQ5P_PINFUNCTION("uart2", eq5p_eyeq5_uart2_groups), + EQ5P_PINFUNCTION("can2", eq5p_eyeq5_can2_groups), + EQ5P_PINFUNCTION("spi2", eq5p_eyeq5_spi2_groups), + EQ5P_PINFUNCTION("spi3", eq5p_eyeq5_spi3_groups), + EQ5P_PINFUNCTION("mclk0", eq5p_eyeq5_mclk0_groups), +}; + +static const struct eq5p_bank eq5p_eyeq5_banks[] = { + { + .npins = EQ5P_EYEQ5_PIN_OFFSET_BANK_B, + .regs = {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0}, + }, + { + .npins = ARRAY_SIZE(eq5p_eyeq5_pins) - EQ5P_EYEQ5_PIN_OFFSET_BANK_B, + .regs = {0x0C8, 0x0CC, 0x0D8, 0x0DC, 0x0B4}, + }, +}; + +static const struct eq5p_match_data eq5p_eyeq5_data = { + .npins = ARRAY_SIZE(eq5p_eyeq5_pins), + .nfunctions = ARRAY_SIZE(eq5p_eyeq5_functions), + .nbanks = ARRAY_SIZE(eq5p_eyeq5_banks), + .pins = eq5p_eyeq5_pins, + .functions = eq5p_eyeq5_functions, + .banks = eq5p_eyeq5_banks, }; static void eq5p_update_bits(const struct eq5p_pinctrl *pctrl, - enum eq5p_bank bank, enum eq5p_regs reg, - u32 mask, u32 val) + const struct eq5p_bank *bank, + enum eq5p_regs reg, u32 mask, u32 val) { - void __iomem *ptr = pctrl->base + eq5p_regs[bank][reg]; + void __iomem *ptr = pctrl->base + bank->regs[reg]; writel((readl(ptr) & ~mask) | (val & mask), ptr); } static bool eq5p_test_bit(const struct eq5p_pinctrl *pctrl, - enum eq5p_bank bank, enum eq5p_regs reg, int offset) + const struct eq5p_bank *bank, + enum eq5p_regs reg, int offset) { - u32 val = readl(pctrl->base + eq5p_regs[bank][reg]); + u32 val = readl(pctrl->base + bank->regs[reg]); if (WARN_ON(offset > 31)) return false; @@ -218,25 +250,29 @@ static bool eq5p_test_bit(const struct eq5p_pinctrl *pctrl, return (val & BIT(offset)) != 0; } -static enum eq5p_bank eq5p_pin_to_bank(unsigned int pin) +static int eq5p_pin_to_bank_offset(const struct eq5p_pinctrl *pctrl, unsigned int pin, + const struct eq5p_bank **bank, unsigned int *offset) { - if (pin < EQ5P_PIN_OFFSET_BANK_B) - return EQ5P_BANK_A; - else - return EQ5P_BANK_B; -} + for (unsigned int i = 0; i < pctrl->data->nbanks; i++) { + const struct eq5p_bank *_bank = &pctrl->data->banks[i]; + unsigned int npins = _bank->npins; -static unsigned int eq5p_pin_to_offset(unsigned int pin) -{ - if (pin < EQ5P_PIN_OFFSET_BANK_B) - return pin; - else - return pin - EQ5P_PIN_OFFSET_BANK_B; + if (pin < npins) { + *bank = _bank; + *offset = pin; + return 0; + } + pin -= npins; + } + + return -EINVAL; } static int eq5p_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) { - return ARRAY_SIZE(eq5p_pins); + struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->npins; } static const char *eq5p_pinctrl_get_group_name(struct pinctrl_dev *pctldev, @@ -260,10 +296,15 @@ static int eq5p_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, { enum pin_config_param param = pinconf_to_config_param(*config); struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - unsigned int offset = eq5p_pin_to_offset(pin); - enum eq5p_bank bank = eq5p_pin_to_bank(pin); + const struct eq5p_bank *bank; + unsigned int offset; u32 val_ds, arg; bool pd, pu; + int ret; + + ret = eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset); + if (ret) + return ret; pd = eq5p_test_bit(pctrl, bank, EQ5P_PD, offset); pu = eq5p_test_bit(pctrl, bank, EQ5P_PU, offset); @@ -281,10 +322,10 @@ static int eq5p_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, case PIN_CONFIG_DRIVE_STRENGTH: offset *= 2; /* two bits per pin */ if (offset >= 32) { - val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_HIGH]); + val_ds = readl(pctrl->base + bank->regs[EQ5P_DS_HIGH]); offset -= 32; } else { - val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_LOW]); + val_ds = readl(pctrl->base + bank->regs[EQ5P_DS_LOW]); } arg = (val_ds >> offset) & EQ5P_DS_MASK; break; @@ -302,30 +343,35 @@ static void eq5p_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, { struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const char *pin_name = pctrl->desc.pins[pin].name; - unsigned int offset = eq5p_pin_to_offset(pin); - enum eq5p_bank bank = eq5p_pin_to_bank(pin); + const struct eq5p_bank *bank; const char *func_name, *bias; unsigned long ds_config; + unsigned int offset; u32 drive_strength; bool pd, pu; int i, j; + if (eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset)) { + seq_puts(s, "unknown pin"); + return; + } + /* * First, let's get the function name. All pins have only two functions: * GPIO (IOCR == 0) and something else (IOCR == 1). */ if (eq5p_test_bit(pctrl, bank, EQ5P_IOCR, offset)) { func_name = NULL; - for (i = 0; i < ARRAY_SIZE(eq5p_functions); i++) { - if (i == GPIO_FUNC_SELECTOR) + for (i = 0; i < pctrl->data->nfunctions; i++) { + if (i == EQ5P_GPIO_FUNC_SELECTOR) continue; - for (j = 0; j < eq5p_functions[i].ngroups; j++) { + for (j = 0; j < pctrl->data->functions[i].ngroups; j++) { /* Groups and pins are the same thing for us. */ - const char *x = eq5p_functions[i].groups[j]; + const char *x = pctrl->data->functions[i].groups[j]; if (strcmp(x, pin_name) == 0) { - func_name = eq5p_functions[i].name; + func_name = pctrl->data->functions[i].name; break; } } @@ -341,7 +387,7 @@ static void eq5p_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, if (!func_name) func_name = "unknown"; } else { - func_name = eq5p_functions[GPIO_FUNC_SELECTOR].name; + func_name = pctrl->data->functions[EQ5P_GPIO_FUNC_SELECTOR].name; } /* Second, we retrieve the bias. */ @@ -376,13 +422,17 @@ static const struct pinctrl_ops eq5p_pinctrl_ops = { static int eq5p_pinmux_get_functions_count(struct pinctrl_dev *pctldev) { - return ARRAY_SIZE(eq5p_functions); + struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->nfunctions; } static const char *eq5p_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector) { - return eq5p_functions[selector].name; + struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->functions[selector].name; } static int eq5p_pinmux_get_function_groups(struct pinctrl_dev *pctldev, @@ -390,8 +440,10 @@ static int eq5p_pinmux_get_function_groups(struct pinctrl_dev *pctldev, const char * const **groups, unsigned int *num_groups) { - *groups = eq5p_functions[selector].groups; - *num_groups = eq5p_functions[selector].ngroups; + struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctrl->data->functions[selector].groups; + *num_groups = pctrl->data->functions[selector].ngroups; return 0; } @@ -399,12 +451,17 @@ static int eq5p_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, unsigned int pin) { struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - const char *func_name = eq5p_functions[func_selector].name; + const char *func_name = pctrl->data->functions[func_selector].name; const char *group_name = pctldev->desc->pins[pin].name; - bool is_gpio = func_selector == GPIO_FUNC_SELECTOR; - unsigned int offset = eq5p_pin_to_offset(pin); - enum eq5p_bank bank = eq5p_pin_to_bank(pin); + bool is_gpio = func_selector == EQ5P_GPIO_FUNC_SELECTOR; + const struct eq5p_bank *bank; + unsigned int offset; u32 mask, val; + int ret; + + ret = eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset); + if (ret) + return ret; dev_dbg(pctldev->dev, "func=%s group=%s\n", func_name, group_name); @@ -419,7 +476,7 @@ static int eq5p_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, unsigned int pin) { /* Pin numbers and group selectors are the same thing in our case. */ - return eq5p_pinmux_set_mux(pctldev, GPIO_FUNC_SELECTOR, pin); + return eq5p_pinmux_set_mux(pctldev, EQ5P_GPIO_FUNC_SELECTOR, pin); } static const struct pinmux_ops eq5p_pinmux_ops = { @@ -435,10 +492,15 @@ static int eq5p_pinconf_set_drive_strength(struct pinctrl_dev *pctldev, unsigned int pin, u32 arg) { struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - unsigned int offset = eq5p_pin_to_offset(pin); - enum eq5p_bank bank = eq5p_pin_to_bank(pin); + const struct eq5p_bank *bank; + unsigned int offset; unsigned int reg; u32 mask, val; + int ret; + + ret = eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset); + if (ret) + return ret; if (arg & ~EQ5P_DS_MASK) { dev_err(pctldev->dev, "Unsupported drive strength: %u\n", arg); @@ -465,12 +527,18 @@ static int eq5p_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, { struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const char *pin_name = pctldev->desc->pins[pin].name; - unsigned int offset = eq5p_pin_to_offset(pin); - enum eq5p_bank bank = eq5p_pin_to_bank(pin); struct device *dev = pctldev->dev; - u32 val = BIT(offset); + const struct eq5p_bank *bank; + unsigned int offset; unsigned int i; + u32 val; + int ret; + ret = eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset); + if (ret) + return ret; + + val = BIT(offset); for (i = 0; i < num_configs; i++) { enum pin_config_param param = pinconf_to_config_param(configs[i]); u32 arg = pinconf_to_config_argument(configs[i]); @@ -533,19 +601,26 @@ static const struct pinconf_ops eq5p_pinconf_ops = { static int eq5p_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id) { + const struct of_device_id *match; struct device *dev = &adev->dev; struct pinctrl_dev *pctldev; struct eq5p_pinctrl *pctrl; int ret; + /* Get match data based on parent OF node set in clk-eyeq */ + match = of_match_node(dev->driver->of_match_table, dev->of_node); + if (!match || !match->data) + return -ENODEV; + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) return -ENOMEM; pctrl->base = (void __iomem *)dev_get_platdata(dev); + pctrl->data = match->data; pctrl->desc.name = dev_name(dev); - pctrl->desc.pins = eq5p_pins; - pctrl->desc.npins = ARRAY_SIZE(eq5p_pins); + pctrl->desc.pins = pctrl->data->pins; + pctrl->desc.npins = pctrl->data->npins; pctrl->desc.pctlops = &eq5p_pinctrl_ops; pctrl->desc.pmxops = &eq5p_pinmux_ops; pctrl->desc.confops = &eq5p_pinconf_ops; @@ -562,6 +637,12 @@ static int eq5p_probe(struct auxiliary_device *adev, return 0; } +static const struct of_device_id eq5p_match_table[] = { + { .compatible = "mobileye,eyeq5-olb", .data = &eq5p_eyeq5_data }, + {} +}; +MODULE_DEVICE_TABLE(of, eq5p_match_table); + static const struct auxiliary_device_id eq5p_id_table[] = { { .name = "clk_eyeq.pinctrl" }, {} @@ -571,5 +652,8 @@ MODULE_DEVICE_TABLE(auxiliary, eq5p_id_table); static struct auxiliary_driver eq5p_driver = { .probe = eq5p_probe, .id_table = eq5p_id_table, + .driver = { + .of_match_table = eq5p_match_table, + } }; module_auxiliary_driver(eq5p_driver); From e91d8e8c735cba92737f2a2fb73eb70fe4221048 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Monin?= Date: Thu, 26 Feb 2026 14:33:50 +0100 Subject: [PATCH 24/84] pinctrl: eyeq5: Add Mobileye EyeQ6Lplus OLB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the match data for the pinctrl found in the EyeQ6Lplus OLB. The pin control is identical in function to the one present in the EyeQ5 but has a single bank of 32 pins. Signed-off-by: Benoît Monin Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 4 +- drivers/pinctrl/pinctrl-eyeq5.c | 95 +++++++++++++++++++++++++++++++++ 2 files changed, 97 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 1965d4fb461d..4bafe1dff195 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -254,11 +254,11 @@ config PINCTRL_EQUILIBRIUM config PINCTRL_EYEQ5 bool "Mobileye EyeQ5 pinctrl driver" depends on OF - depends on MACH_EYEQ5 || COMPILE_TEST + depends on MACH_EYEQ5 || MACH_EYEQ6LPLUS || COMPILE_TEST select PINMUX select GENERIC_PINCONF select AUXILIARY_BUS - default MACH_EYEQ5 + default MACH_EYEQ5 || MACH_EYEQ6LPLUS help Pin controller driver for the Mobileye EyeQ5 platform. It does both pin config & pin muxing. It does not handle GPIO. diff --git a/drivers/pinctrl/pinctrl-eyeq5.c b/drivers/pinctrl/pinctrl-eyeq5.c index c780af09cde9..dcdf80f07a90 100644 --- a/drivers/pinctrl/pinctrl-eyeq5.c +++ b/drivers/pinctrl/pinctrl-eyeq5.c @@ -229,6 +229,100 @@ static const struct eq5p_match_data eq5p_eyeq5_data = { .banks = eq5p_eyeq5_banks, }; +static const struct pinctrl_pin_desc eq5p_eyeq6lplus_pins[] = { + PINCTRL_PIN(0, "PA0"), /* GPIO_A0_TIMER0_CK0 */ + PINCTRL_PIN(1, "PA1"), /* GPIO_A1_TIMER0_EOC */ + PINCTRL_PIN(2, "PA2"), /* GPIO_A2_TIMER1_CK */ + PINCTRL_PIN(3, "PA3"), /* GPIO_A3_TIMER1_EOC1 */ + PINCTRL_PIN(4, "PA4"), /* GPIO_A4_SSI_UART_RX */ + PINCTRL_PIN(5, "PA5"), /* GPIO_A5_SSI_UART_TX */ + PINCTRL_PIN(6, "PA6"), /* GPIO_A6_SPI_0_CS */ + PINCTRL_PIN(7, "PA7"), /* GPIO_A7_SPI_0_DI */ + PINCTRL_PIN(8, "PA8"), /* GPIO_A8_SPI_0_CK */ + PINCTRL_PIN(9, "PA9"), /* GPIO_A9_SPI_0_DO */ + PINCTRL_PIN(10, "PA10"), /* GPIO_A10_SPI_0_CS1 */ + PINCTRL_PIN(11, "PA11"), /* GPIO_A11_UART_0_RX */ + PINCTRL_PIN(12, "PA12"), /* GPIO_A12_UART_0_TX */ + PINCTRL_PIN(13, "PA13"), /* GPIO_A13_TIMER2_CK */ + PINCTRL_PIN(14, "PA14"), /* GPIO_A14_TIMER2_EOC */ + PINCTRL_PIN(15, "PA15"), /* GPIO_A15_TIMER3_CK */ + PINCTRL_PIN(16, "PA16"), /* GPIO_A16_TIMER_EOC */ + PINCTRL_PIN(17, "PA17"), /* GPIO_A17_TIMER_EXT0_INCA P1 */ + PINCTRL_PIN(18, "PA18"), /* GPIO_A18_TIMER_EXT0_INCA P2 */ + PINCTRL_PIN(19, "PA19"), /* GPIO_A19_TIMER_EXT0_OUT CMP1 */ + PINCTRL_PIN(20, "PA20"), /* GPIO_A20_TIMER_EXT0_OUT CMP2 */ + PINCTRL_PIN(21, "PA21"), /* GPIO_A21_SPI_1_CS0 */ + PINCTRL_PIN(22, "PA22"), /* GPIO_A22_SPI_1_DI */ + PINCTRL_PIN(23, "PA23"), /* GPIO_A23_SPI_1_CK */ + PINCTRL_PIN(24, "PA24"), /* GPIO_A24_SPI_1_DO */ + PINCTRL_PIN(25, "PA25"), /* GPIO_A25_SPI_1_CS1 */ + PINCTRL_PIN(26, "PA26"), /* GPIO_A26_TIMER_EXT1_INCA P1 */ + PINCTRL_PIN(27, "PA27"), /* GPIO_A27_TIMER_EXT1_INCA P2 */ + PINCTRL_PIN(28, "PA28"), /* GPIO_A28_TIMER_EXT1_OUTC MP1 */ + PINCTRL_PIN(29, "PA29"), /* GPIO_A29_TIMER_EXT1_OUTC MP2 */ + PINCTRL_PIN(30, "PA30"), /* GPIO_A30_EXT_CLK */ + PINCTRL_PIN(31, "PA31"), /* GPIO_A31_VDI_MCLK */ +}; + +static const char * const eq5p_eyeq6lplus_gpio_groups[] = { + /* Bank A */ + "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", + "PA8", "PA9", "PA10", "PA11", "PA12", "PA13", "PA14", "PA15", + "PA16", "PA17", "PA18", "PA19", "PA20", "PA21", "PA22", "PA23", + "PA24", "PA25", "PA26", "PA27", "PA28", "PA29", "PA30", "PA31", +}; + +/* Groups of functions on bank A */ +static const char * const eq5p_eyeq6lplus_timer0_groups[] = { "PA0", "PA1" }; +static const char * const eq5p_eyeq6lplus_timer1_groups[] = { "PA2", "PA3" }; +static const char * const eq5p_eyeq6lplus_uart_ssi_groups[] = { "PA4", "PA5" }; +static const char * const eq5p_eyeq6lplus_spi0_groups[] = { "PA6", "PA7", "PA8", "PA9", "PA10" }; +static const char * const eq5p_eyeq6lplus_uart0_groups[] = { "PA11", "PA12" }; +static const char * const eq5p_eyeq6lplus_timer2_groups[] = { "PA13", "PA14" }; +static const char * const eq5p_eyeq6lplus_timer3_groups[] = { "PA15", "PA16" }; +static const char * const eq5p_eyeq6lplus_timer_ext0_groups[] = { "PA17", "PA18", "PA19", "PA20" }; +static const char * const eq5p_eyeq6lplus_spi1_groups[] = { + "PA21", "PA22", "PA23", "PA24", "PA25" +}; +static const char * const eq5p_eyeq6lplus_timer_ext1_groups[] = { "PA26", "PA27", "PA28", "PA29" }; +static const char * const eq5p_eyeq6lplus_ext_ref_clk_groups[] = { "PA30" }; +static const char * const eq5p_eyeq6lplus_mipi_ref_clk_groups[] = { "PA31" }; + +static const struct pinfunction eq5p_eyeq6lplus_functions[] = { + /* gpios function */ + EQ5P_PINFUNCTION("gpio", eq5p_eyeq6lplus_gpio_groups), + + /* Bank A alternate functions */ + EQ5P_PINFUNCTION("timer0", eq5p_eyeq6lplus_timer0_groups), + EQ5P_PINFUNCTION("timer1", eq5p_eyeq6lplus_timer1_groups), + EQ5P_PINFUNCTION("uart_ssi", eq5p_eyeq6lplus_uart_ssi_groups), + EQ5P_PINFUNCTION("spi0", eq5p_eyeq6lplus_spi0_groups), + EQ5P_PINFUNCTION("uart0", eq5p_eyeq6lplus_uart0_groups), + EQ5P_PINFUNCTION("timer2", eq5p_eyeq6lplus_timer2_groups), + EQ5P_PINFUNCTION("timer3", eq5p_eyeq6lplus_timer3_groups), + EQ5P_PINFUNCTION("timer_ext0", eq5p_eyeq6lplus_timer_ext0_groups), + EQ5P_PINFUNCTION("spi1", eq5p_eyeq6lplus_spi1_groups), + EQ5P_PINFUNCTION("timer_ext1", eq5p_eyeq6lplus_timer_ext1_groups), + EQ5P_PINFUNCTION("ext_ref_clk", eq5p_eyeq6lplus_ext_ref_clk_groups), + EQ5P_PINFUNCTION("mipi_ref_clk", eq5p_eyeq6lplus_mipi_ref_clk_groups), +}; + +static const struct eq5p_bank eq5p_eyeq6lplus_banks[] = { + { + .npins = ARRAY_SIZE(eq5p_eyeq6lplus_pins), + .regs = {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0}, + }, +}; + +static const struct eq5p_match_data eq5p_eyeq6lplus_data = { + .npins = ARRAY_SIZE(eq5p_eyeq6lplus_pins), + .nfunctions = ARRAY_SIZE(eq5p_eyeq6lplus_functions), + .nbanks = ARRAY_SIZE(eq5p_eyeq6lplus_banks), + .pins = eq5p_eyeq6lplus_pins, + .functions = eq5p_eyeq6lplus_functions, + .banks = eq5p_eyeq6lplus_banks, +}; + static void eq5p_update_bits(const struct eq5p_pinctrl *pctrl, const struct eq5p_bank *bank, enum eq5p_regs reg, u32 mask, u32 val) @@ -639,6 +733,7 @@ static int eq5p_probe(struct auxiliary_device *adev, static const struct of_device_id eq5p_match_table[] = { { .compatible = "mobileye,eyeq5-olb", .data = &eq5p_eyeq5_data }, + { .compatible = "mobileye,eyeq6lplus-olb", .data = &eq5p_eyeq6lplus_data }, {} }; MODULE_DEVICE_TABLE(of, eq5p_match_table); From a92b75100826b1ea27e6b8a678e53970ad4736d7 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Fri, 27 Feb 2026 15:15:54 +0100 Subject: [PATCH 25/84] dt-bindings: pinctrl: marvell,armada3710-xb-pinctrl: add missing items keyword Even though the type of the 'groups' property of a pinmux node is specified as string-array in pinmux-node.yaml, but trying to use multiple strings causes dtbs_check warnings. For example, checking the following dts ... $ cat arch/arm64/boot/dts/marvell/armada-3720-test.dts /dts-v1/; #include "armada-372x.dtsi" &pinctrl_nb { pwm-gpio-pins { groups = "pwm0", "pwm1", "pwm2", "pwm3"; function = "gpio"; }; }; ... results in this warning: arch/arm64/boot/dts/marvell/armada-3720-test.dtb: pinctrl@13800 (marvell,armada3710-nb-pinctrl): pwm-gpio-pins:groups: ['pwm0', 'pwm1', 'pwm2', 'pwm3'] is too long from schema $id: http://devicetree.org/schemas/pinctrl/marvell,armada3710-xb-pinctrl.yaml Add the missing 'items' keyword to the schema to allow using multiple strings without such warnings. Also adjust the indentation of the next statements accordingly. Signed-off-by: Gabor Juhos Acked-by: Conor Dooley Fixes: c1c9641a04e83 ("dt-bindings: pinctrl: Convert marvell,armada-3710-(sb|nb)-pinctrl to DT schema") Reviewed-by: Miquel Raynal Signed-off-by: Linus Walleij --- .../pinctrl/marvell,armada3710-xb-pinctrl.yaml | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml index 4f9013d36874..727da7fb490c 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml @@ -84,11 +84,12 @@ patternProperties: properties: groups: - enum: [ emmc_nb, i2c1, i2c2, jtag, mii_col, onewire, pcie1, - pcie1_clkreq, pcie1_wakeup, pmic0, pmic1, ptp, ptp_clk, - ptp_trig, pwm0, pwm1, pwm2, pwm3, rgmii, sdio0, sdio_sb, smi, - spi_cs1, spi_cs2, spi_cs3, spi_quad, uart1, uart2, - usb2_drvvbus1, usb32_drvvbus0 ] + items: + enum: [ emmc_nb, i2c1, i2c2, jtag, mii_col, onewire, pcie1, + pcie1_clkreq, pcie1_wakeup, pmic0, pmic1, ptp, ptp_clk, + ptp_trig, pwm0, pwm1, pwm2, pwm3, rgmii, sdio0, sdio_sb, + smi, spi_cs1, spi_cs2, spi_cs3, spi_quad, uart1, uart2, + usb2_drvvbus1, usb32_drvvbus0 ] function: enum: [ drvbus, emmc, gpio, i2c, jtag, led, mii, mii_err, onewire, From fe5560688f3ba98364c7de7b4f8dc240ffd1ff75 Mon Sep 17 00:00:00 2001 From: Ethan Tidmore Date: Fri, 27 Feb 2026 15:56:23 -0600 Subject: [PATCH 26/84] pinctrl: pinctrl-pic32: Fix resource leak Fix three possible resource leaks by using the devres version of clk_prepare_enable(). Also, update error message accordingly. Detected by Smatch: drivers/pinctrl/pinctrl-pic32.c:2211 pic32_pinctrl_probe() warn: 'pctl->clk' from clk_prepare_enable() not released on lines: 2208. drivers/pinctrl/pinctrl-pic32.c:2274 pic32_gpio_probe() warn: 'bank->clk' from clk_prepare_enable() not released on lines: 2264,2272. Fixes: 2ba384e6c3810 ("pinctrl: pinctrl-pic32: Add PIC32 pin control driver") Signed-off-by: Ethan Tidmore Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-pic32.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/pinctrl-pic32.c b/drivers/pinctrl/pinctrl-pic32.c index eb438c9d9667..d185fe48dc0d 100644 --- a/drivers/pinctrl/pinctrl-pic32.c +++ b/drivers/pinctrl/pinctrl-pic32.c @@ -2174,16 +2174,10 @@ static int pic32_pinctrl_probe(struct platform_device *pdev) if (IS_ERR(pctl->reg_base)) return PTR_ERR(pctl->reg_base); - pctl->clk = devm_clk_get(&pdev->dev, NULL); + pctl->clk = devm_clk_get_enabled(&pdev->dev, NULL); if (IS_ERR(pctl->clk)) { ret = PTR_ERR(pctl->clk); - dev_err(&pdev->dev, "clk get failed\n"); - return ret; - } - - ret = clk_prepare_enable(pctl->clk); - if (ret) { - dev_err(&pdev->dev, "clk enable failed\n"); + dev_err(&pdev->dev, "Failed to get and enable clock\n"); return ret; } @@ -2239,16 +2233,10 @@ static int pic32_gpio_probe(struct platform_device *pdev) if (irq < 0) return irq; - bank->clk = devm_clk_get(&pdev->dev, NULL); + bank->clk = devm_clk_get_enabled(&pdev->dev, NULL); if (IS_ERR(bank->clk)) { ret = PTR_ERR(bank->clk); - dev_err(&pdev->dev, "clk get failed\n"); - return ret; - } - - ret = clk_prepare_enable(bank->clk); - if (ret) { - dev_err(&pdev->dev, "clk enable failed\n"); + dev_err(&pdev->dev, "Failed to get and enable clock\n"); return ret; } From f08061d267d2061f64d514c1ecbe441a063a6fad Mon Sep 17 00:00:00 2001 From: Ethan Tidmore Date: Fri, 27 Feb 2026 15:56:24 -0600 Subject: [PATCH 27/84] pinctrl: pinctrl-pic32: Use devres version of gpiochip_add_data() Convert gpiochip_add_data() to devm_gpiochip_add_data() to use devres style cleanup across entire driver. Suggested-by: Linus Walleij Signed-off-by: Ethan Tidmore Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-pic32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-pic32.c b/drivers/pinctrl/pinctrl-pic32.c index d185fe48dc0d..07a24e17d35b 100644 --- a/drivers/pinctrl/pinctrl-pic32.c +++ b/drivers/pinctrl/pinctrl-pic32.c @@ -2253,7 +2253,7 @@ static int pic32_gpio_probe(struct platform_device *pdev) girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_level_irq; girq->parents[0] = irq; - ret = gpiochip_add_data(&bank->gpio_chip, bank); + ret = devm_gpiochip_add_data(&pdev->dev, &bank->gpio_chip, bank); if (ret < 0) { dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n", id, ret); From cc2f5e2aeb6c69556837e45756b3ddded98b3898 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sat, 28 Feb 2026 17:48:02 -0800 Subject: [PATCH 28/84] pinctrl: pinconf-generic: fix an enum name description Correct an enum name in a kernel-doc comment to avoid kernel-doc warnings: Warning: include/linux/pinctrl/pinconf-generic.h:161 Enum value 'PIN_CONFIG_SKEW_DELAY_OUTPUT_PS' not described in enum 'pin_config_param' Warning: include/linux/pinctrl/pinconf-generic.h:161 Excess enum value '@PIN_CONFIG_SKEW_DELAY_OUPUT_PS' description in 'pin_config_param' Signed-off-by: Randy Dunlap Signed-off-by: Linus Walleij --- include/linux/pinctrl/pinconf-generic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index 89277808ea61..531dc3e9b3f7 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -115,7 +115,7 @@ struct pinctrl_map; * @PIN_CONFIG_SKEW_DELAY_INPUT_PS: if the pin has independent values for the * programmable skew rate (on inputs) and latch delay (on outputs), then * this parameter specifies the clock skew only. The argument is in ps. - * @PIN_CONFIG_SKEW_DELAY_OUPUT_PS: if the pin has independent values for the + * @PIN_CONFIG_SKEW_DELAY_OUTPUT_PS: if the pin has independent values for the * programmable skew rate (on inputs) and latch delay (on outputs), then * this parameter specifies the latch delay only. The argument is in ps. * @PIN_CONFIG_SLEEP_HARDWARE_STATE: indicate this is sleep related state. From 33d4feff673bb32d3c94a6f25e7ca0be966ef410 Mon Sep 17 00:00:00 2001 From: Michal Piekos Date: Sun, 1 Mar 2026 17:46:31 +0100 Subject: [PATCH 29/84] pinctrl: core: use dev_err_probe() when applying state When applying a pinctrl state, -EPROBE_DEFER may be returned if dependencies are not ready and the consumer will retry probing. This is normal probe ordering behaviour and not a real error. However, pinctrl core currently logs: "Error applying setting, reverse things back" even when the return value is -EPROBE_DEFER, resulting in noisy boot-time error messages. Replace dev_err() with dev_err_probe() to handle -EPROBE_DEFER consistently and suppress error logging for deferred probes. No functional change intended. Signed-off-by: Michal Piekos Signed-off-by: Linus Walleij --- drivers/pinctrl/core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index b5e97689589f..2edc9bdad183 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -1350,7 +1350,8 @@ static int pinctrl_commit_state(struct pinctrl *p, struct pinctrl_state *state) goto restore_old_state; unapply_new_state: - dev_err(p->dev, "Error applying setting, reverse things back\n"); + dev_err_probe(p->dev, ret, + "Error applying setting, reverse things back\n"); /* * All we can do here is pinmux_disable_setting. From 8f72335002db29fb593f8c2c25761feb3b947eb3 Mon Sep 17 00:00:00 2001 From: Felix Gu Date: Tue, 3 Mar 2026 02:13:17 +0800 Subject: [PATCH 30/84] pinctrl: microchip-mssio: Fix missing return in probe In mpfs_pinctrl_probe(), when pctrl->regmap fails, it just print out an error message without return, which could lead serious errors. Fixes: 488d704ed7b7 ("pinctrl: add polarfire soc mssio pinctrl driver") Signed-off-by: Felix Gu Reviewed-by: Conor Dooley Signed-off-by: Linus Walleij --- drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c b/drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c index 3d5ffd6cb14b..15d73ea1028c 100644 --- a/drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c +++ b/drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c @@ -686,7 +686,7 @@ static int mpfs_pinctrl_probe(struct platform_device *pdev) pctrl->regmap = device_node_to_regmap(pdev->dev.parent->of_node); if (IS_ERR(pctrl->regmap)) - dev_err_probe(dev, PTR_ERR(pctrl->regmap), "Failed to find syscon regmap\n"); + return dev_err_probe(dev, PTR_ERR(pctrl->regmap), "Failed to find syscon regmap\n"); pctrl->sysreg_regmap = syscon_regmap_lookup_by_compatible("microchip,mpfs-sysreg-scb"); if (IS_ERR(pctrl->sysreg_regmap)) From bf64b1bae2a555043c8360836c6e708339ac078f Mon Sep 17 00:00:00 2001 From: Matthijs Kooijman Date: Mon, 2 Mar 2026 21:17:17 +0100 Subject: [PATCH 31/84] gpio: rockchip: Call pinctrl for gpio config Pinctrl is responsible for bias settings and possibly other pin config, so call gpiochip_generic_config to apply such config values. This might also include settings that pinctrl does not support, but then it can return ENOTSUPP as appropriate. Signed-off-by: Matthijs Kooijman Signed-off-by: Linus Walleij --- drivers/gpio/gpio-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c index 0fff4a699f12..ac1b939283eb 100644 --- a/drivers/gpio/gpio-rockchip.c +++ b/drivers/gpio/gpio-rockchip.c @@ -296,7 +296,7 @@ static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, */ return -ENOTSUPP; default: - return -ENOTSUPP; + return gpiochip_generic_config(gc, offset, config); } } From e785c990adccabb9cc3286166b2377fae05c2533 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 4 Mar 2026 10:02:28 +0100 Subject: [PATCH 32/84] pinctrl: Kconfig: drop unneeded dependencies on OF_GPIO OF_GPIO is selected automatically on all OF systems. Any symbols it controls also provide stubs so there's really no reason to select it explicitly. Signed-off-by: Bartosz Golaszewski Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 9 --------- drivers/pinctrl/bcm/Kconfig | 4 ++-- drivers/pinctrl/meson/Kconfig | 1 - drivers/pinctrl/starfive/Kconfig | 2 -- drivers/pinctrl/sunplus/Kconfig | 1 - 5 files changed, 2 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 4bafe1dff195..03f2e3ee065f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -77,7 +77,6 @@ config PINCTRL_APPLE_GPIO select GPIOLIB_IRQCHIP select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS - select OF_GPIO help This is the driver for the GPIO controller found on Apple ARM SoCs, including M1. @@ -126,7 +125,6 @@ config PINCTRL_AT91PIO4 select GENERIC_PINCONF select GPIOLIB select GPIOLIB_IRQCHIP - select OF_GPIO help Say Y here to enable the at91 pinctrl/gpio driver for Atmel PIO4 controller available on sama5d2 SoC. @@ -293,7 +291,6 @@ config PINCTRL_K210 select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF select GPIOLIB - select OF_GPIO select REGMAP_MMIO default SOC_CANAAN_K210 help @@ -419,7 +416,6 @@ config PINCTRL_MICROCHIP_SGPIO select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS - select OF_GPIO help Support for the serial GPIO interface used on Microsemi and Microchip SoCs. By using a serial interface, the SIO @@ -441,7 +437,6 @@ config PINCTRL_OCELOT select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS - select OF_GPIO select REGMAP_MMIO help Support for the internal GPIO interfaces on Microsemi Ocelot and @@ -482,7 +477,6 @@ config PINCTRL_PIC32 select PINMUX select GENERIC_PINCONF select GPIOLIB_IRQCHIP - select OF_GPIO help This is the pin controller and gpio driver for Microchip PIC32 microcontrollers. This option is selected automatically when specific @@ -499,7 +493,6 @@ config PINCTRL_PISTACHIO select PINMUX select GENERIC_PINCONF select GPIOLIB_IRQCHIP - select OF_GPIO help This support pinctrl and GPIO driver for IMG Pistachio SoC. @@ -521,7 +514,6 @@ config PINCTRL_ROCKCHIP select GENERIC_PINCONF select GENERIC_IRQ_CHIP select MFD_SYSCON - select OF_GPIO default ARCH_ROCKCHIP help This support pinctrl and GPIO driver for Rockchip SoCs. @@ -557,7 +549,6 @@ config PINCTRL_ST config PINCTRL_STMFX tristate "STMicroelectronics STMFX GPIO expander pinctrl driver" depends on I2C - depends on OF_GPIO depends on HAS_IOMEM select GENERIC_PINCONF select GPIOLIB_IRQCHIP diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig index 096d0778427e..206f3f1249cf 100644 --- a/drivers/pinctrl/bcm/Kconfig +++ b/drivers/pinctrl/bcm/Kconfig @@ -120,7 +120,7 @@ source "drivers/pinctrl/bcm/Kconfig.stb" config PINCTRL_IPROC_GPIO bool "Broadcom iProc GPIO (with PINCONF) driver" - depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST) + depends on ARCH_BCM_IPROC || COMPILE_TEST select GPIOLIB_IRQCHIP select PINCONF select GENERIC_PINCONF @@ -185,7 +185,7 @@ config PINCTRL_NS config PINCTRL_NSP_GPIO bool "Broadcom NSP GPIO (with PINCONF) driver" - depends on OF_GPIO && (ARCH_BCM_NSP || COMPILE_TEST) + depends on ARCH_BCM_NSP || COMPILE_TEST select GPIOLIB_IRQCHIP select PINCONF select GENERIC_PINCONF diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig index ce6aeec2fc79..1af4fc320f42 100644 --- a/drivers/pinctrl/meson/Kconfig +++ b/drivers/pinctrl/meson/Kconfig @@ -8,7 +8,6 @@ menuconfig PINCTRL_MESON select PINCONF select GENERIC_PINCONF select GPIOLIB - select OF_GPIO select REGMAP_MMIO if PINCTRL_MESON diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index 8192ac2087fc..a9a7cb101684 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -9,7 +9,6 @@ config PINCTRL_STARFIVE_JH7100 select GENERIC_PINCONF select GPIOLIB select GPIOLIB_IRQCHIP - select OF_GPIO default SOC_STARFIVE help Say yes here to support pin control on the StarFive JH7100 SoC. @@ -24,7 +23,6 @@ config PINCTRL_STARFIVE_JH7110 select GENERIC_PINCONF select GPIOLIB select GPIOLIB_IRQCHIP - select OF_GPIO config PINCTRL_STARFIVE_JH7110_SYS tristate "System pinctrl and GPIO driver for the StarFive JH7110 SoC" diff --git a/drivers/pinctrl/sunplus/Kconfig b/drivers/pinctrl/sunplus/Kconfig index 4b5c47c193d9..69f82590f6d2 100644 --- a/drivers/pinctrl/sunplus/Kconfig +++ b/drivers/pinctrl/sunplus/Kconfig @@ -13,7 +13,6 @@ config PINCTRL_SPPCTL select PINCONF select PINMUX select GPIOLIB - select OF_GPIO help Say Y here to support Sunplus SP7021 pinmux controller. This driver requires the pinctrl framework. From 35b9b024db9d762952c45bf3bb7007c5aaaddcb6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 5 Mar 2026 10:05:12 +0100 Subject: [PATCH 33/84] pinctrl: imx: PINCTRL_IMX_SCMI should depend on ARCH_MXC i.MX95 SCMI firmware is only present on NXP i.MX94 and i.MX95 SoCs. Hence add a dependency on ARCH_MXC, to prevent asking the user about this driver when configuring a kernel without NXP i.MX SoC family support. While at it, relax the dependencies on ARM_SCMI_PROTOCOL and OF when compile-testing. Signed-off-by: Geert Uytterhoeven Reviewed-by: Peng Fan Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index 8d24decd3f07..fd53cf5bb843 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -9,7 +9,7 @@ config PINCTRL_IMX config PINCTRL_IMX_SCMI tristate "i.MX95 pinctrl driver using SCMI protocol interface" - depends on ARM_SCMI_PROTOCOL && OF + depends on (ARM_SCMI_PROTOCOL && OF && ARCH_MXC) || COMPILE_TEST select PINMUX select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS From e002d162654b74fad60a0f85e8fdb1a6c8a903f5 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 5 Mar 2026 10:50:14 +0100 Subject: [PATCH 34/84] pinctrl: pinconf-generic: Use only fwnode API in parse_dt_cfg() The parse_dt_cfg() uses OF and fwnode APIs. Fix this inconsistency by fully switching it to use fwnode API and rename the function accordingly. While at it, add missing linux/property.h inclusion. Signed-off-by: Andy Shevchenko Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf-generic.c | 34 ++++++++++++++++--------------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 901a225f3531..855ca973a1c8 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -205,19 +206,19 @@ static const struct pinconf_generic_params dt_params[] = { }; /** - * parse_dt_cfg() - Parse DT pinconf parameters - * @np: DT node + * parse_fw_cfg() - Parse firmware pinconf parameters + * @fwnode: firmware node * @params: Array of describing generic parameters * @count: Number of entries in @params * @cfg: Array of parsed config options * @ncfg: Number of entries in @cfg * - * Parse the config options described in @params from @np and puts the result + * Parse the config options described in @params from @fwnode and puts the result * in @cfg. @cfg does not need to be empty, entries are added beginning at * @ncfg. @ncfg is updated to reflect the number of entries after parsing. @cfg * needs to have enough memory allocated to hold all possible entries. */ -static int parse_dt_cfg(struct device_node *np, +static int parse_fw_cfg(struct fwnode_handle *fwnode, const struct pinconf_generic_params *params, unsigned int count, unsigned long *cfg, unsigned int *ncfg) @@ -233,7 +234,7 @@ static int parse_dt_cfg(struct device_node *np, const struct pinconf_generic_params *par = ¶ms[i]; if (par->values && par->num_values) { - ret = fwnode_property_match_property_string(of_fwnode_handle(np), + ret = fwnode_property_match_property_string(fwnode, par->property, par->values, par->num_values); if (ret == -ENOENT) @@ -243,7 +244,7 @@ static int parse_dt_cfg(struct device_node *np, ret = 0; } } else { - ret = of_property_read_u32(np, par->property, &val); + ret = fwnode_property_read_u32(fwnode, par->property, &val); } /* property not found */ @@ -258,8 +259,8 @@ static int parse_dt_cfg(struct device_node *np, if (par->param <= count) { ret = test_and_set_bit(par->param, properties); if (ret) { - pr_err("%s: conflicting setting detected for %s\n", - np->name, par->property); + pr_err("%pfw: conflicting setting detected for %s\n", + fwnode, par->property); bitmap_free(properties); return -EINVAL; } @@ -272,8 +273,8 @@ static int parse_dt_cfg(struct device_node *np, if (test_bit(PIN_CONFIG_DRIVE_STRENGTH, properties) && test_bit(PIN_CONFIG_DRIVE_STRENGTH_UA, properties)) - pr_err("%s: cannot have multiple drive strength properties\n", - np->name); + pr_err("%pfw: cannot have multiple drive strength properties\n", + fwnode); test = test_bit(PIN_CONFIG_BIAS_BUS_HOLD, properties) + test_bit(PIN_CONFIG_BIAS_DISABLE, properties) + @@ -282,15 +283,15 @@ static int parse_dt_cfg(struct device_node *np, test_bit(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, properties) + test_bit(PIN_CONFIG_BIAS_PULL_DOWN, properties); if (test > 1) - pr_err("%s: cannot have multiple bias configurations\n", - np->name); + pr_err("%pfw: cannot have multiple bias configurations\n", + fwnode); test = test_bit(PIN_CONFIG_DRIVE_OPEN_DRAIN, properties) + test_bit(PIN_CONFIG_DRIVE_OPEN_SOURCE, properties) + test_bit(PIN_CONFIG_DRIVE_PUSH_PULL, properties); if (test > 1) - pr_err("%s: cannot have multiple drive configurations\n", - np->name); + pr_err("%pfw: cannot have multiple drive configurations\n", + fwnode); bitmap_free(properties); return 0; @@ -371,6 +372,7 @@ int pinconf_generic_parse_dt_config(struct device_node *np, unsigned long **configs, unsigned int *nconfigs) { + struct fwnode_handle *fwnode = of_fwnode_handle(np); unsigned long *cfg; unsigned int max_cfg, ncfg = 0; int ret; @@ -386,12 +388,12 @@ int pinconf_generic_parse_dt_config(struct device_node *np, if (!cfg) return -ENOMEM; - ret = parse_dt_cfg(np, dt_params, ARRAY_SIZE(dt_params), cfg, &ncfg); + ret = parse_fw_cfg(fwnode, dt_params, ARRAY_SIZE(dt_params), cfg, &ncfg); if (ret) return ret; if (pctldev && pctldev->desc->num_custom_params && pctldev->desc->custom_params) { - ret = parse_dt_cfg(np, pctldev->desc->custom_params, + ret = parse_fw_cfg(fwnode, pctldev->desc->custom_params, pctldev->desc->num_custom_params, cfg, &ncfg); if (ret) return ret; From 24f2baec82279d86a52e7d5d330c9afd65899b30 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Thu, 5 Mar 2026 22:34:11 -0800 Subject: [PATCH 35/84] pinctrl: s32: correct kernel-doc bad line warning Insert a "*" in the kernel-doc line to resolve a warning: Warning: drivers/pinctrl/nxp/pinctrl-s32.h:18 bad line: this group. Signed-off-by: Randy Dunlap Acked-by: Dong Aisheng Signed-off-by: Linus Walleij --- drivers/pinctrl/nxp/pinctrl-s32.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/nxp/pinctrl-s32.h b/drivers/pinctrl/nxp/pinctrl-s32.h index add3c77ddfed..8715befd5f05 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32.h +++ b/drivers/pinctrl/nxp/pinctrl-s32.h @@ -16,7 +16,7 @@ struct platform_device; /** * struct s32_pin_group - describes an S32 pin group * @data: generic data describes group name, number of pins, and a pin array in - this group. + * this group. * @pin_sss: an array of source signal select configs paired with pin array. */ struct s32_pin_group { From a248904e3030926ddba1d7cd32db742a368242bc Mon Sep 17 00:00:00 2001 From: Yu-Chun Lin Date: Fri, 6 Mar 2026 15:52:31 +0800 Subject: [PATCH 36/84] pinctrl: realtek: Cleanup license string Prefer "GPL" over "GPL v2" - see commit bf7fbeeae6db ("module: Cure the MODULE_LICENSE "GPL" vs. "GPL v2" bogosity") Reviewed-by: Bartosz Golaszewski Signed-off-by: Yu-Chun Lin Signed-off-by: Linus Walleij --- drivers/pinctrl/realtek/pinctrl-rtd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c index 244060486332..eafa0d7bb19d 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd.c +++ b/drivers/pinctrl/realtek/pinctrl-rtd.c @@ -593,4 +593,4 @@ int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_des EXPORT_SYMBOL(rtd_pinctrl_probe); MODULE_DESCRIPTION("Realtek DHC SoC pinctrl driver"); -MODULE_LICENSE("GPL v2"); +MODULE_LICENSE("GPL"); From 6a6b238c66dc69cd784baf03b170c50f7e5f24d9 Mon Sep 17 00:00:00 2001 From: Tzuyi Chang Date: Fri, 6 Mar 2026 15:52:32 +0800 Subject: [PATCH 37/84] pinctrl: realtek: Fix return value and silence log for unsupported configs Treating unsupported configurations as errors causes upper layers (like the GPIO subsystem) to interpret optional features as hard failures, aborting operations or printing unnecessary error logs. For example, during gpiod_get(), the GPIO framework attempts to set PIN_CONFIG_PERSIST_STATE. Since this driver does not support it, false error reports are generated in dmesg. Fix this by returning -ENOTSUPP and demoting the log level to dev_dbg. Reviewed-by: Bartosz Golaszewski Signed-off-by: Tzuyi Chang Signed-off-by: Yu-Chun Lin Signed-off-by: Linus Walleij --- drivers/pinctrl/realtek/pinctrl-rtd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c index eafa0d7bb19d..41e7f5c2bf74 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd.c +++ b/drivers/pinctrl/realtek/pinctrl-rtd.c @@ -456,8 +456,8 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, break; default: - dev_err(data->dev, "unsupported pinconf: %d\n", (u32)param); - return -EINVAL; + dev_dbg(data->dev, "unsupported pinconf: %d\n", (u32)param); + return -ENOTSUPP; } ret = regmap_update_bits(data->regmap_pinctrl, reg_off, mask, val); From b7f698b22b8be5e25839d2dcfc6a6889c9ef196b Mon Sep 17 00:00:00 2001 From: Yu-Chun Lin Date: Fri, 6 Mar 2026 15:52:33 +0800 Subject: [PATCH 38/84] pinctrl: realtek: Switch to use devm functions Simplify the probe() function by switching to devm-managed versions of ioremap and pinctrl registration. Signed-off-by: Yu-Chun Lin Signed-off-by: Linus Walleij --- drivers/pinctrl/realtek/pinctrl-rtd.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c index 41e7f5c2bf74..56fd3093c206 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd.c +++ b/drivers/pinctrl/realtek/pinctrl-rtd.c @@ -543,13 +543,12 @@ static const struct regmap_config rtd_pinctrl_regmap_config = { int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_desc *desc) { struct rtd_pinctrl *data; - int ret; data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); if (!data) return -ENOMEM; - data->base = of_iomap(pdev->dev.of_node, 0); + data->base = devm_platform_ioremap_resource(pdev, 0); if (!data->base) return -ENOMEM; @@ -570,25 +569,18 @@ int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_des if (IS_ERR(data->regmap_pinctrl)) { dev_err(data->dev, "failed to init regmap: %ld\n", PTR_ERR(data->regmap_pinctrl)); - ret = PTR_ERR(data->regmap_pinctrl); - goto unmap; + return PTR_ERR(data->regmap_pinctrl); } - data->pcdev = pinctrl_register(&data->desc, &pdev->dev, data); - if (IS_ERR(data->pcdev)) { - ret = PTR_ERR(data->pcdev); - goto unmap; - } + data->pcdev = devm_pinctrl_register(&pdev->dev, &data->desc, data); + if (IS_ERR(data->pcdev)) + return PTR_ERR(data->pcdev); platform_set_drvdata(pdev, data); dev_dbg(&pdev->dev, "probed\n"); return 0; - -unmap: - iounmap(data->base); - return ret; } EXPORT_SYMBOL(rtd_pinctrl_probe); From 5e783510b5c09bc8a9d83a34488ed924769085f2 Mon Sep 17 00:00:00 2001 From: Yu-Chun Lin Date: Fri, 6 Mar 2026 15:52:34 +0800 Subject: [PATCH 39/84] pinctrl: realtek: Simplify error handling with dev_err_probe() Convert the error handling code in probe() to use dev_err_probe() to enhance semantic meaning. Reviewed-by: Bartosz Golaszewski Signed-off-by: Yu-Chun Lin Signed-off-by: Linus Walleij --- drivers/pinctrl/realtek/pinctrl-rtd.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c index 56fd3093c206..382bdae54bf3 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd.c +++ b/drivers/pinctrl/realtek/pinctrl-rtd.c @@ -566,15 +566,14 @@ int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_des data->regmap_pinctrl = devm_regmap_init_mmio(data->dev, data->base, &rtd_pinctrl_regmap_config); - if (IS_ERR(data->regmap_pinctrl)) { - dev_err(data->dev, "failed to init regmap: %ld\n", - PTR_ERR(data->regmap_pinctrl)); - return PTR_ERR(data->regmap_pinctrl); - } + if (IS_ERR(data->regmap_pinctrl)) + return dev_err_probe(data->dev, PTR_ERR(data->regmap_pinctrl), + "Failed to init regmap\n"); data->pcdev = devm_pinctrl_register(&pdev->dev, &data->desc, data); if (IS_ERR(data->pcdev)) - return PTR_ERR(data->pcdev); + return dev_err_probe(data->dev, PTR_ERR(data->pcdev), + "Failed to register pinctrl\n"); platform_set_drvdata(pdev, data); From aeeac6d3a1f51c8b0ac44ab262c568e905211879 Mon Sep 17 00:00:00 2001 From: Yu-Chun Lin Date: Fri, 6 Mar 2026 15:52:35 +0800 Subject: [PATCH 40/84] pinctrl: realtek: Fix grammar in error messages Correct the grammar in dev_err() messages. Change "Not support ..." to " unsupported..." to improve readability and comply with standard English usage. Signed-off-by: Yu-Chun Lin Signed-off-by: Linus Walleij --- drivers/pinctrl/realtek/pinctrl-rtd.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c index 382bdae54bf3..5888a36babba 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd.c +++ b/drivers/pinctrl/realtek/pinctrl-rtd.c @@ -293,14 +293,14 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, config_desc = rtd_pinctrl_find_config(data, pinnr); if (!config_desc) { - dev_err(data->dev, "Not support pin config for pin: %s\n", name); + dev_err(data->dev, "Pin config unsupported for pin: %s\n", name); return -ENOTSUPP; } switch ((u32)param) { case PIN_CONFIG_INPUT_SCHMITT: case PIN_CONFIG_INPUT_SCHMITT_ENABLE: if (config_desc->smt_offset == NA) { - dev_err(data->dev, "Not support input schmitt for pin: %s\n", name); + dev_err(data->dev, "Input schmitt unsupported for pin: %s\n", name); return -ENOTSUPP; } smt_off = config_desc->base_bit + config_desc->smt_offset; @@ -313,7 +313,7 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, case PIN_CONFIG_DRIVE_PUSH_PULL: if (config_desc->pud_en_offset == NA) { - dev_err(data->dev, "Not support push pull for pin: %s\n", name); + dev_err(data->dev, "Push pull unsupported for pin: %s\n", name); return -ENOTSUPP; } pulen_off = config_desc->base_bit + config_desc->pud_en_offset; @@ -325,7 +325,7 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, case PIN_CONFIG_BIAS_DISABLE: if (config_desc->pud_en_offset == NA) { - dev_err(data->dev, "Not support bias disable for pin: %s\n", name); + dev_err(data->dev, "Bias disable unsupported for pin: %s\n", name); return -ENOTSUPP; } pulen_off = config_desc->base_bit + config_desc->pud_en_offset; @@ -337,7 +337,7 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, case PIN_CONFIG_BIAS_PULL_UP: if (config_desc->pud_en_offset == NA) { - dev_err(data->dev, "Not support bias pull up for pin:%s\n", name); + dev_err(data->dev, "Bias pull up unsupported for pin:%s\n", name); return -ENOTSUPP; } pulen_off = config_desc->base_bit + config_desc->pud_en_offset; @@ -350,7 +350,7 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, case PIN_CONFIG_BIAS_PULL_DOWN: if (config_desc->pud_en_offset == NA) { - dev_err(data->dev, "Not support bias pull down for pin: %s\n", name); + dev_err(data->dev, "Bias pull down unsupported for pin: %s\n", name); return -ENOTSUPP; } pulen_off = config_desc->base_bit + config_desc->pud_en_offset; @@ -384,7 +384,7 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, return -EINVAL; break; case NA: - dev_err(data->dev, "Not support drive strength for pin: %s\n", name); + dev_err(data->dev, "Drive strength unsupported for pin: %s\n", name); return -ENOTSUPP; default: return -EINVAL; @@ -394,7 +394,7 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, case PIN_CONFIG_POWER_SOURCE: if (config_desc->power_offset == NA) { - dev_err(data->dev, "Not support power source for pin: %s\n", name); + dev_err(data->dev, "Power source unsupported for pin: %s\n", name); return -ENOTSUPP; } reg_off = config_desc->reg_offset; @@ -411,7 +411,7 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, case RTD_DRIVE_STRENGH_P: sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr); if (!sconfig_desc) { - dev_err(data->dev, "Not support P driving for pin: %s\n", name); + dev_err(data->dev, "P driving unsupported for pin: %s\n", name); return -ENOTSUPP; } set_val = arg; @@ -428,7 +428,7 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, case RTD_DRIVE_STRENGH_N: sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr); if (!sconfig_desc) { - dev_err(data->dev, "Not support N driving for pin: %s\n", name); + dev_err(data->dev, "N driving unsupported for pin: %s\n", name); return -ENOTSUPP; } set_val = arg; @@ -445,7 +445,7 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, case RTD_DUTY_CYCLE: sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr); if (!sconfig_desc || sconfig_desc->dcycle_offset == NA) { - dev_err(data->dev, "Not support duty cycle for pin: %s\n", name); + dev_err(data->dev, "Duty cycle unsupported for pin: %s\n", name); return -ENOTSUPP; } set_val = arg; From 9f6cfc93dde974bff44db11224bf45e68ac1752b Mon Sep 17 00:00:00 2001 From: Tzuyi Chang Date: Fri, 6 Mar 2026 15:52:36 +0800 Subject: [PATCH 41/84] pinctrl: realtek: Support system suspend and resume Add system suspend and resume capabilities to the common Realtek pinctrl library. This enables saving and restoring pin configurations during the noirq phase for SoCs that define register ranges. Signed-off-by: Tzuyi Chang Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin Signed-off-by: Linus Walleij --- drivers/pinctrl/realtek/pinctrl-rtd.c | 98 +++++++++++++++++++++++++++ drivers/pinctrl/realtek/pinctrl-rtd.h | 13 ++++ 2 files changed, 111 insertions(+) diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c index 5888a36babba..60dfb39bc986 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd.c +++ b/drivers/pinctrl/realtek/pinctrl-rtd.c @@ -30,6 +30,7 @@ struct rtd_pinctrl { struct pinctrl_desc desc; const struct rtd_pinctrl_desc *info; struct regmap *regmap_pinctrl; + u32 **saved_regs; }; /* custom pinconf parameters */ @@ -540,6 +541,30 @@ static const struct regmap_config rtd_pinctrl_regmap_config = { .use_relaxed_mmio = true, }; +static int rtd_pinctrl_init_pm(struct rtd_pinctrl *data) +{ + const struct rtd_pin_range *pin_range = data->info->pin_range; + struct device *dev = data->pcdev->dev; + const struct rtd_reg_range *range; + size_t num_entries; + int i; + + data->saved_regs = devm_kcalloc(dev, pin_range->num_ranges, sizeof(u32 *), GFP_KERNEL); + if (!data->saved_regs) + return -ENOMEM; + + for (i = 0; i < pin_range->num_ranges; i++) { + range = &pin_range->ranges[i]; + num_entries = range->len / 4; + + data->saved_regs[i] = devm_kzalloc(dev, num_entries * sizeof(u32), GFP_KERNEL); + if (!data->saved_regs[i]) + return -ENOMEM; + } + + return 0; +} + int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_desc *desc) { struct rtd_pinctrl *data; @@ -579,9 +604,82 @@ int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_des dev_dbg(&pdev->dev, "probed\n"); + if (data->info->pin_range) { + if (rtd_pinctrl_init_pm(data)) + return -ENOMEM; + } + return 0; } EXPORT_SYMBOL(rtd_pinctrl_probe); +static int realtek_pinctrl_suspend(struct device *dev) +{ + struct rtd_pinctrl *data = dev_get_drvdata(dev); + const struct rtd_pin_range *pin_range = data->info->pin_range; + const struct rtd_reg_range *range; + u32 *range_regs; + int count; + int i, j; + int ret; + + if (!data->saved_regs) + return 0; + + for (i = 0; i < pin_range->num_ranges; i++) { + range = &pin_range->ranges[i]; + range_regs = data->saved_regs[i]; + count = range->len / 4; + + for (j = 0; j < count; j++) { + ret = regmap_read(data->regmap_pinctrl, range->offset + (j * 4), + &range_regs[j]); + if (ret) { + dev_err(dev, "failed to store register 0x%x: %d\n", + range->offset + (j * 4), ret); + return ret; + } + } + } + + return 0; +} + +static int realtek_pinctrl_resume(struct device *dev) +{ + struct rtd_pinctrl *data = dev_get_drvdata(dev); + const struct rtd_pin_range *pin_range = data->info->pin_range; + const struct rtd_reg_range *range; + u32 *range_regs; + int count; + int i, j; + int ret; + + if (!data->saved_regs) + return 0; + + for (i = 0; i < pin_range->num_ranges; i++) { + range = &pin_range->ranges[i]; + range_regs = data->saved_regs[i]; + count = range->len / 4; + + for (j = 0; j < count; j++) { + ret = regmap_write(data->regmap_pinctrl, range->offset + (j * 4), + range_regs[j]); + if (ret) { + dev_err(dev, "failed to restore register 0x%x: %d\n", + range->offset + (j * 4), ret); + return ret; + } + } + } + return 0; +} + +const struct dev_pm_ops realtek_pinctrl_pm_ops = { + NOIRQ_SYSTEM_SLEEP_PM_OPS(realtek_pinctrl_suspend, realtek_pinctrl_resume) +}; +EXPORT_SYMBOL_GPL(realtek_pinctrl_pm_ops); + MODULE_DESCRIPTION("Realtek DHC SoC pinctrl driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.h b/drivers/pinctrl/realtek/pinctrl-rtd.h index e15130896abc..7fb0955ce749 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd.h +++ b/drivers/pinctrl/realtek/pinctrl-rtd.h @@ -47,6 +47,16 @@ struct rtd_pin_sconfig_desc { unsigned int pdrive_maskbits; }; +struct rtd_reg_range { + unsigned int offset; + size_t len; +}; + +struct rtd_pin_range { + const struct rtd_reg_range *ranges; + const int num_ranges; +}; + struct rtd_pin_desc { const char *name; unsigned int mux_offset; @@ -119,6 +129,9 @@ struct rtd_pinctrl_desc { unsigned int num_sconfigs; struct rtd_pin_reg_list *lists; unsigned int num_regs; + const struct rtd_pin_range *pin_range; }; int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_desc *desc); + +extern const struct dev_pm_ops realtek_pinctrl_pm_ops; From 5ad32c3607cf241a1a2680cabd64cbcd757227aa Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 27 Feb 2026 17:43:35 +0100 Subject: [PATCH 42/84] pinctrl: cy8c95x0: Avoid returning positive values to user space When probe fails due to unclear interrupt status register, it returns a positive number instead of the proper error code. Fix this accordingly. Fixes: e6cbbe42944d ("pinctrl: Add Cypress cy8c95x0 support") Reported-by: kernel test robot Reported-by: Dan Carpenter Closes: https://lore.kernel.org/r/202602271847.vVWkqLBD-lkp@intel.com/ Signed-off-by: Andy Shevchenko Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-cy8c95x0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index b88a627708ff..38caea3b3376 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -1300,7 +1300,7 @@ static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq) /* Read IRQ status register to clear all pending interrupts */ ret = cy8c95x0_irq_pending(chip, pending_irqs); if (ret) - return dev_err_probe(dev, ret, "failed to clear irq status register\n"); + return dev_err_probe(dev, -EBUSY, "failed to clear irq status register\n"); /* Mask all interrupts */ bitmap_fill(chip->irq_mask, MAX_LINE); From 3bf14aec6d6f1ad694d8e196289ed7e02ba3cb66 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 6 Mar 2026 15:22:15 +0100 Subject: [PATCH 43/84] dt-bindings: pinctrl: qcom: Add Milos LPASS LPI pinctrl Add bindings for pin controller in Milos Low Power Audio SubSystem (LPASS). Signed-off-by: Luca Weiss Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml | 109 ++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000000..73e84f188591 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Milos SoC LPASS LPI TLMM + +maintainers: + - Luca Weiss + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm Milos SoC. + +properties: + compatible: + const: qcom,milos-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI MCC registers + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-milos-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-milos-lpass-state" + additionalProperties: false + +$defs: + qcom-milos-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" + + function: + enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk, + dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b, + ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk, + i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk, + i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, qca_swr_clk, + qca_swr_data, slimbus_clk, slimbus_data, swr_rx_clk, + swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk, + wsa_swr_data ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + pinctrl@3440000 { + compatible = "qcom,milos-lpass-lpi-pinctrl"; + reg = <0x03440000 0x20000>, + <0x034d0000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", + "audio"; + + tx-swr-active-clk-state { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <4>; + slew-rate = <1>; + bias-disable; + }; + }; From ca0395d9ef294a4340104107177de23e04de2344 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 6 Mar 2026 15:22:16 +0100 Subject: [PATCH 44/84] pinctrl: qcom: Add Milos LPASS LPI TLMM Add a driver for the pin controller in the Low Power Audio SubSystem (LPASS) on the Milos SoC. Signed-off-by: Luca Weiss Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + .../pinctrl/qcom/pinctrl-milos-lpass-lpi.c | 217 ++++++++++++++++++ 3 files changed, 228 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index f56592411cf6..ee34ffca3917 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -60,6 +60,16 @@ config PINCTRL_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SoCs. +config PINCTRL_MILOS_LPASS_LPI + tristate "Qualcomm Technologies Inc Milos LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc Milos + platform. + config PINCTRL_SC7280_LPASS_LPI tristate "Qualcomm Technologies Inc SC7280 and SM8350 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 831103b3827b..a8fd12f90d6e 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o obj-$(CONFIG_PINCTRL_MDM9607) += pinctrl-mdm9607.o obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o obj-$(CONFIG_PINCTRL_MILOS) += pinctrl-milos.o +obj-$(CONFIG_PINCTRL_MILOS_LPASS_LPI) += pinctrl-milos-lpass-lpi.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o diff --git a/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c new file mode 100644 index 000000000000..3bf6fe0cf1bb --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2023 Linaro Ltd. + * Copyright (c) 2026 Luca Weiss + */ + +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_dmic4_clk, + LPI_MUX_dmic4_data, + LPI_MUX_i2s0_clk, + LPI_MUX_i2s0_data, + LPI_MUX_i2s0_ws, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_i2s3_clk, + LPI_MUX_i2s3_data, + LPI_MUX_i2s3_ws, + LPI_MUX_qca_swr_clk, + LPI_MUX_qca_swr_data, + LPI_MUX_slimbus_clk, + LPI_MUX_slimbus_data, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_ext_mclk1_a, + LPI_MUX_ext_mclk1_b, + LPI_MUX_ext_mclk1_c, + LPI_MUX_ext_mclk1_d, + LPI_MUX_ext_mclk1_e, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const struct pinctrl_pin_desc milos_lpi_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", +}; + +static const char * const dmic1_clk_groups[] = { "gpio6" }; +static const char * const dmic1_data_groups[] = { "gpio7" }; +static const char * const dmic2_clk_groups[] = { "gpio8" }; +static const char * const dmic2_data_groups[] = { "gpio9" }; +static const char * const dmic3_clk_groups[] = { "gpio12" }; +static const char * const dmic3_data_groups[] = { "gpio13" }; +static const char * const dmic4_clk_groups[] = { "gpio21" }; +static const char * const dmic4_data_groups[] = { "gpio22" }; +static const char * const i2s0_clk_groups[] = { "gpio0" }; +static const char * const i2s0_ws_groups[] = { "gpio1" }; +static const char * const i2s0_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" }; +static const char * const i2s3_clk_groups[] = { "gpio19" }; +static const char * const i2s3_ws_groups[] = { "gpio20" }; +static const char * const i2s3_data_groups[] = { "gpio21", "gpio22" }; +static const char * const qca_swr_clk_groups[] = { "gpio19" }; +static const char * const qca_swr_data_groups[] = { "gpio20" }; +static const char * const slimbus_clk_groups[] = { "gpio19" }; +static const char * const slimbus_data_groups[] = { "gpio20" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" }; +static const char * const wsa_swr_clk_groups[] = { "gpio10" }; +static const char * const wsa_swr_data_groups[] = { "gpio11" }; +static const char * const ext_mclk1_a_groups[] = { "gpio13" }; +static const char * const ext_mclk1_b_groups[] = { "gpio9" }; +static const char * const ext_mclk1_c_groups[] = { "gpio5" }; +static const char * const ext_mclk1_d_groups[] = { "gpio14" }; +static const char * const ext_mclk1_e_groups[] = { "gpio22" }; + +static const struct lpi_pingroup milos_groups[] = { + LPI_PINGROUP(0, 0, swr_tx_clk, i2s0_clk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, i2s0_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, i2s0_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, i2s0_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, i2s0_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, ext_mclk1_c, i2s0_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, ext_mclk1_b, _), + LPI_PINGROUP(10, 16, wsa_swr_clk, i2s2_clk, _, _), + LPI_PINGROUP(11, 18, wsa_swr_data, i2s2_ws, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, ext_mclk1_a, _), + LPI_PINGROUP(14, 6, swr_tx_data, ext_mclk1_d, _, _), + /* gpio15 - gpio18 do not really exist */ + LPI_PINGROUP(15, 20, _, _, _, _), + LPI_PINGROUP(16, 22, _, _, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(18, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(19, LPI_NO_SLEW, i2s3_clk, slimbus_clk, qca_swr_clk, _), + LPI_PINGROUP(20, LPI_NO_SLEW, i2s3_ws, slimbus_data, qca_swr_data, _), + LPI_PINGROUP(21, LPI_NO_SLEW, i2s3_data, dmic4_clk, _, _), + LPI_PINGROUP(22, LPI_NO_SLEW, i2s3_data, dmic4_data, ext_mclk1_e, _), +}; + +static const struct lpi_function milos_functions[] = { + LPI_FUNCTION(gpio), + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(dmic4_clk), + LPI_FUNCTION(dmic4_data), + LPI_FUNCTION(i2s0_clk), + LPI_FUNCTION(i2s0_data), + LPI_FUNCTION(i2s0_ws), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(i2s3_clk), + LPI_FUNCTION(i2s3_data), + LPI_FUNCTION(i2s3_ws), + LPI_FUNCTION(qca_swr_clk), + LPI_FUNCTION(qca_swr_data), + LPI_FUNCTION(slimbus_clk), + LPI_FUNCTION(slimbus_data), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), + LPI_FUNCTION(ext_mclk1_a), + LPI_FUNCTION(ext_mclk1_b), + LPI_FUNCTION(ext_mclk1_c), + LPI_FUNCTION(ext_mclk1_d), + LPI_FUNCTION(ext_mclk1_e), +}; + +static const struct lpi_pinctrl_variant_data milos_lpi_data = { + .pins = milos_lpi_pins, + .npins = ARRAY_SIZE(milos_lpi_pins), + .groups = milos_groups, + .ngroups = ARRAY_SIZE(milos_groups), + .functions = milos_functions, + .nfunctions = ARRAY_SIZE(milos_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,milos-lpass-lpi-pinctrl", + .data = &milos_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver = { + .driver = { + .name = "qcom-milos-lpass-lpi-pinctrl", + .of_match_table = lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("Qualcomm Milos LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); From b7fff045a9f8d15d78ae3206ab393f55bf9c383d Mon Sep 17 00:00:00 2001 From: Philipp Hahn Date: Tue, 10 Mar 2026 12:49:07 +0100 Subject: [PATCH 45/84] pinctrl: Prefer IS_ERR_OR_NULL over manual NULL check Prefer using IS_ERR_OR_NULL() over using IS_ERR() and a manual NULL check. Change generated with coccinelle. To: Linus Walleij Cc: linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Philipp Hahn Signed-off-by: Linus Walleij --- drivers/pinctrl/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 2edc9bdad183..254161d52da7 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -1992,7 +1992,7 @@ static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev) device_root = debugfs_create_dir(debugfs_name, debugfs_root); pctldev->device_root = device_root; - if (IS_ERR(device_root) || !device_root) { + if (IS_ERR_OR_NULL(device_root)) { pr_warn("failed to create debugfs directory for %s\n", dev_name(pctldev->dev)); return; From 91910a4047e4d3c85e140604c9b75097bb8f0329 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 10 Mar 2026 17:58:27 +0000 Subject: [PATCH 46/84] dt-bindings: pinctrl: pincfg-node: permit bias-high-impedance with other bias properties It is possible that devices tristate buffers may set the buffer to the high-Z state in addition to setting pull-up or pull-down on a pin. Remove this particular restriction to prevent warning on zynqmp systems where this configuration seems to be valid. Reported-by: Rob Herring (Arm) Fixes: a901e8705f89f ("dt-bindings: pinctrl: pincfg-node: add restrictions on conflicting properties") Signed-off-by: Conor Dooley Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml | 4 ---- 1 file changed, 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml b/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml index fe936ab09104..981f45c2f56b 100644 --- a/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml @@ -236,8 +236,6 @@ allOf: anyOf: - required: - bias-disable - - required: - - bias-high-impedance - required: - bias-bus-hold - required: @@ -250,8 +248,6 @@ allOf: oneOf: - required: - bias-disable - - required: - - bias-high-impedance - required: - bias-bus-hold - required: From fc334ad4a1d110754b3ec3abd0805d1ae1cfcc4b Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 11 Mar 2026 12:42:28 +0000 Subject: [PATCH 47/84] dt-bindings: pinctrl: qcom,sm8650-lpass-lpi-pinctrl: Add Glymur pinctrl Document compatible for Qualcomm Glymur SoC LPASS TLMM pin controller, fully compatible with previous SM8650 generation (same amount of pins and functions). Signed-off-by: Srinivas Kandagatla Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml index 74df912e60ad..1bf08860a4ba 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml @@ -19,7 +19,9 @@ properties: oneOf: - const: qcom,sm8650-lpass-lpi-pinctrl - items: - - const: qcom,sm8750-lpass-lpi-pinctrl + - enum: + - qcom,glymur-lpass-lpi-pinctrl + - qcom,sm8750-lpass-lpi-pinctrl - const: qcom,sm8650-lpass-lpi-pinctrl reg: From 9ba4ef6847ba53dea92efce47c9e044fbf6d6dcf Mon Sep 17 00:00:00 2001 From: Chen Ni Date: Thu, 12 Mar 2026 11:18:20 +0800 Subject: [PATCH 48/84] pinctrl: realtek: Fix error check for devm_platform_ioremap_resource() Replace NULL check with IS_ERR() for devm_platform_ioremap_resource() return value. Use dev_err_probe() for error handling to maintain consistency with the rest of the probe function. Fixes: b7f698b22b8b ("pinctrl: realtek: Switch to use devm functions") Signed-off-by: Chen Ni Signed-off-by: Linus Walleij --- drivers/pinctrl/realtek/pinctrl-rtd.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c index 60dfb39bc986..7836a15afe44 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd.c +++ b/drivers/pinctrl/realtek/pinctrl-rtd.c @@ -574,8 +574,9 @@ int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_des return -ENOMEM; data->base = devm_platform_ioremap_resource(pdev, 0); - if (!data->base) - return -ENOMEM; + if (IS_ERR(data->base)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->base), + "Failed to ioremap resource\n"); data->dev = &pdev->dev; data->info = desc; From c3b0c06b73974d75c640a4ebc8678f8538654e5a Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Thu, 12 Mar 2026 16:42:42 +0800 Subject: [PATCH 49/84] pinctrl: spacemit: return -ENOTSUPP for unsupported pin configurations Return -ENOTSUPP instead of -EINVAL when encountering unsupported pin configuration parameters. This is more logical and allows the GPIO subsystem to gracefully handle unsupported parameters via functions like gpio_set_config_with_argument_optional(), which specifically ignores -ENOTSUPP but treats others as failure. Signed-off-by: Junhui Liu Reviewed-by: Anand Moon Reviewed-by: Bartosz Golaszewski Reviewed-by: Yixun Lan Signed-off-by: Linus Walleij --- drivers/pinctrl/spacemit/pinctrl-k1.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c index 62cab6f6cd0a..b0be62b1c816 100644 --- a/drivers/pinctrl/spacemit/pinctrl-k1.c +++ b/drivers/pinctrl/spacemit/pinctrl-k1.c @@ -674,7 +674,7 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, arg = 0; break; default: - return -EINVAL; + return -ENOTSUPP; } *config = pinconf_to_config_packed(param, arg); @@ -740,7 +740,7 @@ static int spacemit_pinconf_generate_config(struct spacemit_pinctrl *pctrl, } break; default: - return -EINVAL; + return -ENOTSUPP; } } @@ -814,10 +814,12 @@ static int spacemit_pinconf_set(struct pinctrl_dev *pctldev, struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); u32 value; + int ret; - if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, - configs, num_configs, &value)) - return -EINVAL; + ret = spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, + configs, num_configs, &value); + if (ret) + return ret; return spacemit_pin_set_config(pctrl, pin, value); } @@ -831,16 +833,17 @@ static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, const struct spacemit_pin *spin; const struct group_desc *group; u32 value; - int i; + int i, ret; group = pinctrl_generic_get_group(pctldev, gsel); if (!group) return -EINVAL; spin = spacemit_get_pin(pctrl, group->grp.pins[0]); - if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, - configs, num_configs, &value)) - return -EINVAL; + ret = spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, + configs, num_configs, &value); + if (ret) + return ret; for (i = 0; i < group->grp.npins; i++) spacemit_pin_set_config(pctrl, group->grp.pins[i], value); From 47a9050e678c7929ada33c3f1f28ac4403423181 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Thu, 12 Mar 2026 16:42:43 +0800 Subject: [PATCH 50/84] gpio: spacemit-k1: Add set_config callback support Assign gpiochip_generic_config() to the set_config() callback to support pin configuration through the GPIO subsystem. This allows users to configure GPIO pin attributes like pull-up/down when specifying a GPIO line in the Device Tree. Signed-off-by: Junhui Liu Reviewed-by: Anand Moon Acked-by: Bartosz Golaszewski Reviewed-by: Yixun Lan Signed-off-by: Linus Walleij --- drivers/gpio/gpio-spacemit-k1.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-spacemit-k1.c b/drivers/gpio/gpio-spacemit-k1.c index dbd2e81094b9..5fe813b7f9bb 100644 --- a/drivers/gpio/gpio-spacemit-k1.c +++ b/drivers/gpio/gpio-spacemit-k1.c @@ -228,6 +228,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, gc->label = dev_name(dev); gc->request = gpiochip_generic_request; gc->free = gpiochip_generic_free; + gc->set_config = gpiochip_generic_config; gc->ngpio = SPACEMIT_NR_GPIOS_PER_BANK; gc->base = -1; gc->of_gpio_n_cells = 3; From d453086996957f1b87610315810235db7b03b3a6 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sun, 15 Mar 2026 16:10:00 -0700 Subject: [PATCH 51/84] pinctrl: tegra: use flexible array member for array Simplifies allocation slightly by removing a kcalloc call and using struct_size. Signed-off-by: Rosen Penev [linusw@kernel.org: Add in count variable and use __counted_by()] Signed-off-by: Linus Walleij --- drivers/pinctrl/tegra/pinctrl-tegra.c | 10 +++------- drivers/pinctrl/tegra/pinctrl-tegra.h | 4 ++-- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 11ecbd6a9b2a..bac2adeb5c63 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -832,18 +832,14 @@ int tegra_pinctrl_probe(struct platform_device *pdev, int fn, gn, gfn; unsigned long backup_regs_size = 0; - pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); + pmx = devm_kzalloc(&pdev->dev, + struct_size(pmx, pingroup_configs, soc_data->ngroups), GFP_KERNEL); if (!pmx) return -ENOMEM; pmx->dev = &pdev->dev; pmx->soc = soc_data; - - pmx->pingroup_configs = devm_kcalloc(&pdev->dev, - pmx->soc->ngroups, sizeof(*pmx->pingroup_configs), - GFP_KERNEL); - if (!pmx->pingroup_configs) - return -ENOMEM; + pmx->num_pingroup_configs = soc_data->ngroups; /* * Each mux group will appear in 4 functions' list of groups. diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index bc7b70913b89..deb589cda31e 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -25,8 +25,8 @@ struct tegra_pmx { int nbanks; void __iomem **regs; u32 *backup_regs; - /* Array of size soc->ngroups */ - struct tegra_pingroup_config *pingroup_configs; + unsigned int num_pingroup_configs; + struct tegra_pingroup_config pingroup_configs[] __counted_by(num_pingroup_configs); }; enum tegra_pinconf_param { From c98324ea7849b6e5baa1774f71709b375a2c2f9e Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 17 Mar 2026 11:36:11 +0100 Subject: [PATCH 52/84] pinctrl: pinconf-generic: Fully validate 'pinmux' property The pinconf_generic_parse_dt_pinmux() assumes that the 'pinmux' property is not empty when present. This might be not true. With that, the allocator will give a special value in return and not NULL which lead to the crash when trying to access that (invalid) memory. Fix that by fully validating 'pinmux' value, including its length. Fixes: 7112c05fff83 ("pinctrl: pinconf-generic: Add API for pinmux propertity in DTS file") Signed-off-by: Andy Shevchenko Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf-generic.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 855ca973a1c8..6ba44fc0dd82 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -325,12 +325,17 @@ int pinconf_generic_parse_dt_pinmux(struct device_node *np, struct device *dev, return -ENOENT; } + npins_t = prop->length / sizeof(u32); + if (npins_t == 0) { + dev_info(dev, "pinmux property doesn't have entries\n"); + return -ENODATA; + } + if (!pid || !pmux || !npins) { dev_err(dev, "parameters error\n"); return -EINVAL; } - npins_t = prop->length / sizeof(u32); pid_t = devm_kcalloc(dev, npins_t, sizeof(*pid_t), GFP_KERNEL); pmux_t = devm_kcalloc(dev, npins_t, sizeof(*pmux_t), GFP_KERNEL); if (!pid_t || !pmux_t) { From 1fc7de3047e169e7ae32afadf87a134cd1c68319 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 17 Mar 2026 11:36:12 +0100 Subject: [PATCH 53/84] pinctrl: pinconf-generic: Validate fwnode instead of device node Currently we convert device node to fwnode in the pinconf_generic_parse_dt_config() and then validate the device node. This is confusing order. Instead, assign fwnode and validate it. Fixes: e002d162654b ("pinctrl: pinconf-generic: Use only fwnode API in parse_dt_cfg()") Signed-off-by: Andy Shevchenko Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf-generic.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 6ba44fc0dd82..08bfe504b615 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -377,12 +377,13 @@ int pinconf_generic_parse_dt_config(struct device_node *np, unsigned long **configs, unsigned int *nconfigs) { - struct fwnode_handle *fwnode = of_fwnode_handle(np); unsigned long *cfg; unsigned int max_cfg, ncfg = 0; + struct fwnode_handle *fwnode; int ret; - if (!np) + fwnode = of_fwnode_handle(np); + if (!fwnode) return -EINVAL; /* allocate a temporary array big enough to hold one of each option */ From e238fb21bd52e1a798f7c7662d267703a249bdba Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 17 Mar 2026 11:36:13 +0100 Subject: [PATCH 54/84] pinctrl: pinconf-generic: Convert ..._parse_dt_pinmux() to fwnode API Convert pinconf_generic_parse_dt_pinmux() to fwnode API. This makes code cleaner and potentially reusable for some other types of fwnodes, such as software nodes. Signed-off-by: Andy Shevchenko Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf-generic.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 08bfe504b615..faa03a7967ee 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -312,20 +312,19 @@ int pinconf_generic_parse_dt_pinmux(struct device_node *np, struct device *dev, unsigned int **pid, unsigned int **pmux, unsigned int *npins) { + struct fwnode_handle *fwnode = of_fwnode_handle(np); unsigned int *pid_t; unsigned int *pmux_t; - struct property *prop; unsigned int npins_t, i; - u32 value; int ret; - prop = of_find_property(np, "pinmux", NULL); - if (!prop) { + ret = fwnode_property_count_u32(fwnode, "pinmux"); + if (ret < 0) { dev_info(dev, "Missing pinmux property\n"); - return -ENOENT; + return ret; } - npins_t = prop->length / sizeof(u32); + npins_t = ret; if (npins_t == 0) { dev_info(dev, "pinmux property doesn't have entries\n"); return -ENODATA; @@ -342,14 +341,16 @@ int pinconf_generic_parse_dt_pinmux(struct device_node *np, struct device *dev, dev_err(dev, "kalloc memory fail\n"); return -ENOMEM; } + + ret = fwnode_property_read_u32_array(fwnode, "pinmux", pmux_t, npins_t); + if (ret) { + dev_err(dev, "get pinmux value fail\n"); + goto exit; + } + for (i = 0; i < npins_t; i++) { - ret = of_property_read_u32_index(np, "pinmux", i, &value); - if (ret) { - dev_err(dev, "get pinmux value fail\n"); - goto exit; - } - pmux_t[i] = value & 0xff; - pid_t[i] = (value >> 8) & 0xffffff; + pid_t[i] = pmux_t[i] >> 8; + pmux_t[i] = pmux_t[i] & 0xff; } *pid = pid_t; *pmux = pmux_t; From 1f5451844786ed203605528dca9e5d84ed378160 Mon Sep 17 00:00:00 2001 From: Yu-Chun Lin Date: Tue, 17 Mar 2026 19:54:03 +0800 Subject: [PATCH 55/84] pinctrl: realtek: Fix function signature for config argument The argument originates from pinconf_to_config_argument(), which returns a u32. Therefore, the arg parameter should be an unsigned int instead of enum pin_config_param. Fixes: e99ce78030db ("pinctrl: realtek: Add common pinctrl driver for Realtek DHC RTD SoCs") Signed-off-by: Yu-Chun Lin Signed-off-by: Linus Walleij --- drivers/pinctrl/realtek/pinctrl-rtd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c index 7836a15afe44..b645277ac9a9 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd.c +++ b/drivers/pinctrl/realtek/pinctrl-rtd.c @@ -280,7 +280,7 @@ static const struct rtd_pin_sconfig_desc *rtd_pinctrl_find_sconfig(struct rtd_pi static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, unsigned int pinnr, enum pin_config_param param, - enum pin_config_param arg) + unsigned int arg) { const struct rtd_pin_config_desc *config_desc; const struct rtd_pin_sconfig_desc *sconfig_desc; From 7b9fe771dcbd40201fa5a97befa93f11af53204e Mon Sep 17 00:00:00 2001 From: Tzuyi Chang Date: Tue, 17 Mar 2026 19:54:04 +0800 Subject: [PATCH 56/84] dt-bindings: pincfg-node: Add input-threshold-voltage-microvolt property Add a generic pin configuration property "input-threshold-voltage-microvolt" to support hardware designs where the input logic threshold is decoupled from the power supply voltage. This property allows the pinctrl driver to configure the correct internal reference voltage for pins that need to accept input signals at a different voltage level than their power supply. For example, a pin powered by 3.3V may need to accept 1.8V logic signals. This defines the reference for VIH (Input High Voltage) and VIL (Input Low Voltage) thresholds, enabling proper signal detection across different voltage domains. Signed-off-by: Tzuyi Chang Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin Acked-by: Conor Dooley Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml b/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml index 981f45c2f56b..97dbce8a261f 100644 --- a/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml @@ -162,6 +162,11 @@ properties: this affects the expected delay in ps before latching a value to an output pin. + input-threshold-voltage-microvolt: + description: Specifies the input voltage level of the pin in microvolts. + This defines the reference for VIH (Input High Voltage) and VIL + (Input Low Voltage) thresholds for proper signal detection. + allOf: - if: required: @@ -177,6 +182,7 @@ allOf: then: properties: input-enable: false + input-threshold-voltage-microvolt: false - if: required: From 00a5d1e71c928edb1e7de211a82e87858105dd47 Mon Sep 17 00:00:00 2001 From: Tzuyi Chang Date: Tue, 17 Mar 2026 19:54:05 +0800 Subject: [PATCH 57/84] pinctrl: pinconf-generic: Add properties 'input-threshold-voltage-microvolt' Add a new generic pin configuration parameter PIN_CONFIG_INPUT_VOLTAGE_UV. This parameter is used to specify the input voltage level of a pin in microvolts, which corresponds to the 'input-voltage-microvolt' property in Device Tree. Reviewed-by: Linus Walleij Signed-off-by: Tzuyi Chang Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf-generic.c | 2 ++ include/linux/pinctrl/pinconf-generic.h | 3 +++ 2 files changed, 5 insertions(+) diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index faa03a7967ee..6daa9729dd13 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -57,6 +57,7 @@ static const struct pin_config_item conf_items[] = { PCONFDUMP(PIN_CONFIG_SKEW_DELAY, "skew delay", NULL, true), PCONFDUMP(PIN_CONFIG_SKEW_DELAY_INPUT_PS, "input skew delay", "ps", true), PCONFDUMP(PIN_CONFIG_SKEW_DELAY_OUTPUT_PS, "output skew delay", "ps", true), + PCONFDUMP(PIN_CONFIG_INPUT_VOLTAGE_UV, "input voltage in microvolt", "uV", true), }; static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev, @@ -203,6 +204,7 @@ static const struct pinconf_generic_params dt_params[] = { { "skew-delay", PIN_CONFIG_SKEW_DELAY, 0 }, { "skew-delay-input-ps", PIN_CONFIG_SKEW_DELAY_INPUT_PS, 0 }, { "skew-delay-output-ps", PIN_CONFIG_SKEW_DELAY_OUTPUT_PS, 0 }, + { "input-threshold-voltage-microvolt", PIN_CONFIG_INPUT_VOLTAGE_UV, 0 }, }; /** diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index 531dc3e9b3f7..a5d4b2d8633a 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -83,6 +83,8 @@ struct pinctrl_map; * schmitt-trigger mode is disabled. * @PIN_CONFIG_INPUT_SCHMITT_UV: this will configure an input pin to run in * schmitt-trigger mode. The argument is in uV. + * @PIN_CONFIG_INPUT_VOLTAGE_UV: this will configure the input voltage level of + * the pin. The argument is specified in microvolts. * @PIN_CONFIG_MODE_LOW_POWER: this will configure the pin for low power * operation, if several modes of operation are supported these can be * passed in the argument on a custom form, else just use argument 1 @@ -145,6 +147,7 @@ enum pin_config_param { PIN_CONFIG_INPUT_SCHMITT, PIN_CONFIG_INPUT_SCHMITT_ENABLE, PIN_CONFIG_INPUT_SCHMITT_UV, + PIN_CONFIG_INPUT_VOLTAGE_UV, PIN_CONFIG_MODE_LOW_POWER, PIN_CONFIG_MODE_PWM, PIN_CONFIG_LEVEL, From 56624479a98fe56b6e8b257b016c0bfd49f1b1cf Mon Sep 17 00:00:00 2001 From: Yu-Chun Lin Date: Tue, 17 Mar 2026 19:54:06 +0800 Subject: [PATCH 58/84] dt-bindings: pinctrl: realtek: Improve 'realtek,duty-cycle' description The previous description was misleading because this hardware block is not a PWM generator. It does not generate a signal with a specific frequency and duty ratio. Instead, it provides a fixed nanosecond-level adjustment to the rising/ falling edges of an existing signal. The property name is kept as 'realtek,duty-cycle' rather than being renamed to strictly preserve Device Tree ABI backward compatibility. Acked-by: Conor Dooley Reviewed-by: Linus Walleij Signed-off-by: Yu-Chun Lin Signed-off-by: Linus Walleij --- .../bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml | 7 +++++-- .../bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml | 7 +++++-- .../bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml | 7 +++++-- 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml index 90bd49d87d2e..2a640e495cc7 100644 --- a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml @@ -135,8 +135,11 @@ patternProperties: realtek,duty-cycle: description: | - An integer describing the level to adjust output duty cycle, controlling - the proportion of positive and negative waveforms in nanoseconds. + An integer describing the level to adjust the output pulse width, it + provides a fixed nanosecond-level adjustment to the rising/falling + edges of an existing signal. It is used for Signal Integrity tuning + (adding/subtracting delay to fine-tune the high/low duration), rather + than generating a specific PWM frequency. Valid arguments are described as below: 0: 0ns 2: + 0.25ns diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml index b6211c8544ca..2136546adec8 100644 --- a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml @@ -134,8 +134,11 @@ patternProperties: realtek,duty-cycle: description: | - An integer describing the level to adjust output duty cycle, controlling - the proportion of positive and negative waveforms in nanoseconds. + An integer describing the level to adjust the output pulse width, it + provides a fixed nanosecond-level adjustment to the rising/falling + edges of an existing signal. It is used for Signal Integrity tuning + (adding/subtracting delay to fine-tune the high/low duration), rather + than generating a specific PWM frequency. Valid arguments are described as below: 0: 0ns 2: + 0.25ns diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml index e88bc649cc73..e8ea1362b16d 100644 --- a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml @@ -133,8 +133,11 @@ patternProperties: realtek,duty-cycle: description: | - An integer describing the level to adjust output duty cycle, controlling - the proportion of positive and negative waveforms in nanoseconds. + An integer describing the level to adjust the output pulse width, it + provides a fixed nanosecond-level adjustment to the rising/falling + edges of an existing signal. It is used for Signal Integrity tuning + (adding/subtracting delay to fine-tune the high/low duration), rather + than generating a specific PWM frequency. Valid arguments are described as below: 0: 0ns 2: + 0.25ns From f6ea7004e926ddae54b261327a3db2e4b195c92c Mon Sep 17 00:00:00 2001 From: Tzuyi Chang Date: Tue, 17 Mar 2026 19:54:07 +0800 Subject: [PATCH 59/84] dt-bindings: pinctrl: realtek: Add RTD1625 pinctrl binding Add device tree bindings for RTD1625. Reviewed-by: Conor Dooley Reviewed-by: Linus Walleij Signed-off-by: Tzuyi Chang Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin Signed-off-by: Linus Walleij --- .../pinctrl/realtek,rtd1625-pinctrl.yaml | 260 ++++++++++++++++++ 1 file changed, 260 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml new file mode 100644 index 000000000000..9562a043707e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml @@ -0,0 +1,260 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2025 Realtek Semiconductor Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/realtek,rtd1625-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek DHC RTD1625 Pin Controller + +maintainers: + - Tzuyi Chang + - Yu-Chun Lin + +description: + The Realtek DHC RTD1625 is a high-definition media processor SoC. The + RTD1625 pin controller is used to control pin function, pull-up/down + resistors, drive strength, slew rate, Schmitt trigger, power source + (I/O output voltage), input threshold domain selection and a higher-VIL mode. + +properties: + compatible: + items: + - enum: + - realtek,rtd1625-iso-pinctrl + - realtek,rtd1625-main2-pinctrl + - realtek,rtd1625-isom-pinctrl + - realtek,rtd1625-ve4-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pins: + items: + enum: [gpio_0, gpio_1, gpio_2, gpio_3, gpio_4, gpio_5, gpio_6, + gpio_7, gpio_8, gpio_9, gpio_10, gpio_11, gpio_12, gpio_13, + gpio_14, gpio_15, gpio_16, gpio_17, gpio_18, gpio_19, gpio_20, + gpio_21, gpio_22, gpio_23, gpio_24, gpio_25, gpio_28, gpio_29, + gpio_30, gpio_31, gpio_32, gpio_33, gpio_34, gpio_35, gpio_40, + gpio_41, gpio_42, gpio_43, gpio_44, gpio_45, gpio_46, gpio_47, + gpio_48, gpio_49, gpio_50, gpio_51, gpio_52, gpio_53, gpio_54, + gpio_55, gpio_56, gpio_57, gpio_58, gpio_59, gpio_60, gpio_61, + gpio_62, gpio_63, gpio_64, gpio_65, gpio_66, gpio_67, gpio_80, + gpio_81, gpio_82, gpio_83, gpio_84, gpio_85, gpio_86, gpio_87, + gpio_88, gpio_89, gpio_90, gpio_91, gpio_92, gpio_93, gpio_94, + gpio_95, gpio_96, gpio_97, gpio_98, gpio_99, gpio_100, + gpio_101, gpio_102, gpio_103, gpio_104, gpio_105, gpio_106, + gpio_107, gpio_108, gpio_109, gpio_110, gpio_111, gpio_112, + gpio_128, gpio_129, gpio_130, gpio_131, gpio_132, gpio_133, + gpio_134, gpio_135, gpio_136, gpio_137, gpio_138, gpio_139, + gpio_140, gpio_141, gpio_142, gpio_143, gpio_144, gpio_145, + gpio_146, gpio_147, gpio_148, gpio_149, gpio_150, gpio_151, + gpio_152, gpio_153, gpio_154, gpio_155, gpio_156, gpio_157, + gpio_158, gpio_159, gpio_160, gpio_161, gpio_162, gpio_163, + gpio_164, gpio_165, ai_i2s1_loc, ao_i2s1_loc, arm_trace_dbg_en, + csi_vdsel, ejtag_acpu_loc, ejtag_aucpu0_loc, ejtag_aucpu1_loc, + ejtag_pcpu_loc, ejtag_scpu_loc, ejtag_ve2_loc, emmc_clk, + emmc_cmd, emmc_data_0, emmc_data_1, emmc_data_2, emmc_data_3, + emmc_data_4, emmc_data_5, emmc_data_6, emmc_data_7, + emmc_dd_sb, emmc_rst_n, etn_phy_loc, hif_clk, hif_data, + hif_en, hif_rdy, hi_width, i2c6_loc, ir_rx_loc, rgmii_vdsel, + sf_en, spdif_in_mode, spdif_loc, uart0_loc, usb_cc1, usb_cc2, + ve4_uart_loc] + + function: + enum: [gpio, ai_i2s0, ai_i2s2, ai_tdm0, ai_tdm1, ai_tdm2, ao_i2s0, + ao_i2s2, ao_tdm0, ao_tdm1, ao_tdm2, csi0, csi1, csi_1v2, csi_1v8, + csi_2v5, csi_3v3, dmic0, dmic1, dmic2, dptx_hpd, edptx_hdp, emmc, + gspi0, gspi1, gspi2, hi_width_1bit, hi_width_disable, i2c0, i2c1, + i2c3, i2c4, i2c5, i2c7, iso_tristate, pcie0, pcie1, pcm, pctrl, + pwm4, pwm5, pwm6, rgmii, rgmii_1v2, rgmii_1v8, rgmii_2v5, + rgmii_3v3, rmii, sd, sdio, sf_disable, sf_enable, + spdif_in_coaxial, spdif_in_gpio, spdif_out, spi, ts0, ts1, uart1, + uart2, uart3, uart4, uart5, uart6, uart7, uart8, uart9, uart10, + usb_cc1, usb_cc2, vi0_dtv, vi1_dtv, vtc_ao_i2s, vtc_dmic, + vtc_i2s, ai_i2s1_loc0, ai_i2s1_loc1, ao_i2s0_loc0, ao_i2s0_loc1, + ao_i2s1_loc0, ao_i2s1_loc1, ao_tdm1_loc0, ao_tdm1_loc1, + etn_led_loc0, etn_led_loc1, etn_phy_loc0, etn_phy_loc1, + i2c6_loc0, i2c6_loc1, ir_rx_loc0, ir_rx_loc1, pwm0_loc0, + pwm0_loc1, pwm0_loc2, pwm0_loc3, pwm1_loc0, pwm1_loc1, pwm2_loc0, + pwm2_loc1, pwm3_loc0, pwm3_loc1, spdif_loc0, spdif_loc1, + uart0_loc0, uart0_loc1, ve4_uart_loc0, ve4_uart_loc1, + ve4_uart_loc2, acpu_ejtag_loc0, acpu_ejtag_loc1, acpu_ejtag_loc2, + aucpu0_ejtag_loc0, aucpu0_ejtag_loc1, aucpu0_ejtag_loc2, + aucpu1_ejtag_loc0, aucpu1_ejtag_loc1, aucpu1_ejtag_loc2, + aupu0_ejtag_loc1, aupu1_ejtag_loc1, gpu_ejtag_loc0, + pcpu_ejtag_loc0, pcpu_ejtag_loc1, pcpu_ejtag_loc2, + scpu_ejtag_loc0, scpu_ejtag_loc1, scpu_ejtag_loc2, + ve2_ejtag_loc0, ve2_ejtag_loc1, ve2_ejtag_loc2, pll_test_loc0, + pll_test_loc1, dbg_out1, isom_dbg_out, arm_trace_debug_disable, + arm_trace_debug_enable] + + drive-strength: + enum: [4, 8] + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + input-voltage-microvolt: + description: | + Select the input receiver voltage domain for the pin. + Valid arguments are: + - 1800000: 1.8V input logic level + - 3300000: 3.3V input logic level + enum: [1800000, 3300000] + + drive-push-pull: true + + power-source: + description: | + Valid arguments are described as below: + 0: power supply of 1.8V + 1: power supply of 3.3V + enum: [0, 1] + + slew-rate: + description: | + Valid arguments are described as below: + 1: ~1ns falling time + 10: ~10ns falling time + 20: ~20ns falling time + 30: ~30ns falling time + enum: [1, 10, 20, 30] + + realtek,drive-strength-p: + description: | + Some of pins can be driven using the P-MOS and N-MOS transistor to + achieve finer adjustments. The block-diagram representation is as + follows: + VDD + | + ||--+ + +-----o|| P-MOS-FET + | ||--+ + IN --+ +----- out + | ||--+ + +------|| N-MOS-FET + ||--+ + | + GND + The driving strength of the P-MOS/N-MOS transistors impacts the + waveform's rise/fall times. Greater driving strength results in + shorter rise/fall times. Each P-MOS and N-MOS transistor offers + 8 configurable levels (0 to 7), with higher values indicating + greater driving strength, contributing to achieving the desired + speed. + + The realtek,drive-strength-p is used to control the driving strength + of the P-MOS output. + + This value is not a simple count of transistors. Instead, it + represents a weighted configuration. There is a base driving + capability (even at value 0), and each bit adds a different weight to + the total strength. The resulting current is non-linear and varies + significantly based on the IO voltage (1.8V vs 3.3V) and the specific + pad group. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + realtek,drive-strength-n: + description: | + Similar to the realtek,drive-strength-p, the realtek,drive-strength-n + is used to control the driving strength of the N-MOS output. + + This property uses the same weighted configuration logic where values + 0-7 represent non-linear strength adjustments rather than a transistor + count. + + Higher values indicate greater driving strength, resulting in shorter + fall times. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + realtek,duty-cycle: + description: | + An integer describing the level to adjust the output pulse width, it + provides a fixed nanosecond-level adjustment to the rising/falling + edges of an existing signal. It is used for Signal Integrity tuning + (adding/subtracting delay to fine-tune the high/low duration), rather + than generating a specific PWM frequency. + + Valid arguments are described as below: + 0: 0ns + 2: + 0.25ns + 3: + 0.5ns + 4: -0.25ns + 5: -0.5ns + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 2, 3, 4, 5] + + realtek,high-vil-microvolt: + description: | + The threshold value for the input receiver's LOW recognition (VIL). + + This property is used to address specific HDMI I2C compatibility + issues where some sinks (TVs) have weak pull-down capabilities and + fail to pull the bus voltage below the standard VIL threshold + (~0.7V). + + Setting this property to 1100000 (1.1V) enables a specialized input + receiver mode that raises the effective VIL threshold to improve + detection. + enum: [1100000] + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@4e000 { + compatible = "realtek,rtd1625-iso-pinctrl"; + reg = <0x4e000 0x130>; + + emmc-hs200-pins { + pins = "emmc_clk", + "emmc_cmd", + "emmc_data_0", + "emmc_data_1", + "emmc_data_2", + "emmc_data_3", + "emmc_data_4", + "emmc_data_5", + "emmc_data_6", + "emmc_data_7"; + function = "emmc"; + realtek,drive-strength-p = <2>; + realtek,drive-strength-n = <2>; + }; + + i2c-0-pins { + pins = "gpio_12", + "gpio_13"; + function = "i2c0"; + drive-strength = <4>; + }; + }; From dcc9334435b0fd34adcca96cc397a30915c882d9 Mon Sep 17 00:00:00 2001 From: Tzuyi Chang Date: Tue, 17 Mar 2026 19:54:08 +0800 Subject: [PATCH 60/84] pinctrl: realtek: add support for slew rate, input voltage and high VIL Add support for configuring slew rate, input voltage level and high VIL mode. This involves updating the pin configuration parsing logic to handle PIN_CONFIG_SLEW_RATE, PIN_CONFIG_INPUT_VOLTAGE_UV and the new custom property "realtek,high-vil-microvolt". Reviewed-by: Linus Walleij Signed-off-by: Tzuyi Chang Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin Signed-off-by: Linus Walleij --- drivers/pinctrl/realtek/pinctrl-rtd.c | 66 ++++++++++++++++++++++++++- drivers/pinctrl/realtek/pinctrl-rtd.h | 3 ++ 2 files changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c index b645277ac9a9..a2c672508a4b 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd.c +++ b/drivers/pinctrl/realtek/pinctrl-rtd.c @@ -37,11 +37,13 @@ struct rtd_pinctrl { #define RTD_DRIVE_STRENGH_P (PIN_CONFIG_END + 1) #define RTD_DRIVE_STRENGH_N (PIN_CONFIG_END + 2) #define RTD_DUTY_CYCLE (PIN_CONFIG_END + 3) +#define RTD_HIGH_VIL (PIN_CONFIG_END + 4) static const struct pinconf_generic_params rtd_custom_bindings[] = { {"realtek,drive-strength-p", RTD_DRIVE_STRENGH_P, 0}, {"realtek,drive-strength-n", RTD_DRIVE_STRENGH_N, 0}, {"realtek,duty-cycle", RTD_DUTY_CYCLE, 0}, + {"realtek,high-vil-microvolt", RTD_HIGH_VIL, 0}, }; static int rtd_pinctrl_get_groups_count(struct pinctrl_dev *pcdev) @@ -288,7 +290,8 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, u16 strength; u32 val; u32 mask; - u32 pulsel_off, pulen_off, smt_off, curr_off, pow_off, reg_off, p_off, n_off; + u32 pulsel_off, pulen_off, smt_off, curr_off, pow_off, reg_off, p_off, n_off, + input_volt_off, sr_off, hvil_off; const char *name = data->info->pins[pinnr].name; int ret = 0; @@ -409,6 +412,67 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, val = set_val ? mask : 0; break; + case PIN_CONFIG_SLEW_RATE: + if (config_desc->slew_rate_offset == NA) { + dev_err(data->dev, "Slew rate setting unsupported for pin: %s\n", name); + return -ENOTSUPP; + } + + switch (arg) { + case 1: + set_val = 0; + break; + case 10: + set_val = 1; + break; + case 20: + set_val = 2; + break; + case 30: + set_val = 3; + break; + default: + return -EINVAL; + } + + sr_off = config_desc->base_bit + config_desc->slew_rate_offset; + reg_off = config_desc->reg_offset; + mask = 0x3 << sr_off; + val = arg << sr_off; + break; + + case PIN_CONFIG_INPUT_VOLTAGE_UV: + if (config_desc->input_volt_offset == NA) { + dev_err(data->dev, "Input voltage level setting unsupported for pin:%s\n", + name); + return -ENOTSUPP; + } + + if (arg == 3300000) + set_val = 1; + else if (arg == 1800000) + set_val = 0; + else + return -EINVAL; + + input_volt_off = config_desc->base_bit + config_desc->input_volt_offset; + reg_off = config_desc->reg_offset; + + mask = BIT(input_volt_off); + val = set_val ? BIT(input_volt_off) : 0; + break; + + case RTD_HIGH_VIL: + if (config_desc->hvil_offset == NA) { + dev_err(data->dev, "High vil setting unsupported for pin:%s\n", name); + return -ENOTSUPP; + } + hvil_off = config_desc->base_bit + config_desc->hvil_offset; + reg_off = config_desc->reg_offset; + mask = BIT(hvil_off); + val = 1; + break; + case RTD_DRIVE_STRENGH_P: sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr); if (!sconfig_desc) { diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.h b/drivers/pinctrl/realtek/pinctrl-rtd.h index 7fb0955ce749..02e2d8d269b5 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd.h +++ b/drivers/pinctrl/realtek/pinctrl-rtd.h @@ -34,6 +34,9 @@ struct rtd_pin_config_desc { unsigned int smt_offset; unsigned int power_offset; unsigned int curr_type; + unsigned int input_volt_offset; + unsigned int slew_rate_offset; + unsigned int hvil_offset; }; struct rtd_pin_sconfig_desc { From e309dbd523b877f049496ecd6560fa3d9551e2d1 Mon Sep 17 00:00:00 2001 From: Tzuyi Chang Date: Tue, 17 Mar 2026 19:54:09 +0800 Subject: [PATCH 61/84] pinctrl: realtek: add rtd1625 pinctrl driver Add support for Realtek RTD1625 SoC using the realtek common pinctrl driver. This patch introduces the RTK_PIN_CONFIG_V2 and RTK_PIN_CONFIG_I2C macros, which are required to describe the specific register layout and electrical features (such as slew rate and high VIL) of the RTD1625 pins. Signed-off-by: Tzuyi Chang Signed-off-by: Yu-Chun Lin Signed-off-by: Linus Walleij --- drivers/pinctrl/realtek/Kconfig | 14 + drivers/pinctrl/realtek/Makefile | 1 + drivers/pinctrl/realtek/pinctrl-rtd.h | 34 + drivers/pinctrl/realtek/pinctrl-rtd1625.c | 3138 +++++++++++++++++++++ 4 files changed, 3187 insertions(+) create mode 100644 drivers/pinctrl/realtek/pinctrl-rtd1625.c diff --git a/drivers/pinctrl/realtek/Kconfig b/drivers/pinctrl/realtek/Kconfig index 400c9e5b16ad..054e85db99e7 100644 --- a/drivers/pinctrl/realtek/Kconfig +++ b/drivers/pinctrl/realtek/Kconfig @@ -22,3 +22,17 @@ config PINCTRL_RTD1315E tristate "Realtek DHC 1315E pin controller driver" depends on PINCTRL_RTD default y + +config PINCTRL_RTD1625 + tristate "Realtek DHC 1625 pin controller driver" + depends on PINCTRL_RTD + default y + help + This driver enables support for the pin controller on the Realtek + RTD1625 SoCs. + + It implements pin multiplexing for function selection and GPIO enabling. + It also utilizes the generic pin configuration interface to manage + electrical properties for both individual pins and pin groups. + + Say Y here to enable the pinctrl driver for RTD1625 SoCs \ No newline at end of file diff --git a/drivers/pinctrl/realtek/Makefile b/drivers/pinctrl/realtek/Makefile index c7bace0001e9..59562543396c 100644 --- a/drivers/pinctrl/realtek/Makefile +++ b/drivers/pinctrl/realtek/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PINCTRL_RTD) += pinctrl-rtd.o obj-$(CONFIG_PINCTRL_RTD1619B) += pinctrl-rtd1619b.o obj-$(CONFIG_PINCTRL_RTD1319D) += pinctrl-rtd1319d.o obj-$(CONFIG_PINCTRL_RTD1315E) += pinctrl-rtd1315e.o +obj-$(CONFIG_PINCTRL_RTD1625) += pinctrl-rtd1625.o \ No newline at end of file diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.h b/drivers/pinctrl/realtek/pinctrl-rtd.h index 02e2d8d269b5..77c30ea76443 100644 --- a/drivers/pinctrl/realtek/pinctrl-rtd.h +++ b/drivers/pinctrl/realtek/pinctrl-rtd.h @@ -98,6 +98,40 @@ struct rtd_pin_reg_list { .curr_type = _curr_type, \ } +#define RTK_PIN_CONFIG_V2(_name, _reg_off, _base_bit, _pud_en_off, \ + _pud_sel_off, _curr_off, _smt_off, _pow_off, _input_volt_off, \ + _curr_type) \ + { \ + .name = # _name, \ + .reg_offset = _reg_off, \ + .base_bit = _base_bit, \ + .pud_en_offset = _pud_en_off, \ + .pud_sel_offset = _pud_sel_off, \ + .curr_offset = _curr_off, \ + .smt_offset = _smt_off, \ + .power_offset = _pow_off, \ + .input_volt_offset = _input_volt_off, \ + .curr_type = _curr_type, \ + } + +#define RTK_PIN_CONFIG_I2C(_name, _reg_off, _base_bit, _pud_en_off, \ + _pud_sel_off, _curr_off, _smt_off, _hvil_off, _sr_off, _pow_off, \ + _input_volt_off, _curr_type) \ + { \ + .name = # _name, \ + .reg_offset = _reg_off, \ + .base_bit = _base_bit, \ + .pud_en_offset = _pud_en_off, \ + .pud_sel_offset = _pud_sel_off, \ + .curr_offset = _curr_off, \ + .smt_offset = _smt_off, \ + .hvil_offset = _hvil_off, \ + .slew_rate_offset = _sr_off, \ + .power_offset = _pow_off, \ + .input_volt_offset = _input_volt_off, \ + .curr_type = _curr_type, \ + } + #define RTK_PIN_SCONFIG(_name, _reg_off, _d_offset, _d_mask, \ _n_offset, _n_mask, _p_offset, _p_mask) \ { \ diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1625.c b/drivers/pinctrl/realtek/pinctrl-rtd1625.c new file mode 100644 index 000000000000..2d623bdbf9ca --- /dev/null +++ b/drivers/pinctrl/realtek/pinctrl-rtd1625.c @@ -0,0 +1,3138 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek DHC 1625 pin controller driver + * + * Copyright (c) 2023 Realtek Semiconductor Corp. + * + */ + +#include +#include +#include +#include + +#include "pinctrl-rtd.h" + +enum rtd1625_iso_pins_enum { + RTD1625_ISO_GPIO_8 = 0, + RTD1625_ISO_GPIO_9, + RTD1625_ISO_GPIO_10, + RTD1625_ISO_GPIO_11, + RTD1625_ISO_USB_CC1, + RTD1625_ISO_USB_CC2, + RTD1625_ISO_GPIO_45, + RTD1625_ISO_GPIO_46, + RTD1625_ISO_GPIO_47, + RTD1625_ISO_GPIO_48, + RTD1625_ISO_GPIO_49, + RTD1625_ISO_GPIO_50, + RTD1625_ISO_GPIO_52, + RTD1625_ISO_GPIO_94, + RTD1625_ISO_GPIO_95, + RTD1625_ISO_GPIO_96, + RTD1625_ISO_GPIO_97, + RTD1625_ISO_GPIO_98, + RTD1625_ISO_GPIO_99, + RTD1625_ISO_GPIO_100, + RTD1625_ISO_GPIO_101, + RTD1625_ISO_GPIO_102, + RTD1625_ISO_GPIO_103, + RTD1625_ISO_GPIO_104, + RTD1625_ISO_GPIO_105, + RTD1625_ISO_GPIO_106, + RTD1625_ISO_GPIO_107, + RTD1625_ISO_GPIO_108, + RTD1625_ISO_GPIO_109, + RTD1625_ISO_GPIO_110, + RTD1625_ISO_GPIO_111, + RTD1625_ISO_GPIO_112, + RTD1625_ISO_GPIO_128, + RTD1625_ISO_GPIO_129, + RTD1625_ISO_GPIO_130, + RTD1625_ISO_GPIO_131, + RTD1625_ISO_GPIO_145, + RTD1625_ISO_GPIO_146, + RTD1625_ISO_GPIO_147, + RTD1625_ISO_GPIO_148, + RTD1625_ISO_GPIO_149, + RTD1625_ISO_GPIO_150, + RTD1625_ISO_GPIO_151, + RTD1625_ISO_GPIO_152, + RTD1625_ISO_GPIO_153, + RTD1625_ISO_GPIO_154, + RTD1625_ISO_GPIO_155, + RTD1625_ISO_GPIO_156, + RTD1625_ISO_GPIO_157, + RTD1625_ISO_GPIO_158, + RTD1625_ISO_GPIO_159, + RTD1625_ISO_GPIO_160, + RTD1625_ISO_GPIO_161, + RTD1625_ISO_GPIO_162, + RTD1625_ISO_GPIO_163, + RTD1625_ISO_HI_WIDTH, + RTD1625_ISO_SF_EN, + RTD1625_ISO_ARM_TRACE_DBG_EN, + RTD1625_ISO_EJTAG_AUCPU0_LOC, + RTD1625_ISO_EJTAG_AUCPU1_LOC, + RTD1625_ISO_EJTAG_VE2_LOC, + RTD1625_ISO_EJTAG_SCPU_LOC, + RTD1625_ISO_EJTAG_PCPU_LOC, + RTD1625_ISO_EJTAG_ACPU_LOC, + RTD1625_ISO_I2C6_LOC, + RTD1625_ISO_UART0_LOC, + RTD1625_ISO_AI_I2S1_LOC, + RTD1625_ISO_AO_I2S1_LOC, + RTD1625_ISO_ETN_PHY_LOC, + RTD1625_ISO_SPDIF_LOC, + RTD1625_ISO_RGMII_VDSEL, + RTD1625_ISO_CSI_VDSEL, + RTD1625_ISO_SPDIF_IN_MODE, +}; + +static const struct pinctrl_pin_desc rtd1625_iso_pins[] = { + PINCTRL_PIN(RTD1625_ISO_GPIO_8, "gpio_8"), + PINCTRL_PIN(RTD1625_ISO_GPIO_9, "gpio_9"), + PINCTRL_PIN(RTD1625_ISO_GPIO_10, "gpio_10"), + PINCTRL_PIN(RTD1625_ISO_GPIO_11, "gpio_11"), + PINCTRL_PIN(RTD1625_ISO_USB_CC1, "usb_cc1"), + PINCTRL_PIN(RTD1625_ISO_USB_CC2, "usb_cc2"), + PINCTRL_PIN(RTD1625_ISO_GPIO_45, "gpio_45"), + PINCTRL_PIN(RTD1625_ISO_GPIO_46, "gpio_46"), + PINCTRL_PIN(RTD1625_ISO_GPIO_47, "gpio_47"), + PINCTRL_PIN(RTD1625_ISO_GPIO_48, "gpio_48"), + PINCTRL_PIN(RTD1625_ISO_GPIO_49, "gpio_49"), + PINCTRL_PIN(RTD1625_ISO_GPIO_50, "gpio_50"), + PINCTRL_PIN(RTD1625_ISO_GPIO_52, "gpio_52"), + PINCTRL_PIN(RTD1625_ISO_GPIO_94, "gpio_94"), + PINCTRL_PIN(RTD1625_ISO_GPIO_95, "gpio_95"), + PINCTRL_PIN(RTD1625_ISO_GPIO_96, "gpio_96"), + PINCTRL_PIN(RTD1625_ISO_GPIO_97, "gpio_97"), + PINCTRL_PIN(RTD1625_ISO_GPIO_98, "gpio_98"), + PINCTRL_PIN(RTD1625_ISO_GPIO_99, "gpio_99"), + PINCTRL_PIN(RTD1625_ISO_GPIO_100, "gpio_100"), + PINCTRL_PIN(RTD1625_ISO_GPIO_101, "gpio_101"), + PINCTRL_PIN(RTD1625_ISO_GPIO_102, "gpio_102"), + PINCTRL_PIN(RTD1625_ISO_GPIO_103, "gpio_103"), + PINCTRL_PIN(RTD1625_ISO_GPIO_104, "gpio_104"), + PINCTRL_PIN(RTD1625_ISO_GPIO_105, "gpio_105"), + PINCTRL_PIN(RTD1625_ISO_GPIO_106, "gpio_106"), + PINCTRL_PIN(RTD1625_ISO_GPIO_107, "gpio_107"), + PINCTRL_PIN(RTD1625_ISO_GPIO_108, "gpio_108"), + PINCTRL_PIN(RTD1625_ISO_GPIO_109, "gpio_109"), + PINCTRL_PIN(RTD1625_ISO_GPIO_110, "gpio_110"), + PINCTRL_PIN(RTD1625_ISO_GPIO_111, "gpio_111"), + PINCTRL_PIN(RTD1625_ISO_GPIO_112, "gpio_112"), + PINCTRL_PIN(RTD1625_ISO_GPIO_128, "gpio_128"), + PINCTRL_PIN(RTD1625_ISO_GPIO_129, "gpio_129"), + PINCTRL_PIN(RTD1625_ISO_GPIO_130, "gpio_130"), + PINCTRL_PIN(RTD1625_ISO_GPIO_131, "gpio_131"), + PINCTRL_PIN(RTD1625_ISO_GPIO_145, "gpio_145"), + PINCTRL_PIN(RTD1625_ISO_GPIO_146, "gpio_146"), + PINCTRL_PIN(RTD1625_ISO_GPIO_147, "gpio_147"), + PINCTRL_PIN(RTD1625_ISO_GPIO_148, "gpio_148"), + PINCTRL_PIN(RTD1625_ISO_GPIO_149, "gpio_149"), + PINCTRL_PIN(RTD1625_ISO_GPIO_150, "gpio_150"), + PINCTRL_PIN(RTD1625_ISO_GPIO_151, "gpio_151"), + PINCTRL_PIN(RTD1625_ISO_GPIO_152, "gpio_152"), + PINCTRL_PIN(RTD1625_ISO_GPIO_153, "gpio_153"), + PINCTRL_PIN(RTD1625_ISO_GPIO_154, "gpio_154"), + PINCTRL_PIN(RTD1625_ISO_GPIO_155, "gpio_155"), + PINCTRL_PIN(RTD1625_ISO_GPIO_156, "gpio_156"), + PINCTRL_PIN(RTD1625_ISO_GPIO_157, "gpio_157"), + PINCTRL_PIN(RTD1625_ISO_GPIO_158, "gpio_158"), + PINCTRL_PIN(RTD1625_ISO_GPIO_159, "gpio_159"), + PINCTRL_PIN(RTD1625_ISO_GPIO_160, "gpio_160"), + PINCTRL_PIN(RTD1625_ISO_GPIO_161, "gpio_161"), + PINCTRL_PIN(RTD1625_ISO_GPIO_162, "gpio_162"), + PINCTRL_PIN(RTD1625_ISO_GPIO_163, "gpio_163"), + PINCTRL_PIN(RTD1625_ISO_HI_WIDTH, "hi_width"), + PINCTRL_PIN(RTD1625_ISO_SF_EN, "sf_en"), + PINCTRL_PIN(RTD1625_ISO_ARM_TRACE_DBG_EN, "arm_trace_dbg_en"), + PINCTRL_PIN(RTD1625_ISO_EJTAG_AUCPU0_LOC, "ejtag_aucpu0_loc"), + PINCTRL_PIN(RTD1625_ISO_EJTAG_AUCPU1_LOC, "ejtag_aucpu1_loc"), + PINCTRL_PIN(RTD1625_ISO_EJTAG_VE2_LOC, "ejtag_ve2_loc"), + PINCTRL_PIN(RTD1625_ISO_EJTAG_SCPU_LOC, "ejtag_scpu_loc"), + PINCTRL_PIN(RTD1625_ISO_EJTAG_PCPU_LOC, "ejtag_pcpu_loc"), + PINCTRL_PIN(RTD1625_ISO_EJTAG_ACPU_LOC, "ejtag_acpu_loc"), + PINCTRL_PIN(RTD1625_ISO_I2C6_LOC, "i2c6_loc"), + PINCTRL_PIN(RTD1625_ISO_UART0_LOC, "uart0_loc"), + PINCTRL_PIN(RTD1625_ISO_AI_I2S1_LOC, "ai_i2s1_loc"), + PINCTRL_PIN(RTD1625_ISO_AO_I2S1_LOC, "ao_i2s1_loc"), + PINCTRL_PIN(RTD1625_ISO_ETN_PHY_LOC, "etn_phy_loc"), + PINCTRL_PIN(RTD1625_ISO_SPDIF_LOC, "spdif_loc"), + PINCTRL_PIN(RTD1625_ISO_RGMII_VDSEL, "rgmii_vdsel"), + PINCTRL_PIN(RTD1625_ISO_CSI_VDSEL, "csi_vdsel"), + PINCTRL_PIN(RTD1625_ISO_SPDIF_IN_MODE, "spdif_in_mode"), +}; + +enum rtd1625_isom_pins_enum { + RTD1625_ISOM_GPIO_0 = 0, + RTD1625_ISOM_GPIO_1, + RTD1625_ISOM_GPIO_28, + RTD1625_ISOM_GPIO_29, + RTD1625_ISOM_IR_RX_LOC, +}; + +static const struct pinctrl_pin_desc rtd1625_isom_pins[] = { + PINCTRL_PIN(RTD1625_ISOM_GPIO_0, "gpio_0"), + PINCTRL_PIN(RTD1625_ISOM_GPIO_1, "gpio_1"), + PINCTRL_PIN(RTD1625_ISOM_GPIO_28, "gpio_28"), + PINCTRL_PIN(RTD1625_ISOM_GPIO_29, "gpio_29"), + PINCTRL_PIN(RTD1625_ISOM_IR_RX_LOC, "ir_rx_loc"), +}; + +enum rtd1625_ve4_pins_enum { + RTD1625_VE4_GPIO_2 = 0, + RTD1625_VE4_GPIO_3, + RTD1625_VE4_GPIO_4, + RTD1625_VE4_GPIO_5, + RTD1625_VE4_GPIO_6, + RTD1625_VE4_GPIO_7, + RTD1625_VE4_GPIO_12, + RTD1625_VE4_GPIO_13, + RTD1625_VE4_GPIO_16, + RTD1625_VE4_GPIO_17, + RTD1625_VE4_GPIO_18, + RTD1625_VE4_GPIO_19, + RTD1625_VE4_GPIO_23, + RTD1625_VE4_GPIO_24, + RTD1625_VE4_GPIO_25, + RTD1625_VE4_GPIO_30, + RTD1625_VE4_GPIO_31, + RTD1625_VE4_GPIO_32, + RTD1625_VE4_GPIO_33, + RTD1625_VE4_GPIO_34, + RTD1625_VE4_GPIO_35, + RTD1625_VE4_GPIO_42, + RTD1625_VE4_GPIO_43, + RTD1625_VE4_GPIO_44, + RTD1625_VE4_GPIO_51, + RTD1625_VE4_GPIO_53, + RTD1625_VE4_GPIO_54, + RTD1625_VE4_GPIO_55, + RTD1625_VE4_GPIO_56, + RTD1625_VE4_GPIO_57, + RTD1625_VE4_GPIO_58, + RTD1625_VE4_GPIO_59, + RTD1625_VE4_GPIO_60, + RTD1625_VE4_GPIO_61, + RTD1625_VE4_GPIO_62, + RTD1625_VE4_GPIO_63, + RTD1625_VE4_GPIO_92, + RTD1625_VE4_GPIO_93, + RTD1625_VE4_GPIO_132, + RTD1625_VE4_GPIO_133, + RTD1625_VE4_GPIO_134, + RTD1625_VE4_GPIO_135, + RTD1625_VE4_GPIO_136, + RTD1625_VE4_GPIO_137, + RTD1625_VE4_GPIO_138, + RTD1625_VE4_GPIO_139, + RTD1625_VE4_GPIO_140, + RTD1625_VE4_GPIO_141, + RTD1625_VE4_GPIO_142, + RTD1625_VE4_GPIO_143, + RTD1625_VE4_GPIO_144, + RTD1625_VE4_GPIO_164, + RTD1625_VE4_GPIO_165, + RTD1625_VE4_UART_LOC, +}; + +static const struct pinctrl_pin_desc rtd1625_ve4_pins[] = { + PINCTRL_PIN(RTD1625_VE4_GPIO_2, "gpio_2"), + PINCTRL_PIN(RTD1625_VE4_GPIO_3, "gpio_3"), + PINCTRL_PIN(RTD1625_VE4_GPIO_4, "gpio_4"), + PINCTRL_PIN(RTD1625_VE4_GPIO_5, "gpio_5"), + PINCTRL_PIN(RTD1625_VE4_GPIO_6, "gpio_6"), + PINCTRL_PIN(RTD1625_VE4_GPIO_7, "gpio_7"), + PINCTRL_PIN(RTD1625_VE4_GPIO_12, "gpio_12"), + PINCTRL_PIN(RTD1625_VE4_GPIO_13, "gpio_13"), + PINCTRL_PIN(RTD1625_VE4_GPIO_16, "gpio_16"), + PINCTRL_PIN(RTD1625_VE4_GPIO_17, "gpio_17"), + PINCTRL_PIN(RTD1625_VE4_GPIO_18, "gpio_18"), + PINCTRL_PIN(RTD1625_VE4_GPIO_19, "gpio_19"), + PINCTRL_PIN(RTD1625_VE4_GPIO_23, "gpio_23"), + PINCTRL_PIN(RTD1625_VE4_GPIO_24, "gpio_24"), + PINCTRL_PIN(RTD1625_VE4_GPIO_25, "gpio_25"), + PINCTRL_PIN(RTD1625_VE4_GPIO_30, "gpio_30"), + PINCTRL_PIN(RTD1625_VE4_GPIO_31, "gpio_31"), + PINCTRL_PIN(RTD1625_VE4_GPIO_32, "gpio_32"), + PINCTRL_PIN(RTD1625_VE4_GPIO_33, "gpio_33"), + PINCTRL_PIN(RTD1625_VE4_GPIO_34, "gpio_34"), + PINCTRL_PIN(RTD1625_VE4_GPIO_35, "gpio_35"), + PINCTRL_PIN(RTD1625_VE4_GPIO_42, "gpio_42"), + PINCTRL_PIN(RTD1625_VE4_GPIO_43, "gpio_43"), + PINCTRL_PIN(RTD1625_VE4_GPIO_44, "gpio_44"), + PINCTRL_PIN(RTD1625_VE4_GPIO_51, "gpio_51"), + PINCTRL_PIN(RTD1625_VE4_GPIO_53, "gpio_53"), + PINCTRL_PIN(RTD1625_VE4_GPIO_54, "gpio_54"), + PINCTRL_PIN(RTD1625_VE4_GPIO_55, "gpio_55"), + PINCTRL_PIN(RTD1625_VE4_GPIO_56, "gpio_56"), + PINCTRL_PIN(RTD1625_VE4_GPIO_57, "gpio_57"), + PINCTRL_PIN(RTD1625_VE4_GPIO_58, "gpio_58"), + PINCTRL_PIN(RTD1625_VE4_GPIO_59, "gpio_59"), + PINCTRL_PIN(RTD1625_VE4_GPIO_60, "gpio_60"), + PINCTRL_PIN(RTD1625_VE4_GPIO_61, "gpio_61"), + PINCTRL_PIN(RTD1625_VE4_GPIO_62, "gpio_62"), + PINCTRL_PIN(RTD1625_VE4_GPIO_63, "gpio_63"), + PINCTRL_PIN(RTD1625_VE4_GPIO_92, "gpio_92"), + PINCTRL_PIN(RTD1625_VE4_GPIO_93, "gpio_93"), + PINCTRL_PIN(RTD1625_VE4_GPIO_132, "gpio_132"), + PINCTRL_PIN(RTD1625_VE4_GPIO_133, "gpio_133"), + PINCTRL_PIN(RTD1625_VE4_GPIO_134, "gpio_134"), + PINCTRL_PIN(RTD1625_VE4_GPIO_135, "gpio_135"), + PINCTRL_PIN(RTD1625_VE4_GPIO_136, "gpio_136"), + PINCTRL_PIN(RTD1625_VE4_GPIO_137, "gpio_137"), + PINCTRL_PIN(RTD1625_VE4_GPIO_138, "gpio_138"), + PINCTRL_PIN(RTD1625_VE4_GPIO_139, "gpio_139"), + PINCTRL_PIN(RTD1625_VE4_GPIO_140, "gpio_140"), + PINCTRL_PIN(RTD1625_VE4_GPIO_141, "gpio_141"), + PINCTRL_PIN(RTD1625_VE4_GPIO_142, "gpio_142"), + PINCTRL_PIN(RTD1625_VE4_GPIO_143, "gpio_143"), + PINCTRL_PIN(RTD1625_VE4_GPIO_144, "gpio_144"), + PINCTRL_PIN(RTD1625_VE4_GPIO_164, "gpio_164"), + PINCTRL_PIN(RTD1625_VE4_GPIO_165, "gpio_165"), + PINCTRL_PIN(RTD1625_VE4_UART_LOC, "ve4_uart_loc"), +}; + +enum rtd1625_main2_pins_enum { + RTD1625_MAIN2_GPIO_14 = 0, + RTD1625_MAIN2_GPIO_15, + RTD1625_MAIN2_GPIO_20, + RTD1625_MAIN2_GPIO_21, + RTD1625_MAIN2_GPIO_22, + RTD1625_MAIN2_HIF_DATA, + RTD1625_MAIN2_HIF_EN, + RTD1625_MAIN2_HIF_RDY, + RTD1625_MAIN2_HIF_CLK, + RTD1625_MAIN2_GPIO_40, + RTD1625_MAIN2_GPIO_41, + RTD1625_MAIN2_GPIO_64, + RTD1625_MAIN2_GPIO_65, + RTD1625_MAIN2_GPIO_66, + RTD1625_MAIN2_GPIO_67, + RTD1625_MAIN2_EMMC_DATA_0, + RTD1625_MAIN2_EMMC_DATA_1, + RTD1625_MAIN2_EMMC_DATA_2, + RTD1625_MAIN2_EMMC_DATA_3, + RTD1625_MAIN2_EMMC_DATA_4, + RTD1625_MAIN2_EMMC_DATA_5, + RTD1625_MAIN2_EMMC_DATA_6, + RTD1625_MAIN2_EMMC_DATA_7, + RTD1625_MAIN2_EMMC_RST_N, + RTD1625_MAIN2_EMMC_CMD, + RTD1625_MAIN2_EMMC_CLK, + RTD1625_MAIN2_EMMC_DD_SB, + RTD1625_MAIN2_GPIO_80, + RTD1625_MAIN2_GPIO_81, + RTD1625_MAIN2_GPIO_82, + RTD1625_MAIN2_GPIO_83, + RTD1625_MAIN2_GPIO_84, + RTD1625_MAIN2_GPIO_85, + RTD1625_MAIN2_GPIO_86, + RTD1625_MAIN2_GPIO_87, + RTD1625_MAIN2_GPIO_88, + RTD1625_MAIN2_GPIO_89, + RTD1625_MAIN2_GPIO_90, + RTD1625_MAIN2_GPIO_91, +}; + +static const struct pinctrl_pin_desc rtd1625_main2_pins[] = { + PINCTRL_PIN(RTD1625_MAIN2_GPIO_14, "gpio_14"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_15, "gpio_15"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_20, "gpio_20"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_21, "gpio_21"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_22, "gpio_22"), + PINCTRL_PIN(RTD1625_MAIN2_HIF_DATA, "hif_data"), + PINCTRL_PIN(RTD1625_MAIN2_HIF_EN, "hif_en"), + PINCTRL_PIN(RTD1625_MAIN2_HIF_RDY, "hif_rdy"), + PINCTRL_PIN(RTD1625_MAIN2_HIF_CLK, "hif_clk"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_40, "gpio_40"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_41, "gpio_41"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_64, "gpio_64"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_65, "gpio_65"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_66, "gpio_66"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_67, "gpio_67"), + PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_0, "emmc_data_0"), + PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_1, "emmc_data_1"), + PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_2, "emmc_data_2"), + PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_3, "emmc_data_3"), + PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_4, "emmc_data_4"), + PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_5, "emmc_data_5"), + PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_6, "emmc_data_6"), + PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_7, "emmc_data_7"), + PINCTRL_PIN(RTD1625_MAIN2_EMMC_RST_N, "emmc_rst_n"), + PINCTRL_PIN(RTD1625_MAIN2_EMMC_CMD, "emmc_cmd"), + PINCTRL_PIN(RTD1625_MAIN2_EMMC_CLK, "emmc_clk"), + PINCTRL_PIN(RTD1625_MAIN2_EMMC_DD_SB, "emmc_dd_sb"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_80, "gpio_80"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_81, "gpio_81"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_82, "gpio_82"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_83, "gpio_83"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_84, "gpio_84"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_85, "gpio_85"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_86, "gpio_86"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_87, "gpio_87"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_88, "gpio_88"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_89, "gpio_89"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_90, "gpio_90"), + PINCTRL_PIN(RTD1625_MAIN2_GPIO_91, "gpio_91"), +}; + +#define DECLARE_RTD1625_PIN(_pin, _name) \ + static const unsigned int rtd1625_##_name##_pins[] = { _pin } + +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_8, gpio_8); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_9, gpio_9); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_10, gpio_10); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_11, gpio_11); +DECLARE_RTD1625_PIN(RTD1625_ISO_USB_CC1, usb_cc1); +DECLARE_RTD1625_PIN(RTD1625_ISO_USB_CC2, usb_cc2); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_45, gpio_45); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_46, gpio_46); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_47, gpio_47); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_48, gpio_48); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_49, gpio_49); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_50, gpio_50); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_52, gpio_52); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_94, gpio_94); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_95, gpio_95); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_96, gpio_96); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_97, gpio_97); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_98, gpio_98); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_99, gpio_99); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_100, gpio_100); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_101, gpio_101); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_102, gpio_102); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_103, gpio_103); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_104, gpio_104); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_105, gpio_105); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_106, gpio_106); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_107, gpio_107); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_108, gpio_108); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_109, gpio_109); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_110, gpio_110); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_111, gpio_111); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_112, gpio_112); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_128, gpio_128); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_129, gpio_129); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_130, gpio_130); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_131, gpio_131); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_145, gpio_145); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_146, gpio_146); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_147, gpio_147); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_148, gpio_148); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_149, gpio_149); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_150, gpio_150); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_151, gpio_151); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_152, gpio_152); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_153, gpio_153); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_154, gpio_154); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_155, gpio_155); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_156, gpio_156); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_157, gpio_157); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_158, gpio_158); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_159, gpio_159); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_160, gpio_160); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_161, gpio_161); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_162, gpio_162); +DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_163, gpio_163); + +DECLARE_RTD1625_PIN(RTD1625_ISO_HI_WIDTH, hi_width); +DECLARE_RTD1625_PIN(RTD1625_ISO_SF_EN, sf_en); +DECLARE_RTD1625_PIN(RTD1625_ISO_ARM_TRACE_DBG_EN, arm_trace_dbg_en); +DECLARE_RTD1625_PIN(RTD1625_ISO_EJTAG_AUCPU0_LOC, ejtag_aucpu0_loc); +DECLARE_RTD1625_PIN(RTD1625_ISO_EJTAG_AUCPU1_LOC, ejtag_aucpu1_loc); +DECLARE_RTD1625_PIN(RTD1625_ISO_EJTAG_VE2_LOC, ejtag_ve2_loc); +DECLARE_RTD1625_PIN(RTD1625_ISO_EJTAG_SCPU_LOC, ejtag_scpu_loc); +DECLARE_RTD1625_PIN(RTD1625_ISO_EJTAG_PCPU_LOC, ejtag_pcpu_loc); +DECLARE_RTD1625_PIN(RTD1625_ISO_EJTAG_ACPU_LOC, ejtag_acpu_loc); + +DECLARE_RTD1625_PIN(RTD1625_ISO_I2C6_LOC, i2c6_loc); +DECLARE_RTD1625_PIN(RTD1625_ISO_UART0_LOC, uart0_loc); +DECLARE_RTD1625_PIN(RTD1625_ISO_AI_I2S1_LOC, ai_i2s1_loc); +DECLARE_RTD1625_PIN(RTD1625_ISO_AO_I2S1_LOC, ao_i2s1_loc); +DECLARE_RTD1625_PIN(RTD1625_ISO_ETN_PHY_LOC, etn_phy_loc); +DECLARE_RTD1625_PIN(RTD1625_ISO_SPDIF_LOC, spdif_loc); +DECLARE_RTD1625_PIN(RTD1625_ISO_RGMII_VDSEL, rgmii_vdsel); +DECLARE_RTD1625_PIN(RTD1625_ISO_CSI_VDSEL, csi_vdsel); +DECLARE_RTD1625_PIN(RTD1625_ISO_SPDIF_IN_MODE, spdif_in_mode); + +DECLARE_RTD1625_PIN(RTD1625_ISOM_GPIO_0, gpio_0); +DECLARE_RTD1625_PIN(RTD1625_ISOM_GPIO_1, gpio_1); +DECLARE_RTD1625_PIN(RTD1625_ISOM_GPIO_28, gpio_28); +DECLARE_RTD1625_PIN(RTD1625_ISOM_GPIO_29, gpio_29); +DECLARE_RTD1625_PIN(RTD1625_ISOM_IR_RX_LOC, ir_rx_loc); + +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_2, gpio_2); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_3, gpio_3); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_4, gpio_4); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_5, gpio_5); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_6, gpio_6); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_7, gpio_7); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_12, gpio_12); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_13, gpio_13); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_16, gpio_16); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_17, gpio_17); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_18, gpio_18); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_19, gpio_19); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_23, gpio_23); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_24, gpio_24); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_25, gpio_25); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_30, gpio_30); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_31, gpio_31); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_32, gpio_32); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_33, gpio_33); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_34, gpio_34); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_35, gpio_35); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_42, gpio_42); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_43, gpio_43); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_44, gpio_44); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_51, gpio_51); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_53, gpio_53); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_54, gpio_54); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_55, gpio_55); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_56, gpio_56); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_57, gpio_57); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_58, gpio_58); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_59, gpio_59); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_60, gpio_60); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_61, gpio_61); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_62, gpio_62); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_63, gpio_63); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_92, gpio_92); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_93, gpio_93); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_132, gpio_132); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_133, gpio_133); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_134, gpio_134); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_135, gpio_135); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_136, gpio_136); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_137, gpio_137); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_138, gpio_138); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_139, gpio_139); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_140, gpio_140); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_141, gpio_141); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_142, gpio_142); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_143, gpio_143); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_144, gpio_144); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_164, gpio_164); +DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_165, gpio_165); +DECLARE_RTD1625_PIN(RTD1625_VE4_UART_LOC, ve4_uart_loc); + +DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_RST_N, emmc_rst_n); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DD_SB, emmc_dd_sb); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_CLK, emmc_clk); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_CMD, emmc_cmd); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_0, emmc_data_0); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_1, emmc_data_1); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_2, emmc_data_2); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_3, emmc_data_3); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_4, emmc_data_4); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_5, emmc_data_5); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_6, emmc_data_6); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_7, emmc_data_7); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_14, gpio_14); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_15, gpio_15); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_20, gpio_20); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_21, gpio_21); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_22, gpio_22); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_HIF_DATA, hif_data); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_HIF_EN, hif_en); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_HIF_RDY, hif_rdy); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_HIF_CLK, hif_clk); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_40, gpio_40); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_41, gpio_41); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_64, gpio_64); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_65, gpio_65); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_66, gpio_66); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_67, gpio_67); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_80, gpio_80); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_81, gpio_81); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_82, gpio_82); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_83, gpio_83); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_84, gpio_84); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_85, gpio_85); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_86, gpio_86); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_87, gpio_87); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_88, gpio_88); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_89, gpio_89); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_90, gpio_90); +DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_91, gpio_91); + +#define RTD1625_GROUP(_name) \ + { \ + .name = # _name, \ + .pins = rtd1625_ ## _name ## _pins, \ + .num_pins = ARRAY_SIZE(rtd1625_ ## _name ## _pins), \ + } + +static const struct rtd_pin_group_desc rtd1625_iso_pin_groups[] = { + RTD1625_GROUP(gpio_8), + RTD1625_GROUP(gpio_9), + RTD1625_GROUP(gpio_10), + RTD1625_GROUP(gpio_11), + RTD1625_GROUP(usb_cc1), + RTD1625_GROUP(usb_cc2), + RTD1625_GROUP(gpio_45), + RTD1625_GROUP(gpio_46), + RTD1625_GROUP(gpio_47), + RTD1625_GROUP(gpio_48), + RTD1625_GROUP(gpio_49), + RTD1625_GROUP(gpio_50), + RTD1625_GROUP(gpio_52), + RTD1625_GROUP(gpio_94), + RTD1625_GROUP(gpio_95), + RTD1625_GROUP(gpio_96), + RTD1625_GROUP(gpio_97), + RTD1625_GROUP(gpio_98), + RTD1625_GROUP(gpio_99), + RTD1625_GROUP(gpio_100), + RTD1625_GROUP(gpio_101), + RTD1625_GROUP(gpio_102), + RTD1625_GROUP(gpio_103), + RTD1625_GROUP(gpio_104), + RTD1625_GROUP(gpio_105), + RTD1625_GROUP(gpio_106), + RTD1625_GROUP(gpio_107), + RTD1625_GROUP(gpio_108), + RTD1625_GROUP(gpio_109), + RTD1625_GROUP(gpio_110), + RTD1625_GROUP(gpio_111), + RTD1625_GROUP(gpio_112), + RTD1625_GROUP(gpio_128), + RTD1625_GROUP(gpio_129), + RTD1625_GROUP(gpio_130), + RTD1625_GROUP(gpio_131), + RTD1625_GROUP(gpio_145), + RTD1625_GROUP(gpio_146), + RTD1625_GROUP(gpio_147), + RTD1625_GROUP(gpio_148), + RTD1625_GROUP(gpio_149), + RTD1625_GROUP(gpio_150), + RTD1625_GROUP(gpio_151), + RTD1625_GROUP(gpio_152), + RTD1625_GROUP(gpio_153), + RTD1625_GROUP(gpio_154), + RTD1625_GROUP(gpio_155), + RTD1625_GROUP(gpio_156), + RTD1625_GROUP(gpio_157), + RTD1625_GROUP(gpio_158), + RTD1625_GROUP(gpio_159), + RTD1625_GROUP(gpio_160), + RTD1625_GROUP(gpio_161), + RTD1625_GROUP(gpio_162), + RTD1625_GROUP(gpio_163), + RTD1625_GROUP(hi_width), + RTD1625_GROUP(sf_en), + RTD1625_GROUP(arm_trace_dbg_en), + RTD1625_GROUP(ejtag_aucpu0_loc), + RTD1625_GROUP(ejtag_aucpu1_loc), + RTD1625_GROUP(ejtag_ve2_loc), + RTD1625_GROUP(ejtag_scpu_loc), + RTD1625_GROUP(ejtag_pcpu_loc), + RTD1625_GROUP(ejtag_acpu_loc), + RTD1625_GROUP(i2c6_loc), + RTD1625_GROUP(uart0_loc), + RTD1625_GROUP(ai_i2s1_loc), + RTD1625_GROUP(ao_i2s1_loc), + RTD1625_GROUP(etn_phy_loc), + RTD1625_GROUP(spdif_loc), + RTD1625_GROUP(rgmii_vdsel), + RTD1625_GROUP(csi_vdsel), + RTD1625_GROUP(spdif_in_mode), +}; + +static const struct rtd_pin_group_desc rtd1625_isom_pin_groups[] = { + RTD1625_GROUP(gpio_0), + RTD1625_GROUP(gpio_1), + RTD1625_GROUP(gpio_28), + RTD1625_GROUP(gpio_29), + RTD1625_GROUP(ir_rx_loc), +}; + +static const struct rtd_pin_group_desc rtd1625_ve4_pin_groups[] = { + RTD1625_GROUP(gpio_2), + RTD1625_GROUP(gpio_3), + RTD1625_GROUP(gpio_4), + RTD1625_GROUP(gpio_5), + RTD1625_GROUP(gpio_6), + RTD1625_GROUP(gpio_7), + RTD1625_GROUP(gpio_12), + RTD1625_GROUP(gpio_13), + RTD1625_GROUP(gpio_16), + RTD1625_GROUP(gpio_17), + RTD1625_GROUP(gpio_18), + RTD1625_GROUP(gpio_19), + RTD1625_GROUP(gpio_23), + RTD1625_GROUP(gpio_24), + RTD1625_GROUP(gpio_25), + RTD1625_GROUP(gpio_30), + RTD1625_GROUP(gpio_31), + RTD1625_GROUP(gpio_32), + RTD1625_GROUP(gpio_33), + RTD1625_GROUP(gpio_34), + RTD1625_GROUP(gpio_35), + RTD1625_GROUP(gpio_42), + RTD1625_GROUP(gpio_43), + RTD1625_GROUP(gpio_44), + RTD1625_GROUP(gpio_51), + RTD1625_GROUP(gpio_53), + RTD1625_GROUP(gpio_54), + RTD1625_GROUP(gpio_55), + RTD1625_GROUP(gpio_56), + RTD1625_GROUP(gpio_57), + RTD1625_GROUP(gpio_58), + RTD1625_GROUP(gpio_59), + RTD1625_GROUP(gpio_60), + RTD1625_GROUP(gpio_61), + RTD1625_GROUP(gpio_62), + RTD1625_GROUP(gpio_63), + RTD1625_GROUP(gpio_92), + RTD1625_GROUP(gpio_93), + RTD1625_GROUP(gpio_132), + RTD1625_GROUP(gpio_133), + RTD1625_GROUP(gpio_134), + RTD1625_GROUP(gpio_135), + RTD1625_GROUP(gpio_136), + RTD1625_GROUP(gpio_137), + RTD1625_GROUP(gpio_138), + RTD1625_GROUP(gpio_139), + RTD1625_GROUP(gpio_140), + RTD1625_GROUP(gpio_141), + RTD1625_GROUP(gpio_142), + RTD1625_GROUP(gpio_143), + RTD1625_GROUP(gpio_144), + RTD1625_GROUP(gpio_164), + RTD1625_GROUP(gpio_165), + RTD1625_GROUP(ve4_uart_loc), +}; + +static const struct rtd_pin_group_desc rtd1625_main2_pin_groups[] = { + RTD1625_GROUP(gpio_14), + RTD1625_GROUP(gpio_15), + RTD1625_GROUP(gpio_20), + RTD1625_GROUP(gpio_21), + RTD1625_GROUP(gpio_22), + RTD1625_GROUP(hif_data), + RTD1625_GROUP(hif_en), + RTD1625_GROUP(hif_rdy), + RTD1625_GROUP(hif_clk), + RTD1625_GROUP(gpio_40), + RTD1625_GROUP(gpio_41), + RTD1625_GROUP(gpio_64), + RTD1625_GROUP(gpio_65), + RTD1625_GROUP(gpio_66), + RTD1625_GROUP(gpio_67), + RTD1625_GROUP(emmc_data_0), + RTD1625_GROUP(emmc_data_1), + RTD1625_GROUP(emmc_data_2), + RTD1625_GROUP(emmc_data_3), + RTD1625_GROUP(emmc_data_4), + RTD1625_GROUP(emmc_data_5), + RTD1625_GROUP(emmc_data_6), + RTD1625_GROUP(emmc_data_7), + RTD1625_GROUP(emmc_rst_n), + RTD1625_GROUP(emmc_cmd), + RTD1625_GROUP(emmc_clk), + RTD1625_GROUP(emmc_dd_sb), + RTD1625_GROUP(gpio_80), + RTD1625_GROUP(gpio_81), + RTD1625_GROUP(gpio_82), + RTD1625_GROUP(gpio_83), + RTD1625_GROUP(gpio_84), + RTD1625_GROUP(gpio_85), + RTD1625_GROUP(gpio_86), + RTD1625_GROUP(gpio_87), + RTD1625_GROUP(gpio_88), + RTD1625_GROUP(gpio_89), + RTD1625_GROUP(gpio_90), + RTD1625_GROUP(gpio_91), +}; + +static const char * const rtd1625_iso_gpio_groups[] = { + "gpio_10", "gpio_100", "gpio_101", "gpio_102", "gpio_103", "gpio_104", + "gpio_105", "gpio_106", "gpio_107", "gpio_108", "gpio_109", "gpio_11", + "gpio_110", "gpio_111", "gpio_112", "gpio_128", "gpio_129", "gpio_130", + "gpio_131", "gpio_145", "gpio_146", "gpio_147", "gpio_148", "gpio_149", + "gpio_150", "gpio_151", "gpio_152", "gpio_153", "gpio_154", "gpio_155", + "gpio_156", "gpio_157", "gpio_158", "gpio_159", "gpio_160", "gpio_161", + "gpio_162", "gpio_163", "gpio_45", "gpio_46", "gpio_47", "gpio_48", + "gpio_49", "gpio_50", "gpio_52", "gpio_8", "gpio_9", "gpio_94", "gpio_95", + "gpio_96", "gpio_97", "gpio_98", "gpio_99", "usb_cc1", "usb_cc2" +}; + +static const char * const rtd1625_iso_uart1_groups[] = { + "gpio_10", "gpio_11", "gpio_8", "gpio_9" +}; + +static const char * const rtd1625_iso_iso_tristate_groups[] = { + "gpio_10", "gpio_100", "gpio_101", "gpio_102", "gpio_103", "gpio_104", + "gpio_105", "gpio_106", "gpio_107", "gpio_108", "gpio_109", "gpio_11", + "gpio_110", "gpio_111", "gpio_112", "gpio_128", "gpio_129", "gpio_130", + "gpio_131", "gpio_145", "gpio_146", "gpio_147", "gpio_148", "gpio_149", + "gpio_150", "gpio_151", "gpio_152", "gpio_153", "gpio_154", "gpio_155", + "gpio_156", "gpio_157", "gpio_158", "gpio_159", "gpio_160", "gpio_161", + "gpio_162", "gpio_163", "gpio_45", "gpio_46", "gpio_47", "gpio_48", + "gpio_49", "gpio_50", "gpio_52", "gpio_8", "gpio_9", "gpio_94", "gpio_95", + "gpio_96", "gpio_97", "gpio_98", "gpio_99", "usb_cc1", "usb_cc2" +}; + +static const char * const rtd1625_iso_usb_cc1_groups[] = { + "usb_cc1" +}; + +static const char * const rtd1625_iso_usb_cc2_groups[] = { + "usb_cc2" +}; + +static const char * const rtd1625_iso_sdio_groups[] = { + "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49", "gpio_50" +}; + +static const char * const rtd1625_iso_scpu_ejtag_loc2_groups[] = { + "ejtag_scpu_loc", "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49" +}; + +static const char * const rtd1625_iso_acpu_ejtag_loc2_groups[] = { + "ejtag_acpu_loc", "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49" +}; + +static const char * const rtd1625_iso_pcpu_ejtag_loc2_groups[] = { + "ejtag_pcpu_loc", "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49" +}; + +static const char * const rtd1625_iso_aucpu0_ejtag_loc2_groups[] = { + "ejtag_aucpu0_loc", "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49" +}; + +static const char * const rtd1625_iso_ve2_ejtag_loc2_groups[] = { + "ejtag_ve2_loc", "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49" +}; + +static const char * const rtd1625_iso_aucpu1_ejtag_loc2_groups[] = { + "ejtag_aucpu1_loc", "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49" +}; + +static const char * const rtd1625_iso_pwm4_groups[] = { + "gpio_52" +}; + +static const char * const rtd1625_iso_uart7_groups[] = { + "gpio_94", "gpio_95" +}; + +static const char * const rtd1625_iso_pwm2_loc1_groups[] = { + "gpio_95" +}; + +static const char * const rtd1625_iso_uart8_groups[] = { + "gpio_96", "gpio_97" +}; + +static const char * const rtd1625_iso_pwm3_loc1_groups[] = { + "gpio_97" +}; + +static const char * const rtd1625_iso_ai_tdm0_groups[] = { + "gpio_100", "gpio_101", "gpio_102", "gpio_98" +}; + +static const char * const rtd1625_iso_vtc_i2s_groups[] = { + "gpio_100", "gpio_101", "gpio_102", "gpio_161", "gpio_98" +}; + +static const char * const rtd1625_iso_ai_i2s0_groups[] = { + "gpio_100", "gpio_101", "gpio_102", "gpio_156", "gpio_160", "gpio_161", + "gpio_98" +}; + +static const char * const rtd1625_iso_ao_tdm0_groups[] = { + "gpio_100", "gpio_101", "gpio_102", "gpio_99" +}; + +static const char * const rtd1625_iso_ao_i2s0_groups[] = { + "gpio_100", "gpio_101", "gpio_102", "gpio_112", "gpio_99" +}; + +static const char * const rtd1625_iso_ai_tdm1_groups[] = { + "gpio_103", "gpio_105", "gpio_106", "gpio_107" +}; + +static const char * const rtd1625_iso_ai_i2s1_loc0_groups[] = { + "ai_i2s1_loc", "gpio_103", "gpio_105", "gpio_106", "gpio_107" +}; + +static const char * const rtd1625_iso_ao_i2s0_loc1_groups[] = { + "gpio_103", "gpio_107" +}; + +static const char * const rtd1625_iso_ao_tdm1_loc0_groups[] = { + "gpio_104" +}; + +static const char * const rtd1625_iso_ao_i2s1_loc0_groups[] = { + "ao_i2s1_loc", "gpio_104", "gpio_105", "gpio_106", "gpio_107" +}; + +static const char * const rtd1625_iso_ao_tdm1_groups[] = { + "gpio_105", "gpio_106", "gpio_107" +}; + +static const char * const rtd1625_iso_ai_tdm2_groups[] = { + "gpio_108", "gpio_110", "gpio_111", "gpio_112" +}; + +static const char * const rtd1625_iso_pcm_groups[] = { + "gpio_108", "gpio_109", "gpio_110", "gpio_111" +}; + +static const char * const rtd1625_iso_ai_i2s2_groups[] = { + "gpio_108", "gpio_110", "gpio_111", "gpio_112" +}; + +static const char * const rtd1625_iso_ao_tdm2_groups[] = { + "gpio_109", "gpio_110", "gpio_111", "gpio_112" +}; + +static const char * const rtd1625_iso_ao_i2s2_groups[] = { + "gpio_109", "gpio_110", "gpio_111", "gpio_112" +}; + +static const char * const rtd1625_iso_vtc_ao_i2s_groups[] = { + "gpio_109", "gpio_110", "gpio_111", "gpio_112" +}; + +static const char * const rtd1625_iso_scpu_ejtag_loc0_groups[] = { + "ejtag_scpu_loc", "gpio_112" +}; + +static const char * const rtd1625_iso_acpu_ejtag_loc0_groups[] = { + "ejtag_acpu_loc", "gpio_112" +}; + +static const char * const rtd1625_iso_pcpu_ejtag_loc0_groups[] = { + "ejtag_pcpu_loc", "gpio_112" +}; + +static const char * const rtd1625_iso_aucpu0_ejtag_loc0_groups[] = { + "ejtag_aucpu0_loc", "gpio_112" +}; + +static const char * const rtd1625_iso_ve2_ejtag_loc0_groups[] = { + "ejtag_ve2_loc", "gpio_112" +}; + +static const char * const rtd1625_iso_gpu_ejtag_loc0_groups[] = { + "gpio_112" +}; + +static const char * const rtd1625_iso_ao_tdm1_loc1_groups[] = { + "gpio_112" +}; + +static const char * const rtd1625_iso_aucpu1_ejtag_loc0_groups[] = { + "ejtag_aucpu1_loc", "gpio_112" +}; + +static const char * const rtd1625_iso_edptx_hdp_groups[] = { + "gpio_128" +}; + +static const char * const rtd1625_iso_pwm5_groups[] = { + "gpio_130" +}; + +static const char * const rtd1625_iso_vi0_dtv_groups[] = { + "gpio_145", "gpio_146", "gpio_147", "gpio_148", "gpio_149", "gpio_150", + "gpio_151", "gpio_152", "gpio_153", "gpio_154", "gpio_155", "gpio_156", + "gpio_157", "gpio_158", "gpio_159", "gpio_160", "gpio_161" +}; + +static const char * const rtd1625_iso_vi1_dtv_groups[] = { + "gpio_154", "gpio_155", "gpio_156", "gpio_157", "gpio_158", "gpio_159", + "gpio_160", "gpio_161", "gpio_162" +}; + +static const char * const rtd1625_iso_ao_i2s0_loc0_groups[] = { + "gpio_154", "gpio_155" +}; + +static const char * const rtd1625_iso_dmic0_groups[] = { + "gpio_156", "gpio_157" +}; + +static const char * const rtd1625_iso_vtc_dmic_groups[] = { + "gpio_156", "gpio_157", "gpio_158", "gpio_159" +}; + +static const char * const rtd1625_iso_ai_i2s1_loc1_groups[] = { + "ai_i2s1_loc", "gpio_157", "gpio_158", "gpio_159", "gpio_160" +}; + +static const char * const rtd1625_iso_ao_i2s1_loc1_groups[] = { + "ao_i2s1_loc", "gpio_157", "gpio_158", "gpio_159", "gpio_161" +}; + +static const char * const rtd1625_iso_dmic1_groups[] = { + "gpio_158", "gpio_159" +}; + +static const char * const rtd1625_iso_dmic2_groups[] = { + "gpio_160", "gpio_161" +}; + +static const char * const rtd1625_iso_pwm0_loc2_groups[] = { + "gpio_162" +}; + +static const char * const rtd1625_iso_spdif_in_coaxial_groups[] = { + "gpio_163", "spdif_sel", "spdif_in_mode" +}; + +static const char * const rtd1625_iso_spdif_in_gpio_groups[] = { + "spdif_in_mode" +}; + +static const char * const rtd1625_iso_hi_width_disable_groups[] = { + "hi_width" +}; + +static const char * const rtd1625_iso_hi_width_1bit_groups[] = { + "hi_width" +}; + +static const char * const rtd1625_iso_sf_disable_groups[] = { + "sf_en" +}; + +static const char * const rtd1625_iso_sf_enable_groups[] = { + "sf_en" +}; + +static const char * const rtd1625_iso_arm_trace_debug_disable_groups[] = { + "arm_trace_dbg_en" +}; + +static const char * const rtd1625_iso_arm_trace_debug_enable_groups[] = { + "arm_trace_dbg_en" +}; + +static const char * const rtd1625_iso_aucpu0_ejtag_loc1_groups[] = { + "ejtag_aucpu0_loc" +}; + +static const char * const rtd1625_iso_aucpu1_ejtag_loc1_groups[] = { + "ejtag_aucpu1_loc" +}; + +static const char * const rtd1625_iso_ve2_ejtag_loc1_groups[] = { + "ejtag_ve2_loc" +}; + +static const char * const rtd1625_iso_scpu_ejtag_loc1_groups[] = { + "ejtag_scpu_loc" +}; + +static const char * const rtd1625_iso_pcpu_ejtag_loc1_groups[] = { + "ejtag_pcpu_loc" +}; + +static const char * const rtd1625_iso_acpu_ejtag_loc1_groups[] = { + "ejtag_acpu_loc" +}; + +static const char * const rtd1625_iso_i2c6_loc0_groups[] = { + "i2c6_loc" +}; + +static const char * const rtd1625_iso_i2c6_loc1_groups[] = { + "i2c6_loc" +}; + +static const char * const rtd1625_iso_uart0_loc0_groups[] = { + "uart0_loc" +}; + +static const char * const rtd1625_iso_uart0_loc1_groups[] = { + "uart0_loc" +}; + +static const char * const rtd1625_iso_etn_phy_loc0_groups[] = { + "etn_phy_loc" +}; + +static const char * const rtd1625_iso_etn_phy_loc1_groups[] = { + "etn_phy_loc" +}; + +static const char * const rtd1625_iso_spdif_loc0_groups[] = { + "spdif_loc" +}; + +static const char * const rtd1625_iso_spdif_loc1_groups[] = { + "spdif_loc" +}; + +static const char * const rtd1625_iso_rgmii_1v2_groups[] = { + "rgmii_vdsel" +}; + +static const char * const rtd1625_iso_rgmii_1v8_groups[] = { + "rgmii_vdsel" +}; + +static const char * const rtd1625_iso_rgmii_2v5_groups[] = { + "rgmii_vdsel" +}; + +static const char * const rtd1625_iso_rgmii_3v3_groups[] = { + "rgmii_vdsel" +}; + +static const char * const rtd1625_iso_csi_1v2_groups[] = { + "csi_vdsel" +}; + +static const char * const rtd1625_iso_csi_1v8_groups[] = { + "csi_vdsel" +}; + +static const char * const rtd1625_iso_csi_2v5_groups[] = { + "csi_vdsel" +}; + +static const char * const rtd1625_iso_csi_3v3_groups[] = { + "csi_vdsel" +}; + +static const char * const rtd1625_isom_gpio_groups[] = { + "gpio_0", "gpio_1", "gpio_28", "gpio_29" +}; + +static const char * const rtd1625_isom_pctrl_groups[] = { + "gpio_0", "gpio_1", "gpio_28", "gpio_29" +}; + +static const char * const rtd1625_isom_iso_tristate_groups[] = { + "gpio_0", "gpio_1", "gpio_28", "gpio_29" +}; + +static const char * const rtd1625_isom_ir_rx_loc1_groups[] = { + "gpio_1", "ir_rx_loc" +}; + +static const char * const rtd1625_isom_uart10_groups[] = { + "gpio_28", "gpio_29" +}; + +static const char * const rtd1625_isom_isom_dbg_out_groups[] = { + "gpio_28", "gpio_29" +}; + +static const char * const rtd1625_isom_ir_rx_loc0_groups[] = { + "gpio_29", "ir_rx_loc" +}; + +static const char * const rtd1625_ve4_gpio_groups[] = { + "gpio_12", "gpio_13", "gpio_132", "gpio_133", "gpio_134", "gpio_135", + "gpio_136", "gpio_137", "gpio_138", "gpio_139", "gpio_140", "gpio_141", + "gpio_142", "gpio_143", "gpio_144", "gpio_16", "gpio_164", "gpio_165", + "gpio_17", "gpio_18", "gpio_19", "gpio_2", "gpio_23", "gpio_24", "gpio_25", + "gpio_3", "gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34", "gpio_35", + "gpio_4", "gpio_42", "gpio_43", "gpio_44", "gpio_5", "gpio_51", "gpio_53", + "gpio_54", "gpio_55", "gpio_56", "gpio_57", "gpio_58", "gpio_59", "gpio_6", + "gpio_60", "gpio_61", "gpio_62", "gpio_63", "gpio_7", "gpio_92", "gpio_93" +}; + +static const char * const rtd1625_ve4_uart0_loc0_groups[] = { + "gpio_2", "gpio_3" +}; + +static const char * const rtd1625_ve4_iso_tristate_groups[] = { + "gpio_12", "gpio_13", "gpio_132", "gpio_133", "gpio_134", "gpio_135", + "gpio_136", "gpio_137", "gpio_138", "gpio_139", "gpio_140", "gpio_141", + "gpio_142", "gpio_143", "gpio_144", "gpio_16", "gpio_164", "gpio_165", + "gpio_17", "gpio_18", "gpio_19", "gpio_2", "gpio_23", "gpio_24", "gpio_25", + "gpio_3", "gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34", "gpio_35", + "gpio_4", "gpio_42", "gpio_43", "gpio_44", "gpio_5", "gpio_51", "gpio_53", + "gpio_54", "gpio_55", "gpio_56", "gpio_57", "gpio_58", "gpio_59", "gpio_6", + "gpio_60", "gpio_61", "gpio_62", "gpio_63", "gpio_7", "gpio_92", "gpio_93" +}; + +static const char * const rtd1625_ve4_uart2_groups[] = { + "gpio_4", "gpio_5", "gpio_6", "gpio_7" +}; + +static const char * const rtd1625_ve4_gspi0_groups[] = { + "gpio_4", "gpio_5", "gpio_6", "gpio_7" +}; + +static const char * const rtd1625_ve4_scpu_ejtag_loc0_groups[] = { + "gpio_4", "gpio_5", "gpio_6", "gpio_7" +}; + +static const char * const rtd1625_ve4_acpu_ejtag_loc0_groups[] = { + "gpio_4", "gpio_5", "gpio_6", "gpio_7" +}; + +static const char * const rtd1625_ve4_pcpu_ejtag_loc0_groups[] = { + "gpio_4", "gpio_5", "gpio_6", "gpio_7" +}; + +static const char * const rtd1625_ve4_aucpu0_ejtag_loc0_groups[] = { + "gpio_4", "gpio_5", "gpio_6", "gpio_7" +}; + +static const char * const rtd1625_ve4_ve2_ejtag_loc0_groups[] = { + "gpio_4", "gpio_5", "gpio_6", "gpio_7" +}; + +static const char * const rtd1625_ve4_gpu_ejtag_loc0_groups[] = { + "gpio_4", "gpio_5", "gpio_6", "gpio_7" +}; + +static const char * const rtd1625_ve4_aucpu1_ejtag_loc0_groups[] = { + "gpio_4", "gpio_5", "gpio_6", "gpio_7" +}; + +static const char * const rtd1625_ve4_pwm0_loc1_groups[] = { + "gpio_6" +}; + +static const char * const rtd1625_ve4_pwm1_loc0_groups[] = { + "gpio_7" +}; + +static const char * const rtd1625_ve4_i2c0_groups[] = { + "gpio_12", "gpio_13" +}; + +static const char * const rtd1625_ve4_pwm0_loc3_groups[] = { + "gpio_12" +}; + +static const char * const rtd1625_ve4_dptx_hpd_groups[] = { + "gpio_16" +}; + +static const char * const rtd1625_ve4_pwm2_loc0_groups[] = { + "gpio_16" +}; + +static const char * const rtd1625_ve4_pcie0_groups[] = { + "gpio_18" +}; + +static const char * const rtd1625_ve4_pwm3_loc0_groups[] = { + "gpio_19" +}; + +static const char * const rtd1625_ve4_i2c3_groups[] = { + "gpio_24", "gpio_25" +}; + +static const char * const rtd1625_ve4_pcie1_groups[] = { + "gpio_30" +}; + +static const char * const rtd1625_ve4_uart9_groups[] = { + "gpio_32", "gpio_33" +}; + +static const char * const rtd1625_ve4_ve4_uart_loc2_groups[] = { + "gpio_32", "gpio_33", "ve4_uart_loc" +}; + +static const char * const rtd1625_ve4_sd_groups[] = { + "gpio_42", "gpio_43" +}; + +static const char * const rtd1625_ve4_i2c6_loc1_groups[] = { + "gpio_51", "gpio_61" +}; + +static const char * const rtd1625_ve4_uart3_groups[] = { + "gpio_53", "gpio_54", "gpio_55", "gpio_56" +}; + +static const char * const rtd1625_ve4_ts0_groups[] = { + "gpio_53", "gpio_54", "gpio_55", "gpio_56" +}; + +static const char * const rtd1625_ve4_gspi2_groups[] = { + "gpio_53", "gpio_54", "gpio_55", "gpio_56" +}; + +static const char * const rtd1625_ve4_ve4_uart_loc0_groups[] = { + "gpio_53", "gpio_54", "ve4_uart_loc" +}; + +static const char * const rtd1625_ve4_uart5_groups[] = { + "gpio_57", "gpio_58" +}; + +static const char * const rtd1625_ve4_uart0_loc1_groups[] = { + "gpio_57", "gpio_58" +}; + +static const char * const rtd1625_ve4_gspi1_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60" +}; + +static const char * const rtd1625_ve4_uart4_groups[] = { + "gpio_59", "gpio_60" +}; + +static const char * const rtd1625_ve4_i2c4_groups[] = { + "gpio_59", "gpio_60" +}; + +static const char * const rtd1625_ve4_spdif_out_groups[] = { + "gpio_61" +}; + +static const char * const rtd1625_ve4_spdif_in_optical_groups[] = { + "gpio_61" +}; + +static const char * const rtd1625_ve4_pll_test_loc0_groups[] = { + "gpio_62", "gpio_63" +}; + +static const char * const rtd1625_ve4_uart6_groups[] = { + "gpio_92", "gpio_93" +}; + +static const char * const rtd1625_ve4_i2c7_groups[] = { + "gpio_92", "gpio_93" +}; + +static const char * const rtd1625_ve4_ve4_uart_loc1_groups[] = { + "gpio_92", "gpio_93", "ve4_uart_loc" +}; + +static const char * const rtd1625_ve4_pwm1_loc1_groups[] = { + "gpio_93" +}; + +static const char * const rtd1625_ve4_pwm6_groups[] = { + "gpio_132" +}; + +static const char * const rtd1625_ve4_ts1_groups[] = { + "gpio_133", "gpio_134", "gpio_135", "gpio_136" +}; + +static const char * const rtd1625_ve4_pwm0_loc0_groups[] = { + "gpio_136" +}; + +static const char * const rtd1625_ve4_i2c6_loc0_groups[] = { + "gpio_137", "gpio_138" +}; + +static const char * const rtd1625_ve4_csi0_groups[] = { + "gpio_141" +}; + +static const char * const rtd1625_ve4_csi1_groups[] = { + "gpio_144" +}; + +static const char * const rtd1625_ve4_etn_led_loc1_groups[] = { + "gpio_164", "gpio_165" +}; + +static const char * const rtd1625_ve4_etn_phy_loc1_groups[] = { + "gpio_164", "gpio_165" +}; + +static const char * const rtd1625_ve4_i2c5_groups[] = { + "gpio_164", "gpio_165" +}; + +static const char * const rtd1625_main2_gpio_groups[] = { + "emmc_clk", "emmc_cmd", "emmc_data_0", "emmc_data_1", "emmc_data_2", + "emmc_data_3", "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7", + "emmc_dd_sb", "emmc_rst_n", "gpio_14", "gpio_15", "gpio_20", "gpio_21", + "gpio_22", "gpio_40", "gpio_41", "gpio_64", "gpio_65", "gpio_66", "gpio_67", + "gpio_80", "gpio_81", "gpio_82", "gpio_83", "gpio_84", "gpio_85", "gpio_86", + "gpio_87", "gpio_88", "gpio_89", "gpio_90", "gpio_91", "hif_clk", + "hif_data", "hif_en", "hif_rdy" +}; + +static const char * const rtd1625_main2_emmc_groups[] = { + "emmc_clk", "emmc_cmd", "emmc_data_0", "emmc_data_1", "emmc_data_2", + "emmc_data_3", "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7", + "emmc_dd_sb", "emmc_rst_n" +}; + +static const char * const rtd1625_main2_iso_tristate_groups[] = { + "emmc_clk", "emmc_cmd", "emmc_data_0", "emmc_data_1", "emmc_data_2", + "emmc_data_3", "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7", + "emmc_dd_sb", "emmc_rst_n", "gpio_14", "gpio_15", "gpio_20", "gpio_21", + "gpio_40", "gpio_41", "gpio_64", "gpio_65", "gpio_66", "gpio_67", "gpio_80", + "gpio_81", "gpio_82", "gpio_83", "gpio_84", "gpio_85", "gpio_86", "gpio_87", + "gpio_88", "gpio_89", "gpio_90", "gpio_91", "hif_clk", "hif_data", "hif_en", + "hif_rdy" +}; + +static const char * const rtd1625_main2_nf_groups[] = { + "emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3", "emmc_data_4", + "emmc_data_5" +}; + +static const char * const rtd1625_main2_etn_led_loc0_groups[] = { + "gpio_14", "gpio_15" +}; + +static const char * const rtd1625_main2_etn_phy_loc0_groups[] = { + "gpio_14", "gpio_15" +}; + +static const char * const rtd1625_main2_rgmii_groups[] = { + "gpio_14", "gpio_15", "gpio_80", "gpio_81", "gpio_82", "gpio_83", "gpio_84", + "gpio_85", "gpio_86", "gpio_87", "gpio_88", "gpio_89", "gpio_90", "gpio_91" +}; + +static const char * const rtd1625_main2_i2c1_groups[] = { + "gpio_20", "gpio_21" +}; + +static const char * const rtd1625_main2_dbg_out1_groups[] = { + "gpio_22" +}; + +static const char * const rtd1625_main2_sd_groups[] = { + "gpio_40", "gpio_41", "hif_clk", "hif_data", "hif_en", "hif_rdy" +}; + +static const char * const rtd1625_main2_scpu_ejtag_loc1_groups[] = { + "gpio_40", "hif_clk", "hif_data", "hif_en", "hif_rdy" +}; + +static const char * const rtd1625_main2_acpu_ejtag_loc1_groups[] = { + "gpio_40", "hif_clk", "hif_data", "hif_en", "hif_rdy" +}; + +static const char * const rtd1625_main2_pcpu_ejtag_loc1_groups[] = { + "gpio_40", "hif_clk", "hif_data", "hif_en", "hif_rdy" +}; + +static const char * const rtd1625_main2_aupu0_ejtag_loc1_groups[] = { + "gpio_40", "hif_clk", "hif_data", "hif_en", "hif_rdy" +}; + +static const char * const rtd1625_main2_ve2_ejtag_loc1_groups[] = { + "gpio_40", "hif_clk", "hif_data", "hif_en", "hif_rdy" +}; + +static const char * const rtd1625_main2_hi_loc0_groups[] = { + "hif_clk", "hif_data", "hif_en", "hif_rdy" +}; + +static const char * const rtd1625_main2_hi_m_groups[] = { + "hif_clk", "hif_data", "hif_en", "hif_rdy" +}; + +static const char * const rtd1625_main2_aupu1_ejtag_loc1_groups[] = { + "gpio_40", "hif_clk", "hif_data", "hif_en", "hif_rdy" +}; + +static const char * const rtd1625_main2_spi_groups[] = { + "gpio_64", "gpio_65", "gpio_66", "gpio_67" +}; + +static const char * const rtd1625_main2_pll_test_loc1_groups[] = { + "gpio_65", "gpio_66" +}; + +static const char * const rtd1625_main2_rmii_groups[] = { + "gpio_80", "gpio_81", "gpio_82", "gpio_83", "gpio_84", "gpio_87", "gpio_88", + "gpio_89" +}; + +#define RTD1625_FUNC(_group, _name) \ + { \ + .name = # _name, \ + .groups = rtd1625_ ## _group ## _ ## _name ## _groups, \ + .num_groups = ARRAY_SIZE(rtd1625_ ## _group ## _ ## _name ## _groups), \ + } + +static const struct rtd_pin_func_desc rtd1625_iso_pin_functions[] = { + RTD1625_FUNC(iso, gpio), + RTD1625_FUNC(iso, uart1), + RTD1625_FUNC(iso, iso_tristate), + RTD1625_FUNC(iso, usb_cc1), + RTD1625_FUNC(iso, usb_cc2), + RTD1625_FUNC(iso, sdio), + RTD1625_FUNC(iso, scpu_ejtag_loc2), + RTD1625_FUNC(iso, acpu_ejtag_loc2), + RTD1625_FUNC(iso, pcpu_ejtag_loc2), + RTD1625_FUNC(iso, aucpu0_ejtag_loc2), + RTD1625_FUNC(iso, ve2_ejtag_loc2), + RTD1625_FUNC(iso, aucpu1_ejtag_loc2), + RTD1625_FUNC(iso, pwm4), + RTD1625_FUNC(iso, uart7), + RTD1625_FUNC(iso, pwm2_loc1), + RTD1625_FUNC(iso, uart8), + RTD1625_FUNC(iso, pwm3_loc1), + RTD1625_FUNC(iso, ai_tdm0), + RTD1625_FUNC(iso, vtc_i2s), + RTD1625_FUNC(iso, ai_i2s0), + RTD1625_FUNC(iso, ao_tdm0), + RTD1625_FUNC(iso, ao_i2s0), + RTD1625_FUNC(iso, ai_tdm1), + RTD1625_FUNC(iso, ai_i2s1_loc0), + RTD1625_FUNC(iso, ao_i2s0_loc1), + RTD1625_FUNC(iso, ao_tdm1_loc0), + RTD1625_FUNC(iso, ao_i2s1_loc0), + RTD1625_FUNC(iso, ao_tdm1), + RTD1625_FUNC(iso, ai_tdm2), + RTD1625_FUNC(iso, pcm), + RTD1625_FUNC(iso, ai_i2s2), + RTD1625_FUNC(iso, ao_tdm2), + RTD1625_FUNC(iso, ao_i2s2), + RTD1625_FUNC(iso, vtc_ao_i2s), + RTD1625_FUNC(iso, scpu_ejtag_loc0), + RTD1625_FUNC(iso, acpu_ejtag_loc0), + RTD1625_FUNC(iso, pcpu_ejtag_loc0), + RTD1625_FUNC(iso, aucpu0_ejtag_loc0), + RTD1625_FUNC(iso, ve2_ejtag_loc0), + RTD1625_FUNC(iso, gpu_ejtag_loc0), + RTD1625_FUNC(iso, ao_tdm1_loc1), + RTD1625_FUNC(iso, aucpu1_ejtag_loc0), + RTD1625_FUNC(iso, edptx_hdp), + RTD1625_FUNC(iso, pwm5), + RTD1625_FUNC(iso, vi0_dtv), + RTD1625_FUNC(iso, vi1_dtv), + RTD1625_FUNC(iso, ao_i2s0_loc0), + RTD1625_FUNC(iso, dmic0), + RTD1625_FUNC(iso, vtc_dmic), + RTD1625_FUNC(iso, ai_i2s1_loc1), + RTD1625_FUNC(iso, ao_i2s1_loc1), + RTD1625_FUNC(iso, dmic1), + RTD1625_FUNC(iso, dmic2), + RTD1625_FUNC(iso, pwm0_loc2), + RTD1625_FUNC(iso, spdif_in_coaxial), + RTD1625_FUNC(iso, spdif_in_gpio), + RTD1625_FUNC(iso, hi_width_disable), + RTD1625_FUNC(iso, hi_width_1bit), + RTD1625_FUNC(iso, sf_disable), + RTD1625_FUNC(iso, sf_enable), + RTD1625_FUNC(iso, arm_trace_debug_disable), + RTD1625_FUNC(iso, arm_trace_debug_enable), + RTD1625_FUNC(iso, aucpu0_ejtag_loc1), + RTD1625_FUNC(iso, aucpu1_ejtag_loc1), + RTD1625_FUNC(iso, ve2_ejtag_loc1), + RTD1625_FUNC(iso, scpu_ejtag_loc1), + RTD1625_FUNC(iso, pcpu_ejtag_loc1), + RTD1625_FUNC(iso, acpu_ejtag_loc1), + RTD1625_FUNC(iso, i2c6_loc0), + RTD1625_FUNC(iso, i2c6_loc1), + RTD1625_FUNC(iso, uart0_loc0), + RTD1625_FUNC(iso, uart0_loc1), + RTD1625_FUNC(iso, etn_phy_loc0), + RTD1625_FUNC(iso, etn_phy_loc1), + RTD1625_FUNC(iso, spdif_loc0), + RTD1625_FUNC(iso, spdif_loc1), + RTD1625_FUNC(iso, rgmii_1v2), + RTD1625_FUNC(iso, rgmii_1v8), + RTD1625_FUNC(iso, rgmii_2v5), + RTD1625_FUNC(iso, rgmii_3v3), + RTD1625_FUNC(iso, csi_1v2), + RTD1625_FUNC(iso, csi_1v8), + RTD1625_FUNC(iso, csi_2v5), + RTD1625_FUNC(iso, csi_3v3), +}; + +static const struct rtd_pin_func_desc rtd1625_isom_pin_functions[] = { + RTD1625_FUNC(isom, gpio), + RTD1625_FUNC(isom, pctrl), + RTD1625_FUNC(isom, iso_tristate), + RTD1625_FUNC(isom, ir_rx_loc1), + RTD1625_FUNC(isom, uart10), + RTD1625_FUNC(isom, isom_dbg_out), + RTD1625_FUNC(isom, ir_rx_loc0), +}; + +static const struct rtd_pin_func_desc rtd1625_ve4_pin_functions[] = { + RTD1625_FUNC(ve4, gpio), + RTD1625_FUNC(ve4, uart0_loc0), + RTD1625_FUNC(ve4, iso_tristate), + RTD1625_FUNC(ve4, uart2), + RTD1625_FUNC(ve4, gspi0), + RTD1625_FUNC(ve4, scpu_ejtag_loc0), + RTD1625_FUNC(ve4, acpu_ejtag_loc0), + RTD1625_FUNC(ve4, pcpu_ejtag_loc0), + RTD1625_FUNC(ve4, aucpu0_ejtag_loc0), + RTD1625_FUNC(ve4, ve2_ejtag_loc0), + RTD1625_FUNC(ve4, gpu_ejtag_loc0), + RTD1625_FUNC(ve4, aucpu1_ejtag_loc0), + RTD1625_FUNC(ve4, pwm0_loc1), + RTD1625_FUNC(ve4, pwm1_loc0), + RTD1625_FUNC(ve4, i2c0), + RTD1625_FUNC(ve4, pwm0_loc3), + RTD1625_FUNC(ve4, dptx_hpd), + RTD1625_FUNC(ve4, pwm2_loc0), + RTD1625_FUNC(ve4, pcie0), + RTD1625_FUNC(ve4, pwm3_loc0), + RTD1625_FUNC(ve4, i2c3), + RTD1625_FUNC(ve4, pcie1), + RTD1625_FUNC(ve4, uart9), + RTD1625_FUNC(ve4, ve4_uart_loc2), + RTD1625_FUNC(ve4, sd), + RTD1625_FUNC(ve4, i2c6_loc1), + RTD1625_FUNC(ve4, uart3), + RTD1625_FUNC(ve4, ts0), + RTD1625_FUNC(ve4, gspi2), + RTD1625_FUNC(ve4, ve4_uart_loc0), + RTD1625_FUNC(ve4, uart5), + RTD1625_FUNC(ve4, uart0_loc1), + RTD1625_FUNC(ve4, gspi1), + RTD1625_FUNC(ve4, uart4), + RTD1625_FUNC(ve4, i2c4), + RTD1625_FUNC(ve4, spdif_out), + RTD1625_FUNC(ve4, spdif_in_optical), + RTD1625_FUNC(ve4, pll_test_loc0), + RTD1625_FUNC(ve4, uart6), + RTD1625_FUNC(ve4, i2c7), + RTD1625_FUNC(ve4, ve4_uart_loc1), + RTD1625_FUNC(ve4, pwm1_loc1), + RTD1625_FUNC(ve4, pwm6), + RTD1625_FUNC(ve4, ts1), + RTD1625_FUNC(ve4, pwm0_loc0), + RTD1625_FUNC(ve4, i2c6_loc0), + RTD1625_FUNC(ve4, csi0), + RTD1625_FUNC(ve4, csi1), + RTD1625_FUNC(ve4, etn_led_loc1), + RTD1625_FUNC(ve4, etn_phy_loc1), + RTD1625_FUNC(ve4, i2c5), +}; + +static const struct rtd_pin_func_desc rtd1625_main2_pin_functions[] = { + RTD1625_FUNC(main2, gpio), + RTD1625_FUNC(main2, emmc), + RTD1625_FUNC(main2, iso_tristate), + RTD1625_FUNC(main2, nf), + RTD1625_FUNC(main2, etn_led_loc0), + RTD1625_FUNC(main2, etn_phy_loc0), + RTD1625_FUNC(main2, rgmii), + RTD1625_FUNC(main2, i2c1), + RTD1625_FUNC(main2, dbg_out1), + RTD1625_FUNC(main2, sd), + RTD1625_FUNC(main2, scpu_ejtag_loc1), + RTD1625_FUNC(main2, acpu_ejtag_loc1), + RTD1625_FUNC(main2, pcpu_ejtag_loc1), + RTD1625_FUNC(main2, aupu0_ejtag_loc1), + RTD1625_FUNC(main2, ve2_ejtag_loc1), + RTD1625_FUNC(main2, hi_loc0), + RTD1625_FUNC(main2, hi_m), + RTD1625_FUNC(main2, aupu1_ejtag_loc1), + RTD1625_FUNC(main2, spi), + RTD1625_FUNC(main2, pll_test_loc1), + RTD1625_FUNC(main2, rmii), +}; + +#undef RTD1625_FUNC + +static const struct rtd_pin_desc rtd1625_iso_muxes[] = { + [RTD1625_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0x0, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + [RTD1625_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0x0, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0x0, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0x0, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x0, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "usb_cc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate") + ), + [RTD1625_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0x0, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "usb_cc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate") + ), + [RTD1625_ISO_GPIO_45] = RTK_PIN_MUX(gpio_45, 0x0, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "sdio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "pcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "aucpu0_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "ve2_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 24), "aucpu1_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate") + ), + [RTD1625_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x0, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "sdio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "pcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 28), "aucpu0_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 28), "ve2_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 28), "aucpu1_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate") + ), + + [RTD1625_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x4, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "sdio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "pcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "aucpu0_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "ve2_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 0), "aucpu1_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + [RTD1625_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x4, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sdio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "pcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "aucpu0_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "ve2_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "aucpu1_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x4, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sdio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "pcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "aucpu0_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "ve2_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 8), "aucpu1_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x4, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "sdio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_ISO_GPIO_52] = RTK_PIN_MUX(gpio_52, 0x4, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "pwm4"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate") + ), + [RTD1625_ISO_GPIO_94] = RTK_PIN_MUX(gpio_94, 0x4, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "uart7"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate") + ), + [RTD1625_ISO_GPIO_95] = RTK_PIN_MUX(gpio_95, 0x4, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "uart7"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 24), "pwm2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate") + ), + [RTD1625_ISO_GPIO_96] = RTK_PIN_MUX(gpio_96, 0x4, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart8"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate") + ), + + [RTD1625_ISO_GPIO_97] = RTK_PIN_MUX(gpio_97, 0x8, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart8"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 0), "pwm3_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + [RTD1625_ISO_GPIO_98] = RTK_PIN_MUX(gpio_98, 0x8, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "ai_tdm0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "vtc_i2s"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "ai_i2s0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_ISO_GPIO_99] = RTK_PIN_MUX(gpio_99, 0x8, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ao_tdm0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 8), "ao_i2s0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_ISO_GPIO_100] = RTK_PIN_MUX(gpio_100, 0x8, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "ai_tdm0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "ao_tdm0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "vtc_i2s"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "ai_i2s0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 12), "ao_i2s0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_ISO_GPIO_101] = RTK_PIN_MUX(gpio_101, 0x8, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "ai_tdm0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "ao_tdm0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "vtc_i2s"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "ai_i2s0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "ao_i2s0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate") + ), + [RTD1625_ISO_GPIO_102] = RTK_PIN_MUX(gpio_102, 0x8, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "ai_tdm0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "ao_tdm0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "vtc_i2s"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ai_i2s0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 20), "ao_i2s0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate") + ), + [RTD1625_ISO_GPIO_103] = RTK_PIN_MUX(gpio_103, 0x8, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "ai_tdm1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 24), "ai_i2s1_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 24), "ao_i2s0_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate") + ), + [RTD1625_ISO_GPIO_104] = RTK_PIN_MUX(gpio_104, 0x8, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "ao_tdm1_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 28), "ao_i2s1_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate") + ), + + [RTD1625_ISO_GPIO_105] = RTK_PIN_MUX(gpio_105, 0xc, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "ai_tdm1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ao_tdm1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "ai_i2s1_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 0), "ao_i2s1_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + [RTD1625_ISO_GPIO_106] = RTK_PIN_MUX(gpio_106, 0xc, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "ai_tdm1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "ao_tdm1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "ai_i2s1_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 4), "ao_i2s1_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_ISO_GPIO_107] = RTK_PIN_MUX(gpio_107, 0xc, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "ai_tdm1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ao_tdm1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "ai_i2s1_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 8), "ao_i2s1_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "ao_i2s0_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_ISO_GPIO_108] = RTK_PIN_MUX(gpio_108, 0xc, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "ai_tdm2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "pcm"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "ai_i2s2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_ISO_GPIO_109] = RTK_PIN_MUX(gpio_109, 0xc, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "ao_tdm2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "pcm"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "ao_i2s2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 16), "vtc_ao_i2s"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate") + ), + [RTD1625_ISO_GPIO_110] = RTK_PIN_MUX(gpio_110, 0xc, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "ai_tdm2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "ao_tdm2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "pcm"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 20), "ai_i2s2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 20), "ao_i2s2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 20), "vtc_ao_i2s"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate") + ), + [RTD1625_ISO_GPIO_111] = RTK_PIN_MUX(gpio_111, 0xc, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "ai_tdm2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "ao_tdm2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "pcm"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 24), "ai_i2s2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 24), "ao_i2s2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 24), "vtc_ao_i2s"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate") + ), + + [RTD1625_ISO_GPIO_112] = RTK_PIN_MUX(gpio_112, 0x10, GENMASK(4, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "ai_tdm2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ao_tdm2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "pcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "aucpu0_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "ve2_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "ai_i2s2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 0), "ao_i2s2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 0), "gpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 0), "vtc_ao_i2s"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 0), "ao_tdm1_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 0), "aucpu1_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x13, 0), "ao_i2s0") + ), + [RTD1625_ISO_GPIO_128] = RTK_PIN_MUX(gpio_128, 0x10, GENMASK(8, 5), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 5), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 5), "edptx_hdp"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 5), "iso_tristate") + ), + [RTD1625_ISO_GPIO_129] = RTK_PIN_MUX(gpio_129, 0x10, GENMASK(12, 9), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 9), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 9), "iso_tristate") + ), + [RTD1625_ISO_GPIO_130] = RTK_PIN_MUX(gpio_130, 0x10, GENMASK(16, 13), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 13), "pwm5"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 13), "iso_tristate") + ), + [RTD1625_ISO_GPIO_131] = RTK_PIN_MUX(gpio_131, 0x10, GENMASK(20, 17), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 17), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 17), "iso_tristate") + ), + [RTD1625_ISO_GPIO_145] = RTK_PIN_MUX(gpio_145, 0x10, GENMASK(24, 21), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 21), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 21), "vi0_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 21), "iso_tristate") + ), + [RTD1625_ISO_GPIO_146] = RTK_PIN_MUX(gpio_146, 0x10, GENMASK(28, 25), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 25), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 25), "vi0_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 25), "iso_tristate") + ), + + [RTD1625_ISO_GPIO_147] = RTK_PIN_MUX(gpio_147, 0x14, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "vi0_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + [RTD1625_ISO_GPIO_148] = RTK_PIN_MUX(gpio_148, 0x14, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "vi0_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_ISO_GPIO_149] = RTK_PIN_MUX(gpio_149, 0x14, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "vi0_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_ISO_GPIO_150] = RTK_PIN_MUX(gpio_150, 0x14, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "vi0_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_ISO_GPIO_151] = RTK_PIN_MUX(gpio_151, 0x14, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "vi0_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate") + ), + [RTD1625_ISO_GPIO_152] = RTK_PIN_MUX(gpio_152, 0x14, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vi0_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate") + ), + [RTD1625_ISO_GPIO_153] = RTK_PIN_MUX(gpio_153, 0x14, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "vi0_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate") + ), + [RTD1625_ISO_GPIO_154] = RTK_PIN_MUX(gpio_154, 0x14, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "vi0_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "vi1_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 28), "ao_i2s0_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate") + ), + + [RTD1625_ISO_GPIO_155] = RTK_PIN_MUX(gpio_155, 0x18, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "vi0_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "vi1_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 0), "ao_i2s0_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + [RTD1625_ISO_GPIO_156] = RTK_PIN_MUX(gpio_156, 0x18, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "vi0_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "vi1_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "vtc_dmic"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "ai_i2s0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_ISO_GPIO_157] = RTK_PIN_MUX(gpio_157, 0x18, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "vi0_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "vi1_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "vtc_dmic"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "ai_i2s1_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 8), "ao_i2s1_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_ISO_GPIO_158] = RTK_PIN_MUX(gpio_158, 0x18, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "vi0_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "vi1_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "vtc_dmic"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "ai_i2s1_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 12), "ao_i2s1_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_ISO_GPIO_159] = RTK_PIN_MUX(gpio_159, 0x18, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "vi0_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "vi1_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "dmic1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "vtc_dmic"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "ai_i2s1_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "ao_i2s1_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate") + ), + [RTD1625_ISO_GPIO_160] = RTK_PIN_MUX(gpio_160, 0x18, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vi0_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "vi1_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ai_i2s0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 20), "ai_i2s1_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate") + ), + [RTD1625_ISO_GPIO_161] = RTK_PIN_MUX(gpio_161, 0x18, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "vi0_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "vi1_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "vtc_i2s"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 24), "ai_i2s0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 24), "ao_i2s1_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate") + ), + [RTD1625_ISO_GPIO_162] = RTK_PIN_MUX(gpio_162, 0x18, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "vi1_dtv"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 28), "pwm0_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate") + ), + + [RTD1625_ISO_GPIO_163] = RTK_PIN_MUX(gpio_163, 0x1c, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "spdif_in_coaxial"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + + [RTD1625_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "hi_width_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "hi_width_1bit") + ), + [RTD1625_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "sf_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "sf_enable") + ), + [RTD1625_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(13, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "arm_trace_debug_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "arm_trace_debug_enable") + ), + [RTD1625_ISO_EJTAG_AUCPU0_LOC] = RTK_PIN_MUX(ejtag_aucpu0_loc, 0x120, GENMASK(16, 14), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "aucpu0_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "aucpu0_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 14), "aucpu0_ejtag_loc2") + ), + [RTD1625_ISO_EJTAG_AUCPU1_LOC] = RTK_PIN_MUX(ejtag_aucpu1_loc, 0x120, GENMASK(19, 17), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 17), "aucpu1_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 17), "aucpu1_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 17), "aucpu1_ejtag_loc2") + ), + [RTD1625_ISO_EJTAG_VE2_LOC] = RTK_PIN_MUX(ejtag_ve2_loc, 0x120, GENMASK(22, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "ve2_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "ve2_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "ve2_ejtag_loc2") + ), + [RTD1625_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "scpu_ejtag_loc2") + ), + [RTD1625_ISO_EJTAG_PCPU_LOC] = RTK_PIN_MUX(ejtag_pcpu_loc, 0x120, GENMASK(28, 26), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "pcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "pcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 26), "pcpu_ejtag_loc2") + ), + [RTD1625_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(31, 29), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 29), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 29), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 29), "acpu_ejtag_loc2") + ), + [RTD1625_ISO_I2C6_LOC] = RTK_PIN_MUX(i2c6_loc, 0x128, GENMASK(1, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "i2c6_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "i2c6_loc1") + ), + [RTD1625_ISO_UART0_LOC] = RTK_PIN_MUX(uart0_loc, 0x128, GENMASK(3, 2), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "uart0_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "uart0_loc1") + ), + [RTD1625_ISO_AI_I2S1_LOC] = RTK_PIN_MUX(ai_i2s1_loc, 0x128, GENMASK(5, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "ai_i2s1_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "ai_i2s1_loc1") + ), + [RTD1625_ISO_AO_I2S1_LOC] = RTK_PIN_MUX(ao_i2s1_loc, 0x128, GENMASK(7, 6), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "ao_i2s1_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "ao_i2s1_loc1") + ), + [RTD1625_ISO_ETN_PHY_LOC] = RTK_PIN_MUX(etn_phy_loc, 0x128, GENMASK(9, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "etn_phy_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "etn_phy_loc1") + ), + [RTD1625_ISO_SPDIF_LOC] = RTK_PIN_MUX(spdif_loc, 0x128, GENMASK(14, 13), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "spdif_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 13), "spdif_loc1") + ), + [RTD1625_ISO_RGMII_VDSEL] = RTK_PIN_MUX(rgmii_vdsel, 0x188, GENMASK(17, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "rgmii_3v3"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "rgmii_2v5"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "rgmii_1v8"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "rgmii_1v2") + ), + [RTD1625_ISO_CSI_VDSEL] = RTK_PIN_MUX(csi_vdsel, 0x188, GENMASK(19, 18), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "csi_3v3"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "csi_2v5"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "csi_1v8"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "csi_1v2") + ), + + [RTD1625_ISO_SPDIF_IN_MODE] = RTK_PIN_MUX(spdif_in_mode, 0x188, GENMASK(20, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "spdif_in_gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "spdif_in_coaxial") + ), +}; + +static const struct rtd_pin_desc rtd1625_isom_muxes[] = { + [RTD1625_ISOM_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x0, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "pctrl"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + [RTD1625_ISOM_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x0, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "pctrl"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "ir_rx_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_ISOM_GPIO_28] = RTK_PIN_MUX(gpio_28, 0x0, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart10"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "pctrl"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "isom_dbg_out"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_ISOM_GPIO_29] = RTK_PIN_MUX(gpio_29, 0x0, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart10"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "pctrl"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "ir_rx_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "isom_dbg_out"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_ISOM_IR_RX_LOC] = RTK_PIN_MUX(ir_rx_loc, 0x30, GENMASK(1, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "ir_rx_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ir_rx_loc1") + ), +}; + +static const struct rtd_pin_desc rtd1625_ve4_muxes[] = { + [RTD1625_VE4_GPIO_2] = RTK_PIN_MUX(gpio_2, 0x0, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "uart0_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + [RTD1625_VE4_GPIO_3] = RTK_PIN_MUX(gpio_3, 0x0, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "uart0_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_VE4_GPIO_4] = RTK_PIN_MUX(gpio_4, 0x0, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "gspi0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "pcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "aucpu0_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "ve2_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "gpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 8), "aucpu1_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_VE4_GPIO_5] = RTK_PIN_MUX(gpio_5, 0x0, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "gspi0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "pcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "aucpu0_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 12), "ve2_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 12), "gpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 12), "aucpu1_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_VE4_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x0, GENMASK(20, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "gspi0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "pcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "aucpu0_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "ve2_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "gpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "pwm0_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 16), "aucpu1_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate") + ), + [RTD1625_VE4_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x0, GENMASK(24, 21), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 21), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 21), "uart2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 21), "gspi0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 21), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 21), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 21), "pcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 21), "aucpu0_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 21), "ve2_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 21), "gpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 21), "pwm1_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 21), "aucpu1_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 21), "iso_tristate") + ), + [RTD1625_VE4_GPIO_12] = RTK_PIN_MUX(gpio_12, 0x0, GENMASK(28, 25), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 25), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 25), "i2c0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 25), "pwm0_loc3"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 25), "iso_tristate") + ), + + [RTD1625_VE4_GPIO_13] = RTK_PIN_MUX(gpio_13, 0x4, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "i2c0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + [RTD1625_VE4_GPIO_16] = RTK_PIN_MUX(gpio_16, 0x4, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "dptx_hpd"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 4), "pwm2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_VE4_GPIO_17] = RTK_PIN_MUX(gpio_17, 0x4, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_VE4_GPIO_18] = RTK_PIN_MUX(gpio_18, 0x4, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "pcie0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_VE4_GPIO_19] = RTK_PIN_MUX(gpio_19, 0x4, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "pwm3_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate") + ), + [RTD1625_VE4_GPIO_23] = RTK_PIN_MUX(gpio_23, 0x4, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate") + ), + [RTD1625_VE4_GPIO_24] = RTK_PIN_MUX(gpio_24, 0x4, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "i2c3"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate") + ), + [RTD1625_VE4_GPIO_25] = RTK_PIN_MUX(gpio_25, 0x4, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "i2c3"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate") + ), + + [RTD1625_VE4_GPIO_30] = RTK_PIN_MUX(gpio_30, 0x8, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "pcie1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + [RTD1625_VE4_GPIO_31] = RTK_PIN_MUX(gpio_31, 0x8, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_VE4_GPIO_32] = RTK_PIN_MUX(gpio_32, 0x8, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart9"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "ve4_uart_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_VE4_GPIO_33] = RTK_PIN_MUX(gpio_33, 0x8, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart9"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "ve4_uart_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_VE4_GPIO_34] = RTK_PIN_MUX(gpio_34, 0x8, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate") + ), + [RTD1625_VE4_GPIO_35] = RTK_PIN_MUX(gpio_35, 0x8, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate") + ), + [RTD1625_VE4_GPIO_42] = RTK_PIN_MUX(gpio_42, 0x8, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate") + ), + [RTD1625_VE4_GPIO_43] = RTK_PIN_MUX(gpio_43, 0x8, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate") + ), + + [RTD1625_VE4_GPIO_44] = RTK_PIN_MUX(gpio_44, 0xc, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + [RTD1625_VE4_GPIO_51] = RTK_PIN_MUX(gpio_51, 0xc, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "i2c6_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_VE4_GPIO_53] = RTK_PIN_MUX(gpio_53, 0xc, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart3"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ts0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "ve4_uart_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_VE4_GPIO_54] = RTK_PIN_MUX(gpio_54, 0xc, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart3"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "ts0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "ve4_uart_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_VE4_GPIO_55] = RTK_PIN_MUX(gpio_55, 0xc, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart3"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "ts0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "gspi2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate") + ), + [RTD1625_VE4_GPIO_56] = RTK_PIN_MUX(gpio_56, 0xc, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "uart3"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "ts0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "gspi2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate") + ), + [RTD1625_VE4_GPIO_57] = RTK_PIN_MUX(gpio_57, 0xc, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "uart5"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "uart0_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "gspi1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate") + ), + [RTD1625_VE4_GPIO_58] = RTK_PIN_MUX(gpio_58, 0xc, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart5"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "uart0_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "gspi1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate") + ), + + [RTD1625_VE4_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x10, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart4"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "i2c4"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "gspi1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + [RTD1625_VE4_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x10, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart4"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "i2c4"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "gspi1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_VE4_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x10, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "i2c6_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "spdif_out"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "spdif_in_optical"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_VE4_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x10, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "pll_test_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_VE4_GPIO_63] = RTK_PIN_MUX(gpio_63, 0x10, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pll_test_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate") + ), + [RTD1625_VE4_GPIO_92] = RTK_PIN_MUX(gpio_92, 0x10, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "uart6"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "i2c7"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "ve4_uart_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate") + ), + [RTD1625_VE4_GPIO_93] = RTK_PIN_MUX(gpio_93, 0x10, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "uart6"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "i2c7"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "ve4_uart_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 24), "pwm1_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate") + ), + [RTD1625_VE4_GPIO_132] = RTK_PIN_MUX(gpio_132, 0x10, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 28), "pwm6"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate") + ), + + [RTD1625_VE4_GPIO_133] = RTK_PIN_MUX(gpio_133, 0x14, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ts1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + [RTD1625_VE4_GPIO_134] = RTK_PIN_MUX(gpio_134, 0x14, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "ts1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_VE4_GPIO_135] = RTK_PIN_MUX(gpio_135, 0x14, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ts1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_VE4_GPIO_136] = RTK_PIN_MUX(gpio_136, 0x14, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "ts1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 12), "pwm0_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_VE4_GPIO_137] = RTK_PIN_MUX(gpio_137, 0x14, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "i2c6_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate") + ), + [RTD1625_VE4_GPIO_138] = RTK_PIN_MUX(gpio_138, 0x14, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "i2c6_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate") + ), + [RTD1625_VE4_GPIO_139] = RTK_PIN_MUX(gpio_139, 0x14, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate") + ), + [RTD1625_VE4_GPIO_140] = RTK_PIN_MUX(gpio_140, 0x14, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate") + ), + + [RTD1625_VE4_GPIO_141] = RTK_PIN_MUX(gpio_141, 0x18, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "csi0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + [RTD1625_VE4_GPIO_142] = RTK_PIN_MUX(gpio_142, 0x18, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_VE4_GPIO_143] = RTK_PIN_MUX(gpio_143, 0x18, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_VE4_GPIO_144] = RTK_PIN_MUX(gpio_144, 0x18, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "csi1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_VE4_GPIO_164] = RTK_PIN_MUX(gpio_164, 0x18, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "etn_led_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "etn_phy_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "i2c5"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate") + ), + [RTD1625_VE4_GPIO_165] = RTK_PIN_MUX(gpio_165, 0x18, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "etn_led_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "etn_phy_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "i2c5"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate") + ), + [RTD1625_VE4_UART_LOC] = RTK_PIN_MUX(ve4_uart_loc, 0x80, GENMASK(2, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "ve4_uart_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ve4_uart_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "ve4_uart_loc2") + ), +}; + +static const struct rtd_pin_desc rtd1625_main2_muxes[] = { + [RTD1625_MAIN2_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + [RTD1625_MAIN2_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_MAIN2_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_MAIN2_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_MAIN2_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate") + ), + [RTD1625_MAIN2_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate") + ), + [RTD1625_MAIN2_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate") + ), + [RTD1625_MAIN2_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate") + ), + + [RTD1625_MAIN2_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x4, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + [RTD1625_MAIN2_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x4, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_MAIN2_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x4, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_MAIN2_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x4, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_14] = RTK_PIN_MUX(gpio_14, 0x4, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "etn_led_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "etn_phy_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "rgmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_15] = RTK_PIN_MUX(gpio_15, 0x4, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "etn_led_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "etn_phy_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "rgmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_20] = RTK_PIN_MUX(gpio_20, 0x4, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "i2c1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_21] = RTK_PIN_MUX(gpio_21, 0x4, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "i2c1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate") + ), + + [RTD1625_MAIN2_GPIO_22] = RTK_PIN_MUX(gpio_22, 0x8, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out1") + ), + [RTD1625_MAIN2_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x8, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "pcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "aupu0_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "ve2_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 4), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "aupu1_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_MAIN2_HIF_EN] = RTK_PIN_MUX(hif_en, 0x8, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "pcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "aupu0_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "ve2_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 8), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 8), "aupu1_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_MAIN2_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x8, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "pcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "aupu0_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 12), "ve2_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 12), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 12), "aupu1_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_MAIN2_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x8, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "pcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "aupu0_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "ve2_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 16), "aupu1_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_40] = RTK_PIN_MUX(gpio_40, 0x8, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "pcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "aupu0_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "ve2_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 20), "aupu1_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_41] = RTK_PIN_MUX(gpio_41, 0x8, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_64] = RTK_PIN_MUX(gpio_64, 0x8, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate") + ), + + [RTD1625_MAIN2_GPIO_65] = RTK_PIN_MUX(gpio_65, 0xc, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "pll_test_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_66] = RTK_PIN_MUX(gpio_66, 0xc, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "pll_test_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_67] = RTK_PIN_MUX(gpio_67, 0xc, GENMASK(13, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_80] = RTK_PIN_MUX(gpio_80, 0xc, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "rmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "rgmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_81] = RTK_PIN_MUX(gpio_81, 0xc, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "rmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "rgmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_82] = RTK_PIN_MUX(gpio_82, 0xc, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "rmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "rgmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_83] = RTK_PIN_MUX(gpio_83, 0xc, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "rmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "rgmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_84] = RTK_PIN_MUX(gpio_84, 0xc, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "rmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "rgmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate") + ), + + [RTD1625_MAIN2_GPIO_85] = RTK_PIN_MUX(gpio_85, 0x10, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "rgmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_86] = RTK_PIN_MUX(gpio_86, 0x10, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "rgmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_87] = RTK_PIN_MUX(gpio_87, 0x10, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "rmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "rgmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_88] = RTK_PIN_MUX(gpio_88, 0x10, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "rmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "rgmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_89] = RTK_PIN_MUX(gpio_89, 0x10, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "rmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "rgmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_90] = RTK_PIN_MUX(gpio_90, 0x10, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "rgmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate") + ), + [RTD1625_MAIN2_GPIO_91] = RTK_PIN_MUX(gpio_91, 0x10, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "rgmii"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate") + ), +}; + +static const struct rtd_pin_config_desc rtd1625_iso_configs[] = { + [RTD1625_ISO_GPIO_8] = RTK_PIN_CONFIG_V2(gpio_8, 0x20, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_ISO_GPIO_9] = RTK_PIN_CONFIG_V2(gpio_9, 0x20, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_ISO_GPIO_10] = RTK_PIN_CONFIG_V2(gpio_10, 0x20, 12, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_11] = RTK_PIN_CONFIG_V2(gpio_11, 0x20, 18, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_45] = RTK_PIN_CONFIG(gpio_45, 0x24, 0, 0, 1, NA, 2, 12, NA), + [RTD1625_ISO_GPIO_46] = RTK_PIN_CONFIG(gpio_46, 0x24, 13, 0, 1, NA, 2, 12, NA), + [RTD1625_ISO_GPIO_47] = RTK_PIN_CONFIG(gpio_47, 0x28, 0, 0, 1, NA, 2, 12, NA), + [RTD1625_ISO_GPIO_48] = RTK_PIN_CONFIG(gpio_48, 0x28, 13, 0, 1, NA, 2, 12, NA), + [RTD1625_ISO_GPIO_49] = RTK_PIN_CONFIG(gpio_49, 0x2c, 0, 0, 1, NA, 2, 12, NA), + [RTD1625_ISO_GPIO_50] = RTK_PIN_CONFIG(gpio_50, 0x2c, 13, 0, 1, NA, 2, 12, NA), + [RTD1625_ISO_GPIO_52] = RTK_PIN_CONFIG_V2(gpio_52, 0x2c, 26, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_94] = RTK_PIN_CONFIG_V2(gpio_94, 0x30, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_ISO_GPIO_95] = RTK_PIN_CONFIG_V2(gpio_95, 0x30, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_ISO_GPIO_96] = RTK_PIN_CONFIG_V2(gpio_96, 0x30, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_ISO_GPIO_97] = RTK_PIN_CONFIG_V2(gpio_97, 0x30, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_ISO_GPIO_98] = RTK_PIN_CONFIG_V2(gpio_98, 0x30, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_ISO_GPIO_99] = RTK_PIN_CONFIG_V2(gpio_99, 0x34, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_ISO_GPIO_100] = RTK_PIN_CONFIG_V2(gpio_100, 0x34, 6, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_101] = RTK_PIN_CONFIG_V2(gpio_101, 0x34, 12, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_102] = RTK_PIN_CONFIG_V2(gpio_102, 0x34, 18, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_103] = RTK_PIN_CONFIG_V2(gpio_103, 0x34, 24, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_104] = RTK_PIN_CONFIG_V2(gpio_104, 0x38, 0, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_105] = RTK_PIN_CONFIG_V2(gpio_105, 0x38, 6, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_106] = RTK_PIN_CONFIG_V2(gpio_106, 0x38, 12, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_107] = RTK_PIN_CONFIG_V2(gpio_107, 0x38, 18, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_108] = RTK_PIN_CONFIG_V2(gpio_108, 0x38, 24, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_109] = RTK_PIN_CONFIG_V2(gpio_109, 0x3c, 0, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_110] = RTK_PIN_CONFIG_V2(gpio_110, 0x3c, 6, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_111] = RTK_PIN_CONFIG_V2(gpio_111, 0x3c, 12, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_112] = RTK_PIN_CONFIG_V2(gpio_112, 0x3c, 18, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_128] = RTK_PIN_CONFIG_V2(gpio_128, 0x3c, 24, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_129] = RTK_PIN_CONFIG_V2(gpio_129, 0x40, 0, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_130] = RTK_PIN_CONFIG_V2(gpio_130, 0x40, 6, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_131] = RTK_PIN_CONFIG_V2(gpio_131, 0x40, 12, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_145] = RTK_PIN_CONFIG_V2(gpio_145, 0x40, 18, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_146] = RTK_PIN_CONFIG_V2(gpio_146, 0x40, 24, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_147] = RTK_PIN_CONFIG_V2(gpio_147, 0x44, 0, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_148] = RTK_PIN_CONFIG_V2(gpio_148, 0x44, 6, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_149] = RTK_PIN_CONFIG_V2(gpio_149, 0x44, 12, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_150] = RTK_PIN_CONFIG_V2(gpio_150, 0x44, 18, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_151] = RTK_PIN_CONFIG_V2(gpio_151, 0x44, 24, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_152] = RTK_PIN_CONFIG_V2(gpio_152, 0x48, 0, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_153] = RTK_PIN_CONFIG_V2(gpio_153, 0x48, 6, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_154] = RTK_PIN_CONFIG_V2(gpio_154, 0x48, 12, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_155] = RTK_PIN_CONFIG_V2(gpio_155, 0x48, 18, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_156] = RTK_PIN_CONFIG_V2(gpio_156, 0x48, 24, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_157] = RTK_PIN_CONFIG_V2(gpio_157, 0x4c, 0, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_158] = RTK_PIN_CONFIG_V2(gpio_158, 0x4c, 6, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_159] = RTK_PIN_CONFIG_V2(gpio_159, 0x4c, 12, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_160] = RTK_PIN_CONFIG_V2(gpio_160, 0x4c, 18, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_161] = RTK_PIN_CONFIG_V2(gpio_161, 0x4c, 24, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_162] = RTK_PIN_CONFIG_V2(gpio_162, 0x50, 0, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_GPIO_163] = RTK_PIN_CONFIG_V2(gpio_163, 0x50, 6, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_ISO_USB_CC1] = RTK_PIN_CONFIG_V2(usb_cc1, 0x50, 12, NA, NA, 0, 1, 2, 3, + PADDRI_4_8), + [RTD1625_ISO_USB_CC2] = RTK_PIN_CONFIG_V2(usb_cc2, 0x50, 16, NA, NA, 0, 1, 2, 3, + PADDRI_4_8), +}; + +static const struct rtd_pin_config_desc rtd1625_isom_configs[] = { + [RTD1625_ISOM_GPIO_0] = RTK_PIN_CONFIG_V2(gpio_0, 0x4, 5, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_ISOM_GPIO_1] = RTK_PIN_CONFIG_V2(gpio_1, 0x4, 11, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_ISOM_GPIO_28] = RTK_PIN_CONFIG_V2(gpio_28, 0x4, 17, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_ISOM_GPIO_29] = RTK_PIN_CONFIG_V2(gpio_29, 0x4, 23, 1, 2, 0, 3, 4, 5, PADDRI_4_8), +}; + +static const struct rtd_pin_config_desc rtd1625_ve4_configs[] = { + [RTD1625_VE4_GPIO_2] = RTK_PIN_CONFIG_V2(gpio_2, 0x1c, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_3] = RTK_PIN_CONFIG_V2(gpio_3, 0x1c, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_4] = RTK_PIN_CONFIG_V2(gpio_4, 0x1c, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_5] = RTK_PIN_CONFIG_V2(gpio_5, 0x1c, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_6] = RTK_PIN_CONFIG_V2(gpio_6, 0x1c, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_7] = RTK_PIN_CONFIG_V2(gpio_7, 0x20, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_12] = RTK_PIN_CONFIG_V2(gpio_12, 0x20, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_13] = RTK_PIN_CONFIG_V2(gpio_13, 0x20, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_16] = RTK_PIN_CONFIG_V2(gpio_16, 0x20, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_17] = RTK_PIN_CONFIG_V2(gpio_17, 0x20, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_18] = RTK_PIN_CONFIG_V2(gpio_18, 0x24, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_19] = RTK_PIN_CONFIG_V2(gpio_19, 0x24, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_23] = RTK_PIN_CONFIG_V2(gpio_23, 0x24, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_24] = RTK_PIN_CONFIG_V2(gpio_24, 0x24, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_25] = RTK_PIN_CONFIG_V2(gpio_25, 0x24, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_30] = RTK_PIN_CONFIG_V2(gpio_30, 0x28, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_31] = RTK_PIN_CONFIG_V2(gpio_31, 0x28, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_32] = RTK_PIN_CONFIG_V2(gpio_32, 0x28, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_33] = RTK_PIN_CONFIG_V2(gpio_33, 0x28, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_34] = RTK_PIN_CONFIG_V2(gpio_34, 0x28, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_35] = RTK_PIN_CONFIG_V2(gpio_35, 0x2c, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_42] = RTK_PIN_CONFIG_V2(gpio_42, 0x2c, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_43] = RTK_PIN_CONFIG_V2(gpio_43, 0x2c, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_44] = RTK_PIN_CONFIG_V2(gpio_44, 0x2c, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_51] = RTK_PIN_CONFIG_V2(gpio_51, 0x2c, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_53] = RTK_PIN_CONFIG_V2(gpio_53, 0x30, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_54] = RTK_PIN_CONFIG_V2(gpio_54, 0x30, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_55] = RTK_PIN_CONFIG_V2(gpio_55, 0x30, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_56] = RTK_PIN_CONFIG_V2(gpio_56, 0x30, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_57] = RTK_PIN_CONFIG_V2(gpio_57, 0x30, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_58] = RTK_PIN_CONFIG_V2(gpio_58, 0x34, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_59] = RTK_PIN_CONFIG_V2(gpio_59, 0x34, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_60] = RTK_PIN_CONFIG_V2(gpio_60, 0x34, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_61] = RTK_PIN_CONFIG_V2(gpio_61, 0x34, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_62] = RTK_PIN_CONFIG_V2(gpio_62, 0x34, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_63] = RTK_PIN_CONFIG_V2(gpio_63, 0x38, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_92] = RTK_PIN_CONFIG_V2(gpio_92, 0x38, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_93] = RTK_PIN_CONFIG_V2(gpio_93, 0x38, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8), + [RTD1625_VE4_GPIO_132] = RTK_PIN_CONFIG_V2(gpio_132, 0x38, 18, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_VE4_GPIO_133] = RTK_PIN_CONFIG_V2(gpio_133, 0x38, 24, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_VE4_GPIO_134] = RTK_PIN_CONFIG_V2(gpio_134, 0x3c, 0, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_VE4_GPIO_135] = RTK_PIN_CONFIG_V2(gpio_135, 0x3c, 6, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_VE4_GPIO_136] = RTK_PIN_CONFIG_V2(gpio_136, 0x3c, 12, 1, 2, 0, 3, 4, 5, + PADDRI_4_8), + [RTD1625_VE4_GPIO_137] = RTK_PIN_CONFIG(gpio_137, 0x3c, 18, 1, 2, 0, NA, NA, PADDRI_4_8), + [RTD1625_VE4_GPIO_138] = RTK_PIN_CONFIG(gpio_138, 0x3c, 21, 1, 2, 0, NA, NA, PADDRI_4_8), + [RTD1625_VE4_GPIO_139] = RTK_PIN_CONFIG(gpio_139, 0x3c, 24, 1, 2, 0, NA, NA, PADDRI_4_8), + [RTD1625_VE4_GPIO_140] = RTK_PIN_CONFIG(gpio_140, 0x3c, 27, 1, 2, 0, NA, NA, PADDRI_4_8), + [RTD1625_VE4_GPIO_141] = RTK_PIN_CONFIG(gpio_141, 0x40, 0, 1, 2, 0, NA, NA, PADDRI_4_8), + [RTD1625_VE4_GPIO_142] = RTK_PIN_CONFIG(gpio_142, 0x40, 3, 1, 2, 0, NA, NA, PADDRI_4_8), + [RTD1625_VE4_GPIO_143] = RTK_PIN_CONFIG(gpio_143, 0x40, 6, 1, 2, 0, NA, NA, PADDRI_4_8), + [RTD1625_VE4_GPIO_144] = RTK_PIN_CONFIG(gpio_144, 0x40, 9, 1, 2, 0, NA, NA, PADDRI_4_8), + [RTD1625_VE4_GPIO_164] = RTK_PIN_CONFIG(gpio_164, 0x40, 12, 1, 2, 0, NA, NA, PADDRI_4_8), + [RTD1625_VE4_GPIO_165] = RTK_PIN_CONFIG(gpio_165, 0x40, 15, 1, 2, 0, NA, NA, PADDRI_4_8), +}; + +static const struct rtd_pin_config_desc rtd1625_main2_configs[] = { + [RTD1625_MAIN2_EMMC_CLK] = RTK_PIN_CONFIG(emmc_clk, 0x14, 0, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_EMMC_CMD] = RTK_PIN_CONFIG(emmc_cmd, 0x14, 13, 0, 1, NA, 2, 13, NA), + [RTD1625_MAIN2_EMMC_DATA_0] = RTK_PIN_CONFIG(emmc_data_0, 0x18, 0, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_EMMC_DATA_1] = RTK_PIN_CONFIG(emmc_data_1, 0x18, 13, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_EMMC_DATA_2] = RTK_PIN_CONFIG(emmc_data_2, 0x1c, 0, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_EMMC_DATA_3] = RTK_PIN_CONFIG(emmc_data_3, 0x1c, 13, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_EMMC_DATA_4] = RTK_PIN_CONFIG(emmc_data_4, 0x20, 0, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_EMMC_DATA_5] = RTK_PIN_CONFIG(emmc_data_5, 0x20, 13, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_EMMC_DATA_6] = RTK_PIN_CONFIG(emmc_data_6, 0x24, 0, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_EMMC_DATA_7] = RTK_PIN_CONFIG(emmc_data_7, 0x24, 13, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_EMMC_DD_SB] = RTK_PIN_CONFIG(emmc_dd_sb, 0x28, 0, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_EMMC_RST_N] = RTK_PIN_CONFIG(emmc_rst_n, 0x28, 13, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_GPIO_14] = RTK_PIN_CONFIG(gpio_14, 0x28, 26, 1, 2, 0, NA, NA, PADDRI_4_8), + [RTD1625_MAIN2_GPIO_15] = RTK_PIN_CONFIG(gpio_15, 0x28, 29, 1, 2, 0, NA, NA, PADDRI_4_8), + [RTD1625_MAIN2_GPIO_20] = RTK_PIN_CONFIG_I2C(gpio_20, 0x2c, 0, 1, 2, 0, 3, 4, 5, 7, 8, + PADDRI_4_8), + [RTD1625_MAIN2_GPIO_21] = RTK_PIN_CONFIG_I2C(gpio_21, 0x2c, 9, 1, 2, 0, 3, 4, 5, 7, 8, + PADDRI_4_8), + [RTD1625_MAIN2_GPIO_22] = RTK_PIN_CONFIG_V2(gpio_22, 0x2c, 18, 1, 2, 0, 3, 7, 8, + PADDRI_4_8), + [RTD1625_MAIN2_GPIO_40] = RTK_PIN_CONFIG(gpio_40, 0x30, 0, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_GPIO_41] = RTK_PIN_CONFIG(gpio_41, 0x30, 13, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_GPIO_64] = RTK_PIN_CONFIG(gpio_64, 0x34, 0, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_GPIO_65] = RTK_PIN_CONFIG(gpio_65, 0x34, 13, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_GPIO_66] = RTK_PIN_CONFIG(gpio_66, 0x38, 0, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_GPIO_67] = RTK_PIN_CONFIG(gpio_67, 0x38, 13, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_GPIO_80] = RTK_PIN_CONFIG(gpio_80, 0x38, 26, 1, 2, 0, NA, NA, PADDRI_4_8), + [RTD1625_MAIN2_GPIO_81] = RTK_PIN_CONFIG(gpio_81, 0x38, 29, 1, 2, 0, NA, NA, PADDRI_4_8), + [RTD1625_MAIN2_GPIO_82] = RTK_PIN_CONFIG(gpio_82, 0x3c, 0, 1, 2, 0, NA, NA, PADDRI_4_8), + [RTD1625_MAIN2_GPIO_83] = RTK_PIN_CONFIG(gpio_83, 0x3c, 3, 1, 2, 0, NA, NA, PADDRI_4_8), + [RTD1625_MAIN2_GPIO_84] = RTK_PIN_CONFIG(gpio_84, 0x3c, 6, 1, 2, 0, NA, NA, PADDRI_4_8), + [RTD1625_MAIN2_GPIO_85] = RTK_PIN_CONFIG(gpio_85, 0x3c, 9, 1, 2, NA, NA, NA, PADDRI_4_8), + [RTD1625_MAIN2_GPIO_86] = RTK_PIN_CONFIG(gpio_86, 0x3c, 12, 1, 2, NA, NA, NA, PADDRI_4_8), + [RTD1625_MAIN2_GPIO_87] = RTK_PIN_CONFIG(gpio_87, 0x3c, 22, 1, 2, NA, NA, NA, PADDRI_4_8), + [RTD1625_MAIN2_GPIO_88] = RTK_PIN_CONFIG(gpio_88, 0x40, 0, 1, 2, NA, NA, NA, PADDRI_4_8), + [RTD1625_MAIN2_GPIO_89] = RTK_PIN_CONFIG(gpio_89, 0x40, 10, 1, 2, NA, NA, NA, PADDRI_4_8), + [RTD1625_MAIN2_GPIO_90] = RTK_PIN_CONFIG(gpio_90, 0x40, 20, 1, 2, NA, NA, NA, PADDRI_4_8), + [RTD1625_MAIN2_GPIO_91] = RTK_PIN_CONFIG(gpio_91, 0x44, 0, 1, 2, NA, NA, NA, PADDRI_4_8), + [RTD1625_MAIN2_HIF_CLK] = RTK_PIN_CONFIG(hif_clk, 0x44, 10, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_HIF_DATA] = RTK_PIN_CONFIG(hif_data, 0x48, 0, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_HIF_EN] = RTK_PIN_CONFIG(hif_en, 0x48, 13, 0, 1, NA, 2, 12, NA), + [RTD1625_MAIN2_HIF_RDY] = RTK_PIN_CONFIG(hif_rdy, 0x4c, 0, 0, 1, NA, 2, 12, NA), +}; + +static const struct rtd_pin_sconfig_desc rtd1625_iso_sconfigs[] = { + RTK_PIN_SCONFIG(gpio_45, 0x24, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_46, 0x24, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_47, 0x28, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_48, 0x28, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_49, 0x2c, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_50, 0x2c, 16, 3, 19, 3, 22, 3), +}; + +static const struct rtd_pin_sconfig_desc rtd1625_main2_sconfigs[] = { + RTK_PIN_SCONFIG(emmc_clk, 0x14, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_cmd, 0x14, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_0, 0x18, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_1, 0x18, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_2, 0x1c, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_3, 0x1c, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_4, 0x20, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_5, 0x20, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_6, 0x24, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_7, 0x24, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_dd_sb, 0x28, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_rst_n, 0x28, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_40, 0x30, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_41, 0x30, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_64, 0x34, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_65, 0x34, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_66, 0x38, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_67, 0x38, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_86, 0x3c, 0, 0, 14, 4, 18, 4), + RTK_PIN_SCONFIG(gpio_87, 0x3c, 0, 0, 24, 4, 28, 4), + RTK_PIN_SCONFIG(gpio_88, 0x40, 0, 0, 2, 4, 6, 4), + RTK_PIN_SCONFIG(gpio_89, 0x40, 0, 0, 12, 4, 16, 4), + RTK_PIN_SCONFIG(gpio_90, 0x40, 0, 0, 22, 4, 26, 4), + RTK_PIN_SCONFIG(gpio_91, 0x44, 0, 0, 2, 4, 6, 4), + RTK_PIN_SCONFIG(hif_clk, 0x44, 13, 3, 16, 3, 19, 3), + RTK_PIN_SCONFIG(hif_data, 0x48, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(hif_en, 0x48, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(hif_rdy, 0x4c, 3, 3, 6, 3, 9, 3), +}; + +static const struct rtd_reg_range rtd1625_iso_reg_ranges[] = { + { .offset = 0x0, .len = 0x58 }, + { .offset = 0x120, .len = 0x10 }, + { .offset = 0x180, .len = 0xc }, + { .offset = 0x1A0, .len = 0xc }, +}; + +static const struct rtd_pin_range rtd1625_iso_pin_ranges = { + .ranges = rtd1625_iso_reg_ranges, + .num_ranges = ARRAY_SIZE(rtd1625_iso_reg_ranges), +}; + +static const struct rtd_reg_range rtd1625_isom_reg_ranges[] = { + { .offset = 0x0, .len = 0xc }, + { .offset = 0x30, .len = 0x4 }, +}; + +static const struct rtd_pin_range rtd1625_isom_pin_ranges = { + .ranges = rtd1625_isom_reg_ranges, + .num_ranges = ARRAY_SIZE(rtd1625_isom_reg_ranges), +}; + +static const struct rtd_reg_range rtd1625_ve4_reg_ranges[] = { + { .offset = 0x0, .len = 0x48 }, + { .offset = 0x80, .len = 0x4 }, +}; + +static const struct rtd_pin_range rtd1625_ve4_pin_ranges = { + .ranges = rtd1625_ve4_reg_ranges, + .num_ranges = ARRAY_SIZE(rtd1625_ve4_reg_ranges), +}; + +static const struct rtd_reg_range rtd1625_main2_reg_ranges[] = { + { .offset = 0x0, .len = 0x50 }, +}; + +static const struct rtd_pin_range rtd1625_main2_pin_ranges = { + .ranges = rtd1625_main2_reg_ranges, + .num_ranges = ARRAY_SIZE(rtd1625_main2_reg_ranges), +}; + +static const struct rtd_pinctrl_desc rtd1625_iso_pinctrl_desc = { + .pins = rtd1625_iso_pins, + .num_pins = ARRAY_SIZE(rtd1625_iso_pins), + .groups = rtd1625_iso_pin_groups, + .num_groups = ARRAY_SIZE(rtd1625_iso_pin_groups), + .functions = rtd1625_iso_pin_functions, + .num_functions = ARRAY_SIZE(rtd1625_iso_pin_functions), + .muxes = rtd1625_iso_muxes, + .num_muxes = ARRAY_SIZE(rtd1625_iso_muxes), + .configs = rtd1625_iso_configs, + .num_configs = ARRAY_SIZE(rtd1625_iso_configs), + .sconfigs = rtd1625_iso_sconfigs, + .num_sconfigs = ARRAY_SIZE(rtd1625_iso_sconfigs), + .pin_range = &rtd1625_iso_pin_ranges, +}; + +static const struct rtd_pinctrl_desc rtd1625_isom_pinctrl_desc = { + .pins = rtd1625_isom_pins, + .num_pins = ARRAY_SIZE(rtd1625_isom_pins), + .groups = rtd1625_isom_pin_groups, + .num_groups = ARRAY_SIZE(rtd1625_isom_pin_groups), + .functions = rtd1625_isom_pin_functions, + .num_functions = ARRAY_SIZE(rtd1625_isom_pin_functions), + .muxes = rtd1625_isom_muxes, + .num_muxes = ARRAY_SIZE(rtd1625_isom_muxes), + .configs = rtd1625_isom_configs, + .num_configs = ARRAY_SIZE(rtd1625_isom_configs), + .pin_range = &rtd1625_isom_pin_ranges, +}; + +static const struct rtd_pinctrl_desc rtd1625_ve4_pinctrl_desc = { + .pins = rtd1625_ve4_pins, + .num_pins = ARRAY_SIZE(rtd1625_ve4_pins), + .groups = rtd1625_ve4_pin_groups, + .num_groups = ARRAY_SIZE(rtd1625_ve4_pin_groups), + .functions = rtd1625_ve4_pin_functions, + .num_functions = ARRAY_SIZE(rtd1625_ve4_pin_functions), + .muxes = rtd1625_ve4_muxes, + .num_muxes = ARRAY_SIZE(rtd1625_ve4_muxes), + .configs = rtd1625_ve4_configs, + .num_configs = ARRAY_SIZE(rtd1625_ve4_configs), + .pin_range = &rtd1625_ve4_pin_ranges, +}; + +static const struct rtd_pinctrl_desc rtd1625_main2_pinctrl_desc = { + .pins = rtd1625_main2_pins, + .num_pins = ARRAY_SIZE(rtd1625_main2_pins), + .groups = rtd1625_main2_pin_groups, + .num_groups = ARRAY_SIZE(rtd1625_main2_pin_groups), + .functions = rtd1625_main2_pin_functions, + .num_functions = ARRAY_SIZE(rtd1625_main2_pin_functions), + .muxes = rtd1625_main2_muxes, + .num_muxes = ARRAY_SIZE(rtd1625_main2_muxes), + .configs = rtd1625_main2_configs, + .num_configs = ARRAY_SIZE(rtd1625_main2_configs), + .sconfigs = rtd1625_main2_sconfigs, + .num_sconfigs = ARRAY_SIZE(rtd1625_main2_sconfigs), + .pin_range = &rtd1625_main2_pin_ranges, +}; + +static int rtd1625_pinctrl_probe(struct platform_device *pdev) +{ + const struct rtd_pinctrl_desc *desc = device_get_match_data(&pdev->dev); + + return rtd_pinctrl_probe(pdev, desc); +} + +static const struct of_device_id rtd1625_pinctrl_of_match[] = { + {.compatible = "realtek,rtd1625-iso-pinctrl", .data = &rtd1625_iso_pinctrl_desc}, + {.compatible = "realtek,rtd1625-isom-pinctrl", .data = &rtd1625_isom_pinctrl_desc}, + {.compatible = "realtek,rtd1625-ve4-pinctrl", .data = &rtd1625_ve4_pinctrl_desc}, + {.compatible = "realtek,rtd1625-main2-pinctrl", .data = &rtd1625_main2_pinctrl_desc}, + {}, +}; +MODULE_DEVICE_TABLE(of, rtd1625_pinctrl_of_match); + +static struct platform_driver rtd1625_pinctrl_driver = { + .driver = { + .name = "rtd1625-pinctrl", + .of_match_table = rtd1625_pinctrl_of_match, + .pm = &realtek_pinctrl_pm_ops, + }, + .probe = rtd1625_pinctrl_probe, +}; + +module_platform_driver(rtd1625_pinctrl_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Realtek Semiconductor Corporation"); +MODULE_DESCRIPTION("Realtek DHC SoC RTD1625 pinctrl driver"); From 34006f77890d050e6d80cbee365b5d703c1140b4 Mon Sep 17 00:00:00 2001 From: Yu-Chun Lin Date: Fri, 20 Mar 2026 23:15:06 +0800 Subject: [PATCH 62/84] pinctrl: abx500: Fix type of 'argument' variable The argument variable is assigned the return value of pinconf_to_config_argument(), which returns a u32. Change its type from enum pin_config_param to unsigned int to correctly store the configuration argument. Fixes: 03b054e9696c ("pinctrl: Pass all configs to driver on pin_config_set()") Signed-off-by: Yu-Chun Lin Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-abx500.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c index fc7ebeda8440..858fbaebcf8e 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.c +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -852,7 +852,7 @@ static int abx500_pin_config_set(struct pinctrl_dev *pctldev, int ret = -EINVAL; int i; enum pin_config_param param; - enum pin_config_param argument; + unsigned int argument; for (i = 0; i < num_configs; i++) { param = pinconf_to_config_param(configs[i]); From 9efe63b74e9c30777db9815dc5d38d667576ac6f Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 19 Mar 2026 14:15:14 +0000 Subject: [PATCH 63/84] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties Document the pin configuration properties supported by the RZ/T2H pinctrl driver. The RZ/T2H SoC allows configuring several electrical characteristics through the DRCTLm (I/O Buffer Function Switching) registers. These registers control drive strength, bias configuration, Schmitt trigger input, and output slew rate. Signed-off-by: Lad Prabhakar Acked-by: Conor Dooley Reviewed-by: Linus Walleij Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260319141515.2053556-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../pinctrl/renesas,r9a09g077-pinctrl.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml index f049013a4e0c..63993b20524f 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml @@ -83,6 +83,23 @@ definitions: input: true input-enable: true output-enable: true + bias-disable: true + bias-pull-down: true + bias-pull-up: true + input-schmitt-enable: true + input-schmitt-disable: true + slew-rate: + description: 0 is slow slew rate, 1 is fast slew rate + enum: [0, 1] + drive-strength-microamp: + description: | + Four discrete levels are supported (via registers DRCTLm), corresponding + to the following nominal values: + - 2500 (Low strength) + - 5000 (Middle strength) + - 9000 (High strength) + - 11800 (Ultra High strength) + enum: [2500, 5000, 9000, 11800] oneOf: - required: [pinmux] - required: [pins] From 494feecd60e876a4310cdda279d918e91f930091 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 19 Mar 2026 14:15:15 +0000 Subject: [PATCH 64/84] pinctrl: renesas: rzt2h: Add pin configuration support Add pin configuration support for the Renesas RZ/T2H SoC. The RZ/T2H SoC allows configuring several electrical characteristics through the DRCTLm (I/O Buffer Function Switching) registers. These registers control bias configuration, Schmitt trigger input, output slew rate, and drive strength. Implement pinconf_ops to allow reading and updating these properties through the generic pin configuration framework. The implementation supports bias-disable, bias-pull-up, bias-pull-down, input-schmitt-enable, slew-rate, and drive-strength-microamp. Signed-off-by: Lad Prabhakar Reviewed-by: Linus Walleij Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260319141515.2053556-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzt2h.c | 258 ++++++++++++++++++++++++ 1 file changed, 258 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/renesas/pinctrl-rzt2h.c index 5927744c7a96..4ba11a83b604 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -7,6 +7,7 @@ * Copyright (C) 2025 Renesas Electronics Corporation. */ +#include #include #include #include @@ -43,6 +44,7 @@ #define PMC(m) (0x400 + (m)) #define PFC(m) (0x600 + 8 * (m)) #define PIN(m) (0x800 + (m)) +#define DRCTL(n) (0xa00 + 8 * (n)) #define RSELP(m) (0xc00 + (m)) #define PM_MASK GENMASK(1, 0) @@ -54,6 +56,15 @@ #define PFC_PIN_MASK(pin) (PFC_MASK << ((pin) * 8)) #define PFC_FUNC_INTERRUPT 0 +#define DRCTL_DRV_PIN_MASK(pin) (GENMASK_ULL(1, 0) << ((pin) * 8)) +#define DRCTL_PUD_PIN_MASK(pin) (GENMASK_ULL(3, 2) << ((pin) * 8)) +#define DRCTL_SMT_PIN_MASK(pin) (BIT_ULL(4) << ((pin) * 8)) +#define DRCTL_SR_PIN_MASK(pin) (BIT_ULL(5) << ((pin) * 8)) + +#define DRCTL_PUD_NONE 0 +#define DRCTL_PUD_PULL_UP 1 +#define DRCTL_PUD_PULL_DOWN 2 + /* * Use 16 lower bits [15:0] for pin identifier * Use 8 higher bits [23:16] for pin mux function @@ -91,6 +102,8 @@ struct rzt2h_pinctrl { atomic_t wakeup_path; }; +static const unsigned int rzt2h_drive_strength_ua[] = { 2500, 5000, 9000, 11800 }; + #define RZT2H_GET_BASE(pctrl, port) \ ((port) > RZT2H_MAX_SAFETY_PORTS ? (pctrl)->base0 : (pctrl)->base1) @@ -110,6 +123,37 @@ RZT2H_PINCTRL_REG_ACCESS(b, u8) RZT2H_PINCTRL_REG_ACCESS(w, u16) RZT2H_PINCTRL_REG_ACCESS(q, u64) +static int rzt2h_drive_strength_ua_to_idx(unsigned int ua) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(rzt2h_drive_strength_ua); i++) { + if (rzt2h_drive_strength_ua[i] == ua) + return i; + } + + return -EINVAL; +} + +static int rzt2h_drive_strength_idx_to_ua(unsigned int idx) +{ + if (idx >= ARRAY_SIZE(rzt2h_drive_strength_ua)) + return -EINVAL; + + return rzt2h_drive_strength_ua[idx]; +} + +static void rzt2h_pinctrl_drctl_rmwq(struct rzt2h_pinctrl *pctrl, + u32 port, u64 mask, u64 val) +{ + u32 offset = DRCTL(port); + u64 drctl; + + guard(raw_spinlock_irqsave)(&pctrl->lock); + drctl = rzt2h_pinctrl_readq(pctrl, port, offset) & ~mask; + rzt2h_pinctrl_writeq(pctrl, port, drctl | val, offset); +} + static int rzt2h_validate_pin(struct rzt2h_pinctrl *pctrl, unsigned int offset) { u8 port = RZT2H_PIN_ID_TO_PORT(offset); @@ -443,6 +487,210 @@ static int rzt2h_dt_node_to_map(struct pinctrl_dev *pctldev, return ret; } +static int rzt2h_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *config) +{ + struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + u32 port, param = pinconf_to_config_param(*config); + unsigned int arg; + u8 port_pin; + u64 drctl; + int ret; + + ret = rzt2h_validate_pin(pctrl, pin); + if (ret) + return ret; + + port = RZT2H_PIN_ID_TO_PORT(pin); + port_pin = RZT2H_PIN_ID_TO_PIN(pin); + + switch (param) { + case PIN_CONFIG_SLEW_RATE: + drctl = rzt2h_pinctrl_readq(pctrl, port, DRCTL(port)); + arg = field_get(DRCTL_SR_PIN_MASK(port_pin), drctl); + break; + + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + drctl = rzt2h_pinctrl_readq(pctrl, port, DRCTL(port)); + arg = field_get(DRCTL_PUD_PIN_MASK(port_pin), drctl); + /* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */ + switch (arg) { + case DRCTL_PUD_NONE: + if (param != PIN_CONFIG_BIAS_DISABLE) + return -EINVAL; + break; + case DRCTL_PUD_PULL_UP: + if (param != PIN_CONFIG_BIAS_PULL_UP) + return -EINVAL; + arg = 1; + break; + case DRCTL_PUD_PULL_DOWN: + if (param != PIN_CONFIG_BIAS_PULL_DOWN) + return -EINVAL; + arg = 1; + break; + default: + return -EINVAL; + } + break; + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + drctl = rzt2h_pinctrl_readq(pctrl, port, DRCTL(port)); + arg = field_get(DRCTL_SMT_PIN_MASK(port_pin), drctl); + if (!arg) + return -EINVAL; + break; + + case PIN_CONFIG_DRIVE_STRENGTH_UA: { + int idx_drv; + + drctl = rzt2h_pinctrl_readq(pctrl, port, DRCTL(port)); + arg = field_get(DRCTL_DRV_PIN_MASK(port_pin), drctl); + idx_drv = rzt2h_drive_strength_idx_to_ua(arg); + if (idx_drv < 0) + return idx_drv; + arg = idx_drv; + break; + } + + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int rzt2h_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *configs, + unsigned int num_configs) +{ + struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned int i; + u8 port_pin; + int ret; + + ret = rzt2h_validate_pin(pctrl, pin); + if (ret) + return ret; + + port_pin = RZT2H_PIN_ID_TO_PIN(pin); + + for (i = 0; i < num_configs; i++) { + u32 arg = pinconf_to_config_argument(configs[i]); + u32 param = pinconf_to_config_param(configs[i]); + u64 mask, val; + + switch (param) { + case PIN_CONFIG_SLEW_RATE: + mask = DRCTL_SR_PIN_MASK(port_pin); + val = field_prep(mask, !!arg); + break; + + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: { + u32 bias; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + bias = DRCTL_PUD_NONE; + break; + case PIN_CONFIG_BIAS_PULL_UP: + bias = DRCTL_PUD_PULL_UP; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + bias = DRCTL_PUD_PULL_DOWN; + break; + } + + mask = DRCTL_PUD_PIN_MASK(port_pin); + val = field_prep(mask, bias); + break; + } + + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + mask = DRCTL_SMT_PIN_MASK(port_pin); + val = field_prep(mask, !!arg); + break; + + case PIN_CONFIG_DRIVE_STRENGTH_UA: { + int drv_idx; + + drv_idx = rzt2h_drive_strength_ua_to_idx(arg); + if (drv_idx < 0) + return drv_idx; + + mask = DRCTL_DRV_PIN_MASK(port_pin); + val = field_prep(mask, drv_idx); + break; + } + + default: + return -ENOTSUPP; + } + + rzt2h_pinctrl_drctl_rmwq(pctrl, RZT2H_PIN_ID_TO_PORT(pin), mask, val); + } + + return 0; +} + +static int rzt2h_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *config) +{ + unsigned long prev_config = 0; + const unsigned int *pins; + unsigned int i, npins; + int ret; + + ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + + for (i = 0; i < npins; i++) { + ret = rzt2h_pinctrl_pinconf_get(pctldev, pins[i], config); + if (ret) + return ret; + + /* Check config matches previous pins */ + if (i && prev_config != *config) + return -ENOTSUPP; + + prev_config = *config; + } + + return 0; +} + +static int rzt2h_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *configs, + unsigned int num_configs) +{ + const unsigned int *pins; + unsigned int i, npins; + int ret; + + ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + + for (i = 0; i < npins; i++) { + ret = rzt2h_pinctrl_pinconf_set(pctldev, pins[i], configs, + num_configs); + if (ret) + return ret; + } + + return 0; +} + static const struct pinctrl_ops rzt2h_pinctrl_pctlops = { .get_groups_count = pinctrl_generic_get_group_count, .get_group_name = pinctrl_generic_get_group_name, @@ -459,6 +707,15 @@ static const struct pinmux_ops rzt2h_pinctrl_pmxops = { .strict = true, }; +static const struct pinconf_ops rzt2h_pinctrl_confops = { + .is_generic = true, + .pin_config_get = rzt2h_pinctrl_pinconf_get, + .pin_config_set = rzt2h_pinctrl_pinconf_set, + .pin_config_group_set = rzt2h_pinctrl_pinconf_group_set, + .pin_config_group_get = rzt2h_pinctrl_pinconf_group_get, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + static int rzt2h_gpio_request(struct gpio_chip *chip, unsigned int offset) { struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); @@ -890,6 +1147,7 @@ static int rzt2h_pinctrl_register(struct rzt2h_pinctrl *pctrl) desc->npins = pctrl->data->n_port_pins; desc->pctlops = &rzt2h_pinctrl_pctlops; desc->pmxops = &rzt2h_pinctrl_pmxops; + desc->confops = &rzt2h_pinctrl_confops; desc->owner = THIS_MODULE; pins = devm_kcalloc(dev, desc->npins, sizeof(*pins), GFP_KERNEL); From d9a60e367919752a1d398ebeba667f1e200fae1e Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 26 Mar 2026 16:24:51 +0000 Subject: [PATCH 65/84] pinctrl: renesas: rzg2l: Fix save/restore of {IOLH,IEN,PUPD,SMT} registers The rzg2l_pinctrl_pm_setup_regs() handles save/restore of {IOLH,IEN,PUPD,SMT} registers during s2ram, but only for ports where all pins share the same pincfg. Extend the code to also support ports with variable pincfg per pin, so that {IOLH,IEN,PUPD,SMT} registers are correctly saved and restored for all pins. Fixes: 254203f9a94c ("pinctrl: renesas: rzg2l: Add suspend/resume support") Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260326162459.101414-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 863e779dda02..55e35f63343c 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -3012,6 +3012,13 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); pincnt = hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg)); + if (cfg & RZG2L_VARIABLE_CFG) { + unsigned int pin = port * RZG2L_PINS_PER_PORT; + + for (unsigned int i = 0; i < RZG2L_PINS_PER_PORT; i++) + cfg |= *(u64 *)pctrl->desc.pins[pin + i].drv_data; + } + caps = FIELD_GET(PIN_CFG_MASK, cfg); has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); has_ien = !!(caps & PIN_CFG_IEN); From 3f92867ce3ee2a274ebb7e7d5de7f6ee85da21f6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 26 Mar 2026 19:17:11 +0100 Subject: [PATCH 66/84] pinctrl: renesas: rzg2l: Drop superfluous blank line No need for a blank line after a "case" statement. Signed-off-by: Geert Uytterhoeven Link: https://patch.msgid.link/7bfa105cf72d3b3e72a45d6218b5d88c8a7f520f.1774548955.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 55e35f63343c..561e6018fd89 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1475,7 +1475,6 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, arg = pinconf_to_config_argument(_configs[i]); switch (param) { case PIN_CONFIG_INPUT_ENABLE: - if (!(cfg & PIN_CFG_IEN)) return -EINVAL; From 127e98c05c46654867faf5f578cb56d375b89092 Mon Sep 17 00:00:00 2001 From: Basavaraj Natikar Date: Fri, 27 Mar 2026 10:36:16 +0530 Subject: [PATCH 67/84] pinctrl: amd: Support new ACPI ID AMDI0033 Add AMDI0033 to the AMD GPIO ACPI match table. This lets the driver bind on new AMD platforms that expose this HID. Signed-off-by: Basavaraj Natikar Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-amd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 2af94ef56434..e3128b0045d2 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -1274,6 +1274,7 @@ static const struct acpi_device_id amd_gpio_acpi_match[] = { { "AMD0030", 0 }, { "AMDI0030", 0}, { "AMDI0031", 0}, + { "AMDI0033", 0}, { }, }; MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); From b4e93cbc60641ce2d02d3438cdf59657c8c268b6 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 23 Mar 2026 14:41:23 +0100 Subject: [PATCH 68/84] pinctrl: core: Don't use "proxy" headers Update header inclusions to follow IWYU (Include What You Use) principle. Signed-off-by: Andy Shevchenko Signed-off-by: Linus Walleij --- drivers/pinctrl/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 07a6b7fe1c9c..6cbcaa6709da 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -24,7 +24,7 @@ #include #include -#include +#include #include #include From fe8933c5b3e2e5294f82da546792268e5687391e Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Fri, 27 Mar 2026 22:42:39 +0530 Subject: [PATCH 69/84] pinctrl: qcom: eliza: Fix interrupt target bit The intr_target_bit for Eliza was incorrectly set to 5, which is the value used by older Qualcomm SoCs (e.g. SM8250, MSM8996, X1E80100). Newer SoCs such as SM8650, SM8750, Milos, and Kaanapali all use bit 8 for the interrupt target field in the TLMM interrupt configuration register. Eliza belongs to the newer generation and should use bit 8 to correctly route interrupts to the KPSS (Applications Processor). Using the wrong bit position means the interrupt target routing is silently misconfigured, which can result in GPIO interrupts not being delivered to the expected processor. Fix this by aligning Eliza with the correct value used by its peer SoCs. Fixes: 6f26989e15fb ("pinctrl: qcom: Add Eliza pinctrl driver") Signed-off-by: Mukesh Ojha Reviewed-by: Abel Vesa Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-eliza.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pinctrl-eliza.c index 1a2e6461a69b..19c706137f81 100644 --- a/drivers/pinctrl/qcom/pinctrl-eliza.c +++ b/drivers/pinctrl/qcom/pinctrl-eliza.c @@ -47,7 +47,7 @@ .intr_status_bit = 0, \ .intr_wakeup_present_bit = 6, \ .intr_wakeup_enable_bit = 7, \ - .intr_target_bit = 5, \ + .intr_target_bit = 8, \ .intr_target_kpss_val = 3, \ .intr_raw_status_bit = 4, \ .intr_polarity_bit = 1, \ From 0720208b37ae4f1193dc7103ee269b180a8f8943 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Fri, 27 Mar 2026 22:42:40 +0530 Subject: [PATCH 70/84] pinctrl: qcom: Drop redundant intr_target_reg on modern SoCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On all Qualcomm TLMM generations from APQ8084 onwards, the interrupt target routing bits are located in the same register as the interrupt configuration bits (intr_cfg_reg). Only five older SoCs — APQ8064, IPQ8064, MDM9615, MSM8660 and MSM8960 — have a genuinely separate interrupt target routing register at a different offset (0x400 + 0x4 * id). Replace MSM_ACCESSOR(intr_target) with a custom accessor that falls back to intr_cfg_reg when intr_target_reg is zero. Apply the same fallback in the SCM path. Drop the now-redundant .intr_target_reg initializer from all SoC drivers where it duplicated intr_cfg_reg, keeping it only in the five drivers where it genuinely differs. Signed-off-by: Mukesh Ojha Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-apq8084.c | 2 -- drivers/pinctrl/qcom/pinctrl-eliza.c | 3 --- drivers/pinctrl/qcom/pinctrl-glymur.c | 3 --- drivers/pinctrl/qcom/pinctrl-ipq4019.c | 1 - drivers/pinctrl/qcom/pinctrl-ipq5018.c | 1 - drivers/pinctrl/qcom/pinctrl-ipq5332.c | 1 - drivers/pinctrl/qcom/pinctrl-ipq5424.c | 1 - drivers/pinctrl/qcom/pinctrl-ipq6018.c | 1 - drivers/pinctrl/qcom/pinctrl-ipq8074.c | 1 - drivers/pinctrl/qcom/pinctrl-ipq9574.c | 1 - drivers/pinctrl/qcom/pinctrl-kaanapali.c | 3 --- drivers/pinctrl/qcom/pinctrl-mdm9607.c | 2 -- drivers/pinctrl/qcom/pinctrl-milos.c | 3 --- drivers/pinctrl/qcom/pinctrl-msm.c | 20 ++++++++++++++++++-- drivers/pinctrl/qcom/pinctrl-msm.h | 6 +++++- drivers/pinctrl/qcom/pinctrl-msm8226.c | 2 -- drivers/pinctrl/qcom/pinctrl-msm8909.c | 2 -- drivers/pinctrl/qcom/pinctrl-msm8916.c | 2 -- drivers/pinctrl/qcom/pinctrl-msm8917.c | 2 -- drivers/pinctrl/qcom/pinctrl-msm8953.c | 2 -- drivers/pinctrl/qcom/pinctrl-msm8976.c | 2 -- drivers/pinctrl/qcom/pinctrl-msm8994.c | 2 -- drivers/pinctrl/qcom/pinctrl-msm8996.c | 2 -- drivers/pinctrl/qcom/pinctrl-msm8998.c | 3 --- drivers/pinctrl/qcom/pinctrl-msm8x74.c | 3 --- drivers/pinctrl/qcom/pinctrl-qcm2290.c | 3 --- drivers/pinctrl/qcom/pinctrl-qcs404.c | 2 -- drivers/pinctrl/qcom/pinctrl-qcs615.c | 3 --- drivers/pinctrl/qcom/pinctrl-qcs8300.c | 3 --- drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 1 - drivers/pinctrl/qcom/pinctrl-qdu1000.c | 3 --- drivers/pinctrl/qcom/pinctrl-sa8775p.c | 3 --- drivers/pinctrl/qcom/pinctrl-sar2130p.c | 2 -- drivers/pinctrl/qcom/pinctrl-sc7180.c | 3 --- drivers/pinctrl/qcom/pinctrl-sc7280.c | 3 --- drivers/pinctrl/qcom/pinctrl-sc8180x.c | 3 --- drivers/pinctrl/qcom/pinctrl-sc8280xp.c | 3 --- drivers/pinctrl/qcom/pinctrl-sdm660.c | 2 -- drivers/pinctrl/qcom/pinctrl-sdm670.c | 4 ---- drivers/pinctrl/qcom/pinctrl-sdm845.c | 3 --- drivers/pinctrl/qcom/pinctrl-sdx55.c | 2 -- drivers/pinctrl/qcom/pinctrl-sdx65.c | 3 --- drivers/pinctrl/qcom/pinctrl-sdx75.c | 2 -- drivers/pinctrl/qcom/pinctrl-sm4450.c | 3 --- drivers/pinctrl/qcom/pinctrl-sm6115.c | 3 --- drivers/pinctrl/qcom/pinctrl-sm6125.c | 3 --- drivers/pinctrl/qcom/pinctrl-sm6350.c | 3 --- drivers/pinctrl/qcom/pinctrl-sm6375.c | 3 --- drivers/pinctrl/qcom/pinctrl-sm7150.c | 3 --- drivers/pinctrl/qcom/pinctrl-sm8150.c | 3 --- drivers/pinctrl/qcom/pinctrl-sm8250.c | 3 --- drivers/pinctrl/qcom/pinctrl-sm8350.c | 3 --- drivers/pinctrl/qcom/pinctrl-sm8450.c | 3 --- drivers/pinctrl/qcom/pinctrl-sm8550.c | 3 --- drivers/pinctrl/qcom/pinctrl-sm8650.c | 3 --- drivers/pinctrl/qcom/pinctrl-sm8750.c | 3 --- drivers/pinctrl/qcom/pinctrl-x1e80100.c | 3 --- 57 files changed, 23 insertions(+), 138 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c b/drivers/pinctrl/qcom/pinctrl-apq8084.c index 27693cd64881..9fdbe6743512 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8084.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c @@ -343,7 +343,6 @@ static const unsigned int sdc2_data_pins[] = { 152 }; .io_reg = 0x1004 + 0x10 * id, \ .intr_cfg_reg = 0x1008 + 0x10 * id, \ .intr_status_reg = 0x100c + 0x10 * id, \ - .intr_target_reg = 0x1008 + 0x10 * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -370,7 +369,6 @@ static const unsigned int sdc2_data_pins[] = { 152 }; .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pinctrl-eliza.c index 19c706137f81..c1f756cbcdeb 100644 --- a/drivers/pinctrl/qcom/pinctrl-eliza.c +++ b/drivers/pinctrl/qcom/pinctrl-eliza.c @@ -34,7 +34,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -64,7 +63,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -89,7 +87,6 @@ .io_reg = io, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-glymur.c b/drivers/pinctrl/qcom/pinctrl-glymur.c index 2da3b513d31b..9838c7839923 100644 --- a/drivers/pinctrl/qcom/pinctrl-glymur.c +++ b/drivers/pinctrl/qcom/pinctrl-glymur.c @@ -21,7 +21,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -64,7 +63,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -89,7 +87,6 @@ .io_reg = io, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c index 6ede3149b6e1..c5f0decc3eb3 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -242,7 +242,6 @@ DECLARE_QCA_GPIO_PINS(99); .io_reg = 0x4 + 0x1000 * id, \ .intr_cfg_reg = 0x8 + 0x1000 * id, \ .intr_status_reg = 0xc + 0x1000 * id, \ - .intr_target_reg = 0x8 + 0x1000 * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5018.c b/drivers/pinctrl/qcom/pinctrl-ipq5018.c index cbf34854f882..0698c8f0110b 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq5018.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq5018.c @@ -32,7 +32,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5332.c b/drivers/pinctrl/qcom/pinctrl-ipq5332.c index 239cbe75f198..26a7a8c818f3 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq5332.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq5332.c @@ -32,7 +32,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5424.c b/drivers/pinctrl/qcom/pinctrl-ipq5424.c index 67b452a033d6..362ad88a5386 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq5424.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq5424.c @@ -33,7 +33,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ diff --git a/drivers/pinctrl/qcom/pinctrl-ipq6018.c b/drivers/pinctrl/qcom/pinctrl-ipq6018.c index be177fb0a92d..cc83f9362a85 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq6018.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq6018.c @@ -32,7 +32,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c b/drivers/pinctrl/qcom/pinctrl-ipq8074.c index e94de9083314..64ce8ea8f544 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq8074.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq8074.c @@ -32,7 +32,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9574.c b/drivers/pinctrl/qcom/pinctrl-ipq9574.c index 3ed093ea8eb9..09223eb166c9 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq9574.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq9574.c @@ -32,7 +32,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ diff --git a/drivers/pinctrl/qcom/pinctrl-kaanapali.c b/drivers/pinctrl/qcom/pinctrl-kaanapali.c index 364e6d997337..5cc45b9c55ab 100644 --- a/drivers/pinctrl/qcom/pinctrl-kaanapali.c +++ b/drivers/pinctrl/qcom/pinctrl-kaanapali.c @@ -34,7 +34,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -64,7 +63,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -89,7 +87,6 @@ .io_reg = io, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9607.c b/drivers/pinctrl/qcom/pinctrl-mdm9607.c index cef330547ce7..5794b0a11010 100644 --- a/drivers/pinctrl/qcom/pinctrl-mdm9607.c +++ b/drivers/pinctrl/qcom/pinctrl-mdm9607.c @@ -225,7 +225,6 @@ static const unsigned int qdsd_data3_pins[] = { 91 }; .io_reg = 0x4 + 0x1000 * id, \ .intr_cfg_reg = 0x8 + 0x1000 * id, \ .intr_status_reg = 0xc + 0x1000 * id, \ - .intr_target_reg = 0x8 + 0x1000 * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -251,7 +250,6 @@ static const unsigned int qdsd_data3_pins[] = { 91 }; .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ diff --git a/drivers/pinctrl/qcom/pinctrl-milos.c b/drivers/pinctrl/qcom/pinctrl-milos.c index 19abd5233a2c..74b5253257af 100644 --- a/drivers/pinctrl/qcom/pinctrl-milos.c +++ b/drivers/pinctrl/qcom/pinctrl-milos.c @@ -36,7 +36,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -67,7 +66,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -92,7 +90,6 @@ .io_reg = io, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index e99871b90ab9..45b3a2763eb8 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -98,7 +98,22 @@ MSM_ACCESSOR(ctl) MSM_ACCESSOR(io) MSM_ACCESSOR(intr_cfg) MSM_ACCESSOR(intr_status) -MSM_ACCESSOR(intr_target) + +static u32 msm_readl_intr_target(struct msm_pinctrl *pctrl, + const struct msm_pingroup *g) +{ + u32 reg = g->intr_target_reg ? g->intr_target_reg : g->intr_cfg_reg; + + return readl(pctrl->regs[g->tile] + reg); +} + +static void msm_writel_intr_target(u32 val, struct msm_pinctrl *pctrl, + const struct msm_pingroup *g) +{ + u32 reg = g->intr_target_reg ? g->intr_target_reg : g->intr_cfg_reg; + + writel(val, pctrl->regs[g->tile] + reg); +} static void msm_ack_intr_status(struct msm_pinctrl *pctrl, const struct msm_pingroup *g) @@ -1078,7 +1093,8 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) intr_target_mask = GENMASK(g->intr_target_width - 1, 0); if (pctrl->intr_target_use_scm) { - u32 addr = pctrl->phys_base[0] + g->intr_target_reg; + u32 reg = g->intr_target_reg ? g->intr_target_reg : g->intr_cfg_reg; + u32 addr = pctrl->phys_base[0] + reg; int ret; qcom_scm_io_readl(addr, &val); diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 4625fa5320a9..a4af279f748a 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -52,7 +52,11 @@ struct pinctrl_pin_desc; * @intr_cfg_reg: Offset of the register holding interrupt configuration bits. * @intr_status_reg: Offset of the register holding the status bits for this group. * @intr_target_reg: Offset of the register specifying routing of the interrupts - * from this group. + * from this group. On most SoCs this register is the same as + * @intr_cfg_reg; leaving this field as zero causes the driver + * to fall back to @intr_cfg_reg automatically. Only set this + * explicitly on older SoCs where the interrupt target routing + * lives in a separate register (e.g. APQ8064, MSM8960). * @mux_bit: Offset in @ctl_reg for the pinmux function selection. * @pull_bit: Offset in @ctl_reg for the bias configuration. * @drv_bit: Offset in @ctl_reg for the drive strength configuration. diff --git a/drivers/pinctrl/qcom/pinctrl-msm8226.c b/drivers/pinctrl/qcom/pinctrl-msm8226.c index a81aa092ef12..d27b7599ea83 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8226.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8226.c @@ -282,7 +282,6 @@ static const unsigned int sdc2_data_pins[] = { 122 }; .io_reg = 0x1004 + 0x10 * id, \ .intr_cfg_reg = 0x1008 + 0x10 * id, \ .intr_status_reg = 0x100c + 0x10 * id, \ - .intr_target_reg = 0x1008 + 0x10 * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -308,7 +307,6 @@ static const unsigned int sdc2_data_pins[] = { 122 }; .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ diff --git a/drivers/pinctrl/qcom/pinctrl-msm8909.c b/drivers/pinctrl/qcom/pinctrl-msm8909.c index 544a52fb8f3d..8fa922d89101 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8909.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8909.c @@ -33,7 +33,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -59,7 +58,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ diff --git a/drivers/pinctrl/qcom/pinctrl-msm8916.c b/drivers/pinctrl/qcom/pinctrl-msm8916.c index b1b6934bb4b6..709c5d1d4d0a 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8916.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c @@ -307,7 +307,6 @@ static const unsigned int qdsd_data3_pins[] = { 133 }; .io_reg = 0x4 + 0x1000 * id, \ .intr_cfg_reg = 0x8 + 0x1000 * id, \ .intr_status_reg = 0xc + 0x1000 * id, \ - .intr_target_reg = 0x8 + 0x1000 * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -333,7 +332,6 @@ static const unsigned int qdsd_data3_pins[] = { 133 }; .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ diff --git a/drivers/pinctrl/qcom/pinctrl-msm8917.c b/drivers/pinctrl/qcom/pinctrl-msm8917.c index f23d92d6615b..d1ede4891703 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8917.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8917.c @@ -333,7 +333,6 @@ static const unsigned int qdsd_data3_pins[] = { 146 }; .io_reg = 0x4 + 0x1000 * id, \ .intr_cfg_reg = 0x8 + 0x1000 * id, \ .intr_status_reg = 0xc + 0x1000 * id, \ - .intr_target_reg = 0x8 + 0x1000 * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -359,7 +358,6 @@ static const unsigned int qdsd_data3_pins[] = { 146 }; .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ diff --git a/drivers/pinctrl/qcom/pinctrl-msm8953.c b/drivers/pinctrl/qcom/pinctrl-msm8953.c index 67db062fdf56..02ea89f5feaa 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8953.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8953.c @@ -29,7 +29,6 @@ .io_reg = 0x4 + 0x1000 * id, \ .intr_cfg_reg = 0x8 + 0x1000 * id, \ .intr_status_reg = 0xc + 0x1000 * id, \ - .intr_target_reg = 0x8 + 0x1000 * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -55,7 +54,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ diff --git a/drivers/pinctrl/qcom/pinctrl-msm8976.c b/drivers/pinctrl/qcom/pinctrl-msm8976.c index 345539b9e696..906a90778b97 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8976.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8976.c @@ -35,7 +35,6 @@ .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ - .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -61,7 +60,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ diff --git a/drivers/pinctrl/qcom/pinctrl-msm8994.c b/drivers/pinctrl/qcom/pinctrl-msm8994.c index 94e042d1f4b2..ecbe6b91d1da 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8994.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8994.c @@ -33,7 +33,6 @@ .io_reg = 0x1004 + 0x10 * id, \ .intr_cfg_reg = 0x1008 + 0x10 * id, \ .intr_status_reg = 0x100c + 0x10 * id, \ - .intr_target_reg = 0x1008 + 0x10 * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -59,7 +58,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ diff --git a/drivers/pinctrl/qcom/pinctrl-msm8996.c b/drivers/pinctrl/qcom/pinctrl-msm8996.c index e5b55693d023..73b07a10a957 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8996.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8996.c @@ -33,7 +33,6 @@ .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ - .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -59,7 +58,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ diff --git a/drivers/pinctrl/qcom/pinctrl-msm8998.c b/drivers/pinctrl/qcom/pinctrl-msm8998.c index b727593af34a..dcf11b79e562 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8998.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8998.c @@ -35,7 +35,6 @@ .io_reg = base + 0x4 + 0x1000 * id, \ .intr_cfg_reg = base + 0x8 + 0x1000 * id, \ .intr_status_reg = base + 0xc + 0x1000 * id, \ - .intr_target_reg = base + 0x8 + 0x1000 * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -61,7 +60,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -86,7 +84,6 @@ .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c index 202bec003e96..ff432ec5815a 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c @@ -344,7 +344,6 @@ static const unsigned int hsic_data_pins[] = { 153 }; .io_reg = 0x1004 + 0x10 * id, \ .intr_cfg_reg = 0x1008 + 0x10 * id, \ .intr_status_reg = 0x100c + 0x10 * id, \ - .intr_target_reg = 0x1008 + 0x10 * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -370,7 +369,6 @@ static const unsigned int hsic_data_pins[] = { 153 }; .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -401,7 +399,6 @@ static const unsigned int hsic_data_pins[] = { 153 }; .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = 25, \ .pull_bit = -1, \ .drv_bit = -1, \ diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c index 38200957451e..3b28ac498885 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcm2290.c +++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c @@ -33,7 +33,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -61,7 +60,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -86,7 +84,6 @@ .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c index 0b8db2c7e58a..1048a7093b2e 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -43,7 +43,6 @@ enum { .io_reg = 0x1000 * id + 0x4, \ .intr_cfg_reg = 0x1000 * id + 0x8, \ .intr_status_reg = 0x1000 * id + 0xc, \ - .intr_target_reg = 0x1000 * id + 0x8, \ .tile = _tile, \ .mux_bit = 2, \ .pull_bit = 0, \ @@ -70,7 +69,6 @@ enum { .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .tile = SOUTH, \ .mux_bit = -1, \ .pull_bit = pull, \ diff --git a/drivers/pinctrl/qcom/pinctrl-qcs615.c b/drivers/pinctrl/qcom/pinctrl-qcs615.c index 4dfa820d4e77..be1996fe98cf 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs615.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs615.c @@ -43,7 +43,6 @@ static const char * const qcs615_tiles[] = { .io_reg = 0x1000 * id + 0x4, \ .intr_cfg_reg = 0x1000 * id + 0x8, \ .intr_status_reg = 0x1000 * id + 0xc, \ - .intr_target_reg = 0x1000 * id + 0x8, \ .tile = _tile, \ .mux_bit = 2, \ .pull_bit = 0, \ @@ -70,7 +69,6 @@ static const char * const qcs615_tiles[] = { .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .tile = _tile, \ .mux_bit = -1, \ .pull_bit = pull, \ @@ -96,7 +94,6 @@ static const char * const qcs615_tiles[] = { .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .tile = WEST, \ .mux_bit = -1, \ .pull_bit = 3, \ diff --git a/drivers/pinctrl/qcom/pinctrl-qcs8300.c b/drivers/pinctrl/qcom/pinctrl-qcs8300.c index f1af1a620684..852cd36df6d5 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs8300.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs8300.c @@ -34,7 +34,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -62,7 +61,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -87,7 +85,6 @@ .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c index 9ecc4d40e4dc..3b9edcf8780b 100644 --- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c +++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c @@ -106,7 +106,6 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev) groups[gpio].io_reg = 0x04 + 0x10000 * gpio; groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio; groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio; - groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio; groups[gpio].mux_bit = 2; groups[gpio].pull_bit = 0; diff --git a/drivers/pinctrl/qcom/pinctrl-qdu1000.c b/drivers/pinctrl/qcom/pinctrl-qdu1000.c index 7c535698a780..5125df7eb127 100644 --- a/drivers/pinctrl/qcom/pinctrl-qdu1000.c +++ b/drivers/pinctrl/qcom/pinctrl-qdu1000.c @@ -35,7 +35,6 @@ .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ - .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -61,7 +60,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -86,7 +84,6 @@ .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c b/drivers/pinctrl/qcom/pinctrl-sa8775p.c index 53f28b9c49ba..e9a510d3583f 100644 --- a/drivers/pinctrl/qcom/pinctrl-sa8775p.c +++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c @@ -34,7 +34,6 @@ .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ - .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -63,7 +62,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -88,7 +86,6 @@ .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sar2130p.c b/drivers/pinctrl/qcom/pinctrl-sar2130p.c index 4a53f4ee2041..1d1b5de4eefd 100644 --- a/drivers/pinctrl/qcom/pinctrl-sar2130p.c +++ b/drivers/pinctrl/qcom/pinctrl-sar2130p.c @@ -34,7 +34,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -62,7 +61,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sc7180.c b/drivers/pinctrl/qcom/pinctrl-sc7180.c index 3eae51472b13..01cfcb416f33 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7180.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7180.c @@ -41,7 +41,6 @@ enum { .io_reg = 0x1000 * id + 0x4, \ .intr_cfg_reg = 0x1000 * id + 0x8, \ .intr_status_reg = 0x1000 * id + 0xc, \ - .intr_target_reg = 0x1000 * id + 0x8, \ .tile = _tile, \ .mux_bit = 2, \ .pull_bit = 0, \ @@ -68,7 +67,6 @@ enum { .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .tile = SOUTH, \ .mux_bit = -1, \ .pull_bit = pull, \ @@ -94,7 +92,6 @@ enum { .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .tile = SOUTH, \ .mux_bit = -1, \ .pull_bit = 3, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/pinctrl-sc7280.c index 44e09608aad0..f22fd56efd89 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c @@ -31,7 +31,6 @@ .io_reg = 0x1000 * id + 0x4, \ .intr_cfg_reg = 0x1000 * id + 0x8, \ .intr_status_reg = 0x1000 * id + 0xc, \ - .intr_target_reg = 0x1000 * id + 0x8, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -59,7 +58,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -84,7 +82,6 @@ .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sc8180x.c b/drivers/pinctrl/qcom/pinctrl-sc8180x.c index d9f9e3dd9dd1..062cb913e5ee 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8180x.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8180x.c @@ -60,7 +60,6 @@ static const struct tile_info sc8180x_tile_info[] = { .io_reg = REG_SIZE * id + 0x4 + offset, \ .intr_cfg_reg = REG_SIZE * id + 0x8 + offset, \ .intr_status_reg = REG_SIZE * id + 0xc + offset,\ - .intr_target_reg = REG_SIZE * id + 0x8 + offset,\ .tile = _tile, \ .mux_bit = 2, \ .pull_bit = 0, \ @@ -90,7 +89,6 @@ static const struct tile_info sc8180x_tile_info[] = { .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .tile = EAST, \ .mux_bit = -1, \ .pull_bit = pull, \ @@ -116,7 +114,6 @@ static const struct tile_info sc8180x_tile_info[] = { .io_reg = 0xb6004, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .tile = SOUTH, \ .mux_bit = -1, \ .pull_bit = 3, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp.c index cf8297e8b8f8..4056b9fa32f8 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8280xp.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp.c @@ -31,7 +31,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -59,7 +58,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -84,7 +82,6 @@ .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660.c b/drivers/pinctrl/qcom/pinctrl-sdm660.c index 687d986de75c..ab0368653d30 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm660.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c @@ -46,7 +46,6 @@ enum { .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .tile = _tile, \ .mux_bit = 2, \ .pull_bit = 0, \ @@ -73,7 +72,6 @@ enum { .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .tile = NORTH, \ .mux_bit = -1, \ .pull_bit = pull, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sdm670.c b/drivers/pinctrl/qcom/pinctrl-sdm670.c index 486b72edf7b4..533b87c39cd5 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm670.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm670.c @@ -37,7 +37,6 @@ .io_reg = base + 0x4 + REG_SIZE * id, \ .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ .intr_status_reg = base + 0xc + REG_SIZE * id, \ - .intr_target_reg = base + 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -67,7 +66,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = -1, \ .drv_bit = -1, \ @@ -92,7 +90,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -117,7 +114,6 @@ .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 4cf8575797a0..b5ed2311b70e 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -37,7 +37,6 @@ .io_reg = base + 0x4 + REG_SIZE * id, \ .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ .intr_status_reg = base + 0xc + REG_SIZE * id, \ - .intr_target_reg = base + 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -63,7 +62,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -88,7 +86,6 @@ .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sdx55.c b/drivers/pinctrl/qcom/pinctrl-sdx55.c index 79a7010b73f1..3e87f5927924 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdx55.c +++ b/drivers/pinctrl/qcom/pinctrl-sdx55.c @@ -33,7 +33,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -59,7 +58,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sdx65.c b/drivers/pinctrl/qcom/pinctrl-sdx65.c index cc8a99a6a91e..4e787341b2a2 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdx65.c +++ b/drivers/pinctrl/qcom/pinctrl-sdx65.c @@ -33,7 +33,6 @@ .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ - .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -59,7 +58,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -84,7 +82,6 @@ .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sdx75.c b/drivers/pinctrl/qcom/pinctrl-sdx75.c index 4078d83d818c..9a7e359dbd23 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdx75.c +++ b/drivers/pinctrl/qcom/pinctrl-sdx75.c @@ -19,7 +19,6 @@ .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ - .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -60,7 +59,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sm4450.c b/drivers/pinctrl/qcom/pinctrl-sm4450.c index d51e271e3361..83650f173b01 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm4450.c +++ b/drivers/pinctrl/qcom/pinctrl-sm4450.c @@ -33,7 +33,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -61,7 +60,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -86,7 +84,6 @@ .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115.c b/drivers/pinctrl/qcom/pinctrl-sm6115.c index 06700685ea2a..234451fbf47b 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6115.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6115.c @@ -43,7 +43,6 @@ enum { .io_reg = 0x4 + 0x1000 * id, \ .intr_cfg_reg = 0x8 + 0x1000 * id, \ .intr_status_reg = 0xc + 0x1000 * id, \ - .intr_target_reg = 0x8 + 0x1000 * id, \ .tile = _tile, \ .mux_bit = 2, \ .pull_bit = 0, \ @@ -70,7 +69,6 @@ enum { .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .tile = _tile, \ .mux_bit = -1, \ .pull_bit = pull, \ @@ -96,7 +94,6 @@ enum { .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .tile = WEST, \ .mux_bit = -1, \ .pull_bit = 3, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sm6125.c b/drivers/pinctrl/qcom/pinctrl-sm6125.c index 5d3d1e402345..2cf9136860fc 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6125.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6125.c @@ -40,7 +40,6 @@ enum { .io_reg = 0x4 + 0x1000 * id, \ .intr_cfg_reg = 0x8 + 0x1000 * id, \ .intr_status_reg = 0xc + 0x1000 * id, \ - .intr_target_reg = 0x8 + 0x1000 * id, \ .tile = _tile, \ .mux_bit = 2, \ .pull_bit = 0, \ @@ -67,7 +66,6 @@ enum { .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .tile = _tile, \ .mux_bit = -1, \ .pull_bit = pull, \ @@ -93,7 +91,6 @@ enum { .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .tile = WEST, \ .mux_bit = -1, \ .pull_bit = 3, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350.c b/drivers/pinctrl/qcom/pinctrl-sm6350.c index 220fb582cac9..eb8cd4aa8a97 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6350.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6350.c @@ -33,7 +33,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -59,7 +58,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -84,7 +82,6 @@ .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sm6375.c b/drivers/pinctrl/qcom/pinctrl-sm6375.c index 08b8ef6efaf0..d4547dd9f21f 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6375.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6375.c @@ -34,7 +34,6 @@ .io_reg = REG_SIZE * id + 0x4, \ .intr_cfg_reg = REG_SIZE * id + 0x8, \ .intr_status_reg = REG_SIZE * id + 0xc, \ - .intr_target_reg = REG_SIZE * id + 0x8, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -62,7 +61,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -87,7 +85,6 @@ .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sm7150.c b/drivers/pinctrl/qcom/pinctrl-sm7150.c index 78dd8153a4d4..a01437c37525 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm7150.c +++ b/drivers/pinctrl/qcom/pinctrl-sm7150.c @@ -47,7 +47,6 @@ enum { .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .tile = _tile, \ .mux_bit = 2, \ .pull_bit = 0, \ @@ -74,7 +73,6 @@ enum { .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .tile = _tile, \ .mux_bit = -1, \ .pull_bit = pull, \ @@ -100,7 +98,6 @@ enum { .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .tile = WEST, \ .mux_bit = -1, \ .pull_bit = 3, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c index ad861cd66958..0767261f5149 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8150.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c @@ -43,7 +43,6 @@ enum { .io_reg = 0x1000 * id + 0x4, \ .intr_cfg_reg = 0x1000 * id + 0x8, \ .intr_status_reg = 0x1000 * id + 0xc, \ - .intr_target_reg = 0x1000 * id + 0x8, \ .tile = _tile, \ .mux_bit = 2, \ .pull_bit = 0, \ @@ -70,7 +69,6 @@ enum { .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .tile = NORTH, \ .mux_bit = -1, \ .pull_bit = pull, \ @@ -96,7 +94,6 @@ enum { .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .tile = SOUTH, \ .mux_bit = -1, \ .pull_bit = 3, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c index f05361f3100d..f73f3b052de4 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8250.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c @@ -44,7 +44,6 @@ enum { .io_reg = REG_SIZE * id + 0x4, \ .intr_cfg_reg = REG_SIZE * id + 0x8, \ .intr_status_reg = REG_SIZE * id + 0xc, \ - .intr_target_reg = REG_SIZE * id + 0x8, \ .tile = _tile, \ .mux_bit = 2, \ .pull_bit = 0, \ @@ -73,7 +72,6 @@ enum { .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .tile = NORTH, \ .mux_bit = -1, \ .pull_bit = pull, \ @@ -99,7 +97,6 @@ enum { .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .tile = SOUTH, \ .mux_bit = -1, \ .pull_bit = 3, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350.c b/drivers/pinctrl/qcom/pinctrl-sm8350.c index 99949b552021..377ddfc77e4f 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8350.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8350.c @@ -34,7 +34,6 @@ .io_reg = REG_SIZE * id + 0x4, \ .intr_cfg_reg = REG_SIZE * id + 0x8, \ .intr_status_reg = REG_SIZE * id + 0xc, \ - .intr_target_reg = REG_SIZE * id + 0x8, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -60,7 +59,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -85,7 +83,6 @@ .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450.c b/drivers/pinctrl/qcom/pinctrl-sm8450.c index 9889fc5dc2cd..a1d84074ea49 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450.c @@ -34,7 +34,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -62,7 +61,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -87,7 +85,6 @@ .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c index 10a62031fdfd..cc8fbf4d5e84 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c @@ -35,7 +35,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -64,7 +63,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -89,7 +87,6 @@ .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c index e2ae03800206..ab41292e3b4e 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c @@ -36,7 +36,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -67,7 +66,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -92,7 +90,6 @@ .io_reg = io, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-sm8750.c b/drivers/pinctrl/qcom/pinctrl-sm8750.c index 6f92f176edd4..4cfe73f30fac 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8750.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8750.c @@ -35,7 +35,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -65,7 +64,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -90,7 +88,6 @@ .io_reg = io, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ diff --git a/drivers/pinctrl/qcom/pinctrl-x1e80100.c b/drivers/pinctrl/qcom/pinctrl-x1e80100.c index bb36f40b19fa..a9fe75fc45e5 100644 --- a/drivers/pinctrl/qcom/pinctrl-x1e80100.c +++ b/drivers/pinctrl/qcom/pinctrl-x1e80100.c @@ -33,7 +33,6 @@ .io_reg = 0x4 + REG_SIZE * id, \ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ .intr_status_reg = 0xc + REG_SIZE * id, \ - .intr_target_reg = 0x8 + REG_SIZE * id, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -62,7 +61,6 @@ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -87,7 +85,6 @@ .io_reg = offset + 0x4, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ - .intr_target_reg = 0, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ From c0dd33f0e9ab253ac45a1df74f9933f399e9115f Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Mon, 30 Mar 2026 10:21:04 +0530 Subject: [PATCH 71/84] dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl Add device tree bindings for IPQ5210 TLMM block. Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,ipq5210-tlmm.yaml | 123 ++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml new file mode 100644 index 000000000000..12c5e76235a3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5210-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ5210 TLMM pin controller + +maintainers: + - Bjorn Andersson + - Kathiravan Thirumoorthy + +description: + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5210 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq5210-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 27 + + gpio-line-names: + maxItems: 54 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq5210-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq5210-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq5210-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char_start, atest_char_status0, atest_char_status1, + atest_char_status2, atest_char_status3, atest_tic_en, audio_pri, + audio_pri_mclk_out0, audio_pri_mclk_in0, audio_pri_mclk_out1, + audio_pri_mclk_in1, audio_pri_mclk_out2, audio_pri_mclk_in2, + audio_pri_mclk_out3, audio_pri_mclk_in3, audio_sec, + audio_sec_mclk_out0, audio_sec_mclk_in0, audio_sec_mclk_out1, + audio_sec_mclk_in1, audio_sec_mclk_out2, audio_sec_mclk_in2, + audio_sec_mclk_out3, audio_sec_mclk_in3, core_voltage_0, + cri_trng0, cri_trng1, cri_trng2, cri_trng3, dbg_out_clk, dg_out, + gcc_plltest_bypassnl, gcc_plltest_resetn, gcc_tlmm, gpio, led0, + led1, led2, mdc_mst, mdc_slv0, mdc_slv1, mdc_slv2, mdio_mst, + mdio_slv0, mdio_slv1, mdio_slv2, mux_tod_out, pcie0_clk_req_n, + pcie0_wake, pcie1_clk_req_n, pcie1_wake, pll_test, + pon_active_led, pon_mux_sel, pon_rx, pon_rx_los, pon_tx, + pon_tx_burst, pon_tx_dis, pon_tx_fault, pon_tx_sd, gpn_rx_los, + gpn_tx_burst, gpn_tx_dis, gpn_tx_fault, gpn_tx_sd, pps, pwm0, + pwm1, pwm2, pwm3, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, + qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, + qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, + qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a, + qdss_tracedata_a, qrng_rosc0, qrng_rosc1, qrng_rosc2, + qspi_data, qspi_clk, qspi_cs_n, qup_se0, qup_se1, qup_se2, + qup_se3, qup_se4, qup_se5, qup_se5_l1, resout, rx_los0, rx_los1, + rx_los2, sdc_clk, sdc_cmd, sdc_data, tsens_max ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5210-tlmm"; + reg = <0x01000000 0x300000>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <&tlmm 0 0 54>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <0x2>; + + qup-uart1-default-state { + pins = "gpio38", "gpio39"; + function = "qup_se1"; + drive-strength = <6>; + bias-pull-down; + }; + }; From a549fe22376f5c312d9f61965184265425c8fd28 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Mon, 30 Mar 2026 10:21:05 +0530 Subject: [PATCH 72/84] pinctrl: qcom: Introduce IPQ5210 TLMM driver Qualcomm's IPQ5210 SoC comes with a TLMM block, like all other platforms, so add a driver for it. Reviewed-by: Konrad Dybcio Reviewed-by: Bjorn Andersson Signed-off-by: Kathiravan Thirumoorthy [linusw@kernel.org: Dropped intr_target_reg] Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig.msm | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-ipq5210.c | 897 +++++++++++++++++++++++++ 3 files changed, 906 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5210.c diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm index 6df6159fa5f8..17416dce8e70 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -58,6 +58,14 @@ config PINCTRL_IPQ8064 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm IPQ8064 platform. +config PINCTRL_IPQ5210 + tristate "Qualcomm Technologies Inc IPQ5210 pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc IPQ5210 platform. + config PINCTRL_IPQ5332 tristate "Qualcomm Technologies Inc IPQ5332 pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index a8fd12f90d6e..84ff95ff246a 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_GLYMUR) += pinctrl-glymur.o obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o +obj-$(CONFIG_PINCTRL_IPQ5210) += pinctrl-ipq5210.o obj-$(CONFIG_PINCTRL_IPQ5332) += pinctrl-ipq5332.o obj-$(CONFIG_PINCTRL_IPQ5424) += pinctrl-ipq5424.o obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5210.c b/drivers/pinctrl/qcom/pinctrl-ipq5210.c new file mode 100644 index 000000000000..827a4ad07a6b --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq5210.c @@ -0,0 +1,897 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + }, \ + .nfuncs = 10, \ + } + +static const struct pinctrl_pin_desc ipq5210_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); + +enum ipq5210_functions { + msm_mux_atest_char_start, + msm_mux_atest_char_status0, + msm_mux_atest_char_status1, + msm_mux_atest_char_status2, + msm_mux_atest_char_status3, + msm_mux_atest_tic_en, + msm_mux_audio_pri, + msm_mux_audio_pri_mclk_out0, + msm_mux_audio_pri_mclk_in0, + msm_mux_audio_pri_mclk_out1, + msm_mux_audio_pri_mclk_in1, + msm_mux_audio_pri_mclk_out2, + msm_mux_audio_pri_mclk_in2, + msm_mux_audio_pri_mclk_out3, + msm_mux_audio_pri_mclk_in3, + msm_mux_audio_sec, + msm_mux_audio_sec_mclk_out0, + msm_mux_audio_sec_mclk_in0, + msm_mux_audio_sec_mclk_out1, + msm_mux_audio_sec_mclk_in1, + msm_mux_audio_sec_mclk_out2, + msm_mux_audio_sec_mclk_in2, + msm_mux_audio_sec_mclk_out3, + msm_mux_audio_sec_mclk_in3, + msm_mux_core_voltage_0, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_cri_trng2, + msm_mux_cri_trng3, + msm_mux_dbg_out_clk, + msm_mux_dg_out, + msm_mux_gcc_plltest_bypassnl, + msm_mux_gcc_plltest_resetn, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_led0, + msm_mux_led1, + msm_mux_led2, + msm_mux_mdc_mst, + msm_mux_mdc_slv0, + msm_mux_mdc_slv1, + msm_mux_mdc_slv2, + msm_mux_mdio_mst, + msm_mux_mdio_slv0, + msm_mux_mdio_slv1, + msm_mux_mdio_slv2, + msm_mux_mux_tod_out, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie0_wake, + msm_mux_pcie1_clk_req_n, + msm_mux_pcie1_wake, + msm_mux_pll_test, + msm_mux_pon_active_led, + msm_mux_pon_mux_sel, + msm_mux_pon_rx, + msm_mux_pon_rx_los, + msm_mux_pon_tx, + msm_mux_pon_tx_burst, + msm_mux_pon_tx_dis, + msm_mux_pon_tx_fault, + msm_mux_pon_tx_sd, + msm_mux_gpn_rx_los, + msm_mux_gpn_tx_burst, + msm_mux_gpn_tx_dis, + msm_mux_gpn_tx_fault, + msm_mux_gpn_tx_sd, + msm_mux_pps, + msm_mux_pwm0, + msm_mux_pwm1, + msm_mux_pwm2, + msm_mux_pwm3, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracedata_a, + msm_mux_qrng_rosc0, + msm_mux_qrng_rosc1, + msm_mux_qrng_rosc2, + msm_mux_qspi_data, + msm_mux_qspi_clk, + msm_mux_qspi_cs_n, + msm_mux_qup_se0, + msm_mux_qup_se1, + msm_mux_qup_se2, + msm_mux_qup_se3, + msm_mux_qup_se4, + msm_mux_qup_se5, + msm_mux_qup_se5_l1, + msm_mux_resout, + msm_mux_rx_los0, + msm_mux_rx_los1, + msm_mux_rx_los2, + msm_mux_sdc_clk, + msm_mux_sdc_cmd, + msm_mux_sdc_data, + msm_mux_tsens_max, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", + "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", + "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", + "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", + "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", +}; + +static const char *const atest_char_start_groups[] = { + "gpio46", +}; + +static const char *const atest_char_status0_groups[] = { + "gpio34", +}; + +static const char *const atest_char_status1_groups[] = { + "gpio35", +}; + +static const char *const atest_char_status2_groups[] = { + "gpio36", +}; + +static const char *const atest_char_status3_groups[] = { + "gpio37", +}; + +static const char *const atest_tic_en_groups[] = { + "gpio42", +}; + +static const char *const audio_pri_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37", +}; + +static const char *const audio_pri_mclk_out0_groups[] = { + "gpio12", +}; + +static const char *const audio_pri_mclk_in0_groups[] = { + "gpio12", +}; + +static const char *const audio_pri_mclk_out1_groups[] = { + "gpio19", +}; + +static const char *const audio_pri_mclk_in1_groups[] = { + "gpio19", +}; + +static const char *const audio_pri_mclk_out2_groups[] = { + "gpio8", +}; + +static const char *const audio_pri_mclk_in2_groups[] = { + "gpio8", +}; + +static const char *const audio_pri_mclk_out3_groups[] = { + "gpio13", +}; + +static const char *const audio_pri_mclk_in3_groups[] = { + "gpio13", +}; + +static const char *const audio_sec_mclk_out0_groups[] = { + "gpio17", +}; + +static const char *const audio_sec_mclk_in0_groups[] = { + "gpio17", +}; + +static const char *const audio_sec_mclk_out1_groups[] = { + "gpio16", +}; + +static const char *const audio_sec_mclk_in1_groups[] = { + "gpio16", +}; + +static const char *const audio_sec_mclk_out2_groups[] = { + "gpio49", +}; + +static const char *const audio_sec_mclk_in2_groups[] = { + "gpio49", +}; + +static const char *const audio_sec_mclk_out3_groups[] = { + "gpio50", +}; + +static const char *const audio_sec_mclk_in3_groups[] = { + "gpio50", +}; + +static const char *const audio_sec_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", +}; + +static const char *const core_voltage_0_groups[] = { + "gpio22", +}; + +static const char *const cri_trng0_groups[] = { + "gpio6", +}; + +static const char *const cri_trng1_groups[] = { + "gpio7", +}; + +static const char *const cri_trng2_groups[] = { + "gpio8", +}; + +static const char *const cri_trng3_groups[] = { + "gpio9", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio23", +}; + +static const char *const dg_out_groups[] = { + "gpio46", +}; + +static const char *const gcc_plltest_bypassnl_groups[] = { + "gpio38", +}; + +static const char *const gcc_plltest_resetn_groups[] = { + "gpio40", +}; + +static const char *const gcc_tlmm_groups[] = { + "gpio39", +}; + +static const char *const led0_groups[] = { + "gpio6", "gpio23", "gpio39", +}; + +static const char *const led1_groups[] = { + "gpio7", "gpio27", "gpio39", +}; + +static const char *const led2_groups[] = { + "gpio9", "gpio26", "gpio38", +}; + +static const char *const mdc_mst_groups[] = { + "gpio26", +}; + +static const char *const mdc_slv0_groups[] = { + "gpio31", +}; + +static const char *const mdc_slv1_groups[] = { + "gpio20", +}; + +static const char *const mdc_slv2_groups[] = { + "gpio47", +}; + +static const char *const mdio_mst_groups[] = { + "gpio27", +}; + +static const char *const mdio_slv0_groups[] = { + "gpio33", +}; + +static const char *const mdio_slv1_groups[] = { + "gpio21", +}; + +static const char *const mdio_slv2_groups[] = { + "gpio49", +}; + +static const char *const mux_tod_out_groups[] = { + "gpio19", +}; + +static const char *const pcie0_clk_req_n_groups[] = { + "gpio31", +}; + +static const char *const pcie0_wake_groups[] = { + "gpio33", +}; + +static const char *const pcie1_clk_req_n_groups[] = { + "gpio28", +}; + +static const char *const pcie1_wake_groups[] = { + "gpio30", +}; + +static const char *const pll_test_groups[] = { + "gpio18", +}; + +static const char *const pon_active_led_groups[] = { + "gpio11", +}; + +static const char *const pon_mux_sel_groups[] = { + "gpio45", +}; + +static const char *const pon_rx_groups[] = { + "gpio48", +}; + +static const char *const pon_rx_los_groups[] = { + "gpio10", +}; + +static const char *const pon_tx_groups[] = { + "gpio15", +}; + +static const char *const pon_tx_burst_groups[] = { + "gpio14", +}; + +static const char *const pon_tx_dis_groups[] = { + "gpio12", +}; + +static const char *const pon_tx_fault_groups[] = { + "gpio17", +}; + +static const char *const pon_tx_sd_groups[] = { + "gpio16", +}; + +static const char *const gpn_rx_los_groups[] = { + "gpio47", +}; + +static const char *const gpn_tx_burst_groups[] = { + "gpio51", +}; + +static const char *const gpn_tx_dis_groups[] = { + "gpio13", +}; + +static const char *const gpn_tx_fault_groups[] = { + "gpio49", +}; + +static const char *const gpn_tx_sd_groups[] = { + "gpio50", +}; + +static const char *const pps_groups[] = { + "gpio18", +}; + +static const char *const pwm0_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", +}; + +static const char *const pwm1_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", +}; + +static const char *const pwm2_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const pwm3_groups[] = { + "gpio22", +}; + +static const char *const qdss_cti_trig_in_a0_groups[] = { + "gpio30", +}; + +static const char *const qdss_cti_trig_in_a1_groups[] = { + "gpio33", +}; + +static const char *const qdss_cti_trig_in_b0_groups[] = { + "gpio34", +}; + +static const char *const qdss_cti_trig_in_b1_groups[] = { + "gpio37", +}; + +static const char *const qdss_cti_trig_out_a0_groups[] = { + "gpio28", +}; + +static const char *const qdss_cti_trig_out_a1_groups[] = { + "gpio31", +}; + +static const char *const qdss_cti_trig_out_b0_groups[] = { + "gpio16", +}; + +static const char *const qdss_cti_trig_out_b1_groups[] = { + "gpio35", +}; + +static const char *const qdss_traceclk_a_groups[] = { + "gpio23", +}; + +static const char *const qdss_tracectl_a_groups[] = { + "gpio26", +}; + +static const char *const qdss_tracedata_a_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio20", "gpio21", + "gpio38", "gpio39", "gpio40", "gpio41", +}; + +static const char *const qrng_rosc0_groups[] = { + "gpio12", +}; + +static const char *const qrng_rosc1_groups[] = { + "gpio13", +}; + +static const char *const qrng_rosc2_groups[] = { + "gpio14", +}; + +static const char *const qspi_data_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const qspi_clk_groups[] = { + "gpio5", +}; + +static const char *const qspi_cs_n_groups[] = { + "gpio4", +}; + +static const char *const qup_se0_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", "gpio14", "gpio15", +}; + +static const char *const qup_se1_groups[] = { + "gpio28", "gpio30", "gpio38", "gpio39", +}; + +static const char *const qup_se2_groups[] = { + "gpio12", "gpio13", "gpio20", "gpio21", "gpio52", "gpio53", +}; + +static const char *const qup_se3_groups[] = { + "gpio10", "gpio11", "gpio22", "gpio23", +}; + +static const char *const qup_se4_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio52", "gpio53", +}; + +static const char *const qup_se5_groups[] = { + "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", +}; + +static const char *const qup_se5_l1_groups[] = { + "gpio52", "gpio53", +}; + +static const char *const resout_groups[] = { + "gpio44", +}; + +static const char *const rx_los0_groups[] = { + "gpio37", "gpio42", +}; + +static const char *const rx_los1_groups[] = { + "gpio36", "gpio41", +}; + +static const char *const rx_los2_groups[] = { + "gpio35", "gpio40", +}; + +static const char *const sdc_clk_groups[] = { + "gpio5", +}; + +static const char *const sdc_cmd_groups[] = { + "gpio4", +}; + +static const char *const sdc_data_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const tsens_max_groups[] = { + "gpio20", +}; + +static const struct pinfunction ipq5210_functions[] = { + MSM_PIN_FUNCTION(atest_char_start), + MSM_PIN_FUNCTION(atest_char_status0), + MSM_PIN_FUNCTION(atest_char_status1), + MSM_PIN_FUNCTION(atest_char_status2), + MSM_PIN_FUNCTION(atest_char_status3), + MSM_PIN_FUNCTION(atest_tic_en), + MSM_PIN_FUNCTION(audio_pri), + MSM_PIN_FUNCTION(audio_pri_mclk_out0), + MSM_PIN_FUNCTION(audio_pri_mclk_in0), + MSM_PIN_FUNCTION(audio_pri_mclk_out1), + MSM_PIN_FUNCTION(audio_pri_mclk_in1), + MSM_PIN_FUNCTION(audio_pri_mclk_out2), + MSM_PIN_FUNCTION(audio_pri_mclk_in2), + MSM_PIN_FUNCTION(audio_pri_mclk_out3), + MSM_PIN_FUNCTION(audio_pri_mclk_in3), + MSM_PIN_FUNCTION(audio_sec), + MSM_PIN_FUNCTION(audio_sec_mclk_out0), + MSM_PIN_FUNCTION(audio_sec_mclk_in0), + MSM_PIN_FUNCTION(audio_sec_mclk_out1), + MSM_PIN_FUNCTION(audio_sec_mclk_in1), + MSM_PIN_FUNCTION(audio_sec_mclk_out2), + MSM_PIN_FUNCTION(audio_sec_mclk_in2), + MSM_PIN_FUNCTION(audio_sec_mclk_out3), + MSM_PIN_FUNCTION(audio_sec_mclk_in3), + MSM_PIN_FUNCTION(core_voltage_0), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(cri_trng2), + MSM_PIN_FUNCTION(cri_trng3), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(dg_out), + MSM_PIN_FUNCTION(gcc_plltest_bypassnl), + MSM_PIN_FUNCTION(gcc_plltest_resetn), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(led0), + MSM_PIN_FUNCTION(led1), + MSM_PIN_FUNCTION(led2), + MSM_PIN_FUNCTION(mdc_mst), + MSM_PIN_FUNCTION(mdc_slv0), + MSM_PIN_FUNCTION(mdc_slv1), + MSM_PIN_FUNCTION(mdc_slv2), + MSM_PIN_FUNCTION(mdio_mst), + MSM_PIN_FUNCTION(mdio_slv0), + MSM_PIN_FUNCTION(mdio_slv1), + MSM_PIN_FUNCTION(mdio_slv2), + MSM_PIN_FUNCTION(mux_tod_out), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie0_wake), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(pcie1_wake), + MSM_PIN_FUNCTION(pll_test), + MSM_PIN_FUNCTION(pon_active_led), + MSM_PIN_FUNCTION(pon_mux_sel), + MSM_PIN_FUNCTION(pon_rx), + MSM_PIN_FUNCTION(pon_rx_los), + MSM_PIN_FUNCTION(pon_tx), + MSM_PIN_FUNCTION(pon_tx_burst), + MSM_PIN_FUNCTION(pon_tx_dis), + MSM_PIN_FUNCTION(pon_tx_fault), + MSM_PIN_FUNCTION(pon_tx_sd), + MSM_PIN_FUNCTION(gpn_rx_los), + MSM_PIN_FUNCTION(gpn_tx_burst), + MSM_PIN_FUNCTION(gpn_tx_dis), + MSM_PIN_FUNCTION(gpn_tx_fault), + MSM_PIN_FUNCTION(gpn_tx_sd), + MSM_PIN_FUNCTION(pps), + MSM_PIN_FUNCTION(pwm0), + MSM_PIN_FUNCTION(pwm1), + MSM_PIN_FUNCTION(pwm2), + MSM_PIN_FUNCTION(pwm3), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qrng_rosc0), + MSM_PIN_FUNCTION(qrng_rosc1), + MSM_PIN_FUNCTION(qrng_rosc2), + MSM_PIN_FUNCTION(qspi_data), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs_n), + MSM_PIN_FUNCTION(qup_se0), + MSM_PIN_FUNCTION(qup_se1), + MSM_PIN_FUNCTION(qup_se2), + MSM_PIN_FUNCTION(qup_se3), + MSM_PIN_FUNCTION(qup_se4), + MSM_PIN_FUNCTION(qup_se5), + MSM_PIN_FUNCTION(qup_se5_l1), + MSM_PIN_FUNCTION(resout), + MSM_PIN_FUNCTION(rx_los0), + MSM_PIN_FUNCTION(rx_los1), + MSM_PIN_FUNCTION(rx_los2), + MSM_PIN_FUNCTION(sdc_clk), + MSM_PIN_FUNCTION(sdc_cmd), + MSM_PIN_FUNCTION(sdc_data), + MSM_PIN_FUNCTION(tsens_max), +}; + +static const struct msm_pingroup ipq5210_groups[] = { + [0] = PINGROUP(0, sdc_data, qspi_data, pwm2, _, _, _, _, _, _), + [1] = PINGROUP(1, sdc_data, qspi_data, pwm2, _, _, _, _, _, _), + [2] = PINGROUP(2, sdc_data, qspi_data, pwm2, _, _, _, _, _, _), + [3] = PINGROUP(3, sdc_data, qspi_data, pwm2, _, _, _, _, _, _), + [4] = PINGROUP(4, sdc_cmd, qspi_cs_n, _, _, _, _, _, _, _), + [5] = PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _), + [6] = PINGROUP(6, qup_se0, led0, pwm1, _, cri_trng0, qdss_tracedata_a, _, _, _), + [7] = PINGROUP(7, qup_se0, led1, pwm1, _, cri_trng1, qdss_tracedata_a, _, _, _), + [8] = PINGROUP(8, qup_se0, pwm1, audio_pri_mclk_out2, audio_pri_mclk_in2, _, cri_trng2, qdss_tracedata_a, _, _), + [9] = PINGROUP(9, qup_se0, led2, pwm1, _, cri_trng3, qdss_tracedata_a, _, _, _), + [10] = PINGROUP(10, pon_rx_los, qup_se3, pwm0, _, _, qdss_tracedata_a, _, _, _), + [11] = PINGROUP(11, pon_active_led, qup_se3, pwm0, _, _, qdss_tracedata_a, _, _, _), + [12] = PINGROUP(12, pon_tx_dis, qup_se2, pwm0, audio_pri_mclk_out0, audio_pri_mclk_in0, _, qrng_rosc0, qdss_tracedata_a, _), + [13] = PINGROUP(13, gpn_tx_dis, qup_se2, pwm0, audio_pri_mclk_out3, audio_pri_mclk_in3, _, qrng_rosc1, qdss_tracedata_a, _), + [14] = PINGROUP(14, pon_tx_burst, qup_se0, _, qrng_rosc2, qdss_tracedata_a, _, _, _, _), + [15] = PINGROUP(15, pon_tx, qup_se0, _, qdss_tracedata_a, _, _, _, _, _), + [16] = PINGROUP(16, pon_tx_sd, audio_sec_mclk_out1, audio_sec_mclk_in1, qdss_cti_trig_out_b0, _, _, _, _, _), + [17] = PINGROUP(17, pon_tx_fault, audio_sec_mclk_out0, audio_sec_mclk_in0, _, _, _, _, _, _), + [18] = PINGROUP(18, pps, pll_test, _, _, _, _, _, _, _), + [19] = PINGROUP(19, mux_tod_out, audio_pri_mclk_out1, audio_pri_mclk_in1, _, _, _, _, _, _), + [20] = PINGROUP(20, qup_se2, mdc_slv1, tsens_max, qdss_tracedata_a, _, _, _, _, _), + [21] = PINGROUP(21, qup_se2, mdio_slv1, qdss_tracedata_a, _, _, _, _, _, _), + [22] = PINGROUP(22, core_voltage_0, qup_se3, pwm3, _, _, _, _, _, _), + [23] = PINGROUP(23, led0, qup_se3, dbg_out_clk, qdss_traceclk_a, _, _, _, _, _), + [24] = PINGROUP(24, _, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, mdc_mst, led2, _, qdss_tracectl_a, _, _, _, _, _), + [27] = PINGROUP(27, mdio_mst, led1, _, _, _, _, _, _, _), + [28] = PINGROUP(28, pcie1_clk_req_n, qup_se1, _, _, qdss_cti_trig_out_a0, _, _, _, _), + [29] = PINGROUP(29, _, _, _, _, _, _, _, _, _), + [30] = PINGROUP(30, pcie1_wake, qup_se1, _, _, qdss_cti_trig_in_a0, _, _, _, _), + [31] = PINGROUP(31, pcie0_clk_req_n, mdc_slv0, _, qdss_cti_trig_out_a1, _, _, _, _, _), + [32] = PINGROUP(32, _, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, pcie0_wake, mdio_slv0, qdss_cti_trig_in_a1, _, _, _, _, _, _), + [34] = PINGROUP(34, audio_pri, atest_char_status0, qdss_cti_trig_in_b0, _, _, _, _, _, _), + [35] = PINGROUP(35, audio_pri, rx_los2, atest_char_status1, qdss_cti_trig_out_b1, _, _, _, _, _), + [36] = PINGROUP(36, audio_pri, _, rx_los1, atest_char_status2, _, _, _, _, _), + [37] = PINGROUP(37, audio_pri, rx_los0, atest_char_status3, _, qdss_cti_trig_in_b1, _, _, _, _), + [38] = PINGROUP(38, qup_se1, led2, gcc_plltest_bypassnl, qdss_tracedata_a, _, _, _, _, _), + [39] = PINGROUP(39, qup_se1, led1, led0, gcc_tlmm, qdss_tracedata_a, _, _, _, _), + [40] = PINGROUP(40, qup_se4, rx_los2, audio_sec, gcc_plltest_resetn, qdss_tracedata_a, _, _, _, _), + [41] = PINGROUP(41, qup_se4, rx_los1, audio_sec, qdss_tracedata_a, _, _, _, _, _), + [42] = PINGROUP(42, qup_se4, rx_los0, audio_sec, atest_tic_en, _, _, _, _, _), + [43] = PINGROUP(43, qup_se4, audio_sec, _, _, _, _, _, _, _), + [44] = PINGROUP(44, resout, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, pon_mux_sel, _, _, _, _, _, _, _, _), + [46] = PINGROUP(46, dg_out, atest_char_start, _, _, _, _, _, _, _), + [47] = PINGROUP(47, gpn_rx_los, mdc_slv2, qup_se5, _, _, _, _, _, _), + [48] = PINGROUP(48, pon_rx, qup_se5, _, _, _, _, _, _, _), + [49] = PINGROUP(49, gpn_tx_fault, mdio_slv2, qup_se5, audio_sec_mclk_out2, audio_sec_mclk_in2, _, _, _, _), + [50] = PINGROUP(50, gpn_tx_sd, qup_se5, audio_sec_mclk_out3, audio_sec_mclk_in3, _, _, _, _, _), + [51] = PINGROUP(51, gpn_tx_burst, qup_se5, _, _, _, _, _, _, _), + [52] = PINGROUP(52, qup_se2, qup_se5, qup_se4, qup_se5_l1, _, _, _, _, _), + [53] = PINGROUP(53, qup_se2, qup_se4, qup_se5_l1, _, _, _, _, _, _), +}; + +static const struct msm_pinctrl_soc_data ipq5210_tlmm = { + .pins = ipq5210_pins, + .npins = ARRAY_SIZE(ipq5210_pins), + .functions = ipq5210_functions, + .nfunctions = ARRAY_SIZE(ipq5210_functions), + .groups = ipq5210_groups, + .ngroups = ARRAY_SIZE(ipq5210_groups), + .ngpios = 54, +}; + +static const struct of_device_id ipq5210_tlmm_of_match[] = { + { .compatible = "qcom,ipq5210-tlmm", }, + { }, +}; + +static int ipq5210_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq5210_tlmm); +} + +static struct platform_driver ipq5210_tlmm_driver = { + .driver = { + .name = "ipq5210-tlmm", + .of_match_table = ipq5210_tlmm_of_match, + }, + .probe = ipq5210_tlmm_probe, +}; + +static int __init ipq5210_tlmm_init(void) +{ + return platform_driver_register(&ipq5210_tlmm_driver); +} +arch_initcall(ipq5210_tlmm_init); + +static void __exit ipq5210_tlmm_exit(void) +{ + platform_driver_unregister(&ipq5210_tlmm_driver); +} +module_exit(ipq5210_tlmm_exit); + +MODULE_DESCRIPTION("QTI IPQ5210 TLMM driver"); +MODULE_LICENSE("GPL"); From a22d2598a5637986115ec442781edb634097ab88 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Tue, 31 Mar 2026 16:06:55 -0400 Subject: [PATCH 73/84] dt-bindings: qcom: lpass-lpi-common: add reserved GPIOs property There can be reserved GPIOs on the LPASS LPI pin controller to possibly control sensors. Add the property for reserved GPIOs so they can be avoided appropriately. Adapted from the same entry in qcom,tlmm-common.yaml. Signed-off-by: Richard Acayan Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,lpass-lpi-common.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-common.yaml index 619341dd637c..30f93b8159fd 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-common.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-common.yaml @@ -27,6 +27,14 @@ properties: gpio-ranges: maxItems: 1 + gpio-reserved-ranges: + minItems: 1 + maxItems: 30 + description: + Pins can be reserved for trusted applications or for LPASS, thereby + inaccessible from the OS. This property can be used to mark the pins + which resources should not be accessed by the OS. + required: - gpio-controller - "#gpio-cells" From 72102fdae3a01365e32de651e8332db663899901 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Tue, 31 Mar 2026 16:06:56 -0400 Subject: [PATCH 74/84] dt-bindings: pinctrl: qcom: Add SDM670 LPASS LPI pinctrl Add the pin controller for the audio Low-Power Island (LPI) on SDM670. Signed-off-by: Richard Acayan Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../qcom,sdm670-lpass-lpi-pinctrl.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000000..c76ad70e6b9f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM670 SoC LPASS LPI TLMM + +maintainers: + - Richard Acayan + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SDM670 SoC. + +properties: + compatible: + const: qcom,sdm670-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdm670-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdm670-lpass-state" + additionalProperties: false + +$defs: + qcom-sdm670-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-9]|3[0-1])$" + + function: + enum: [ gpio, comp_rx, dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, + i2s1_clk, i2s_data, i2s_ws, lpi_cdc_rst, mclk0, pdm_rx, + pdm_sync, pdm_tx, slimbus_clk ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + lpi_tlmm: pinctrl@62b40000 { + compatible = "qcom,sdm670-lpass-lpi-pinctrl"; + reg = <0x62b40000 0x20000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 32>; + + cdc_comp_default: cdc-comp-default-state { + pins = "gpio22", "gpio24"; + function = "comp_rx"; + drive-strength = <4>; + }; + }; From 9826035a75da609ac2424c97915d6fe5b836ee65 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Tue, 31 Mar 2026 16:06:57 -0400 Subject: [PATCH 75/84] pinctrl: qcom: add sdm670 lpi tlmm The Snapdragon 670 has an Low-Power Island (LPI) TLMM for configuring pins related to audio. Add the driver for this. Signed-off-by: Richard Acayan Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 10 ++ drivers/pinctrl/qcom/Makefile | 1 + .../pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c | 166 ++++++++++++++++++ 3 files changed, 177 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index ee34ffca3917..80af372a1147 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -99,6 +99,16 @@ config PINCTRL_SM4250_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SM4250 platform. +config PINCTRL_SDM670_LPASS_LPI + tristate "Qualcomm Technologies Inc SDM670 LPASS LPI pin controller driver" + depends on GPIOLIB + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SDM670 platform. + config PINCTRL_SM6115_LPASS_LPI tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 84ff95ff246a..4c585bad813c 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_PINCTRL_SC8280XP) += pinctrl-sc8280xp.o obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_SDM660_LPASS_LPI) += pinctrl-sdm660-lpass-lpi.o obj-$(CONFIG_PINCTRL_SDM670) += pinctrl-sdm670.o +obj-$(CONFIG_PINCTRL_SDM670_LPASS_LPI) += pinctrl-sdm670-lpass-lpi.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o diff --git a/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c new file mode 100644 index 000000000000..6270c6d09c22 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023-2026, Richard Acayan. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_comp_rx, + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_lpi_cdc_rst, + LPI_MUX_mclk0, + LPI_MUX_pdm_rx, + LPI_MUX_pdm_sync, + LPI_MUX_pdm_tx, + LPI_MUX_slimbus_clk, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const struct pinctrl_pin_desc sdm670_lpi_pinctrl_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), + PINCTRL_PIN(23, "gpio23"), + PINCTRL_PIN(24, "gpio24"), + PINCTRL_PIN(25, "gpio25"), + PINCTRL_PIN(26, "gpio26"), + PINCTRL_PIN(27, "gpio27"), + PINCTRL_PIN(28, "gpio28"), + PINCTRL_PIN(29, "gpio29"), + PINCTRL_PIN(30, "gpio30"), + PINCTRL_PIN(31, "gpio31"), +}; + +static const char * const comp_rx_groups[] = { "gpio22", "gpio24" }; +static const char * const dmic1_clk_groups[] = { "gpio26" }; +static const char * const dmic1_data_groups[] = { "gpio27" }; +static const char * const dmic2_clk_groups[] = { "gpio28" }; +static const char * const dmic2_data_groups[] = { "gpio29" }; +static const char * const i2s1_clk_groups[] = { "gpio8" }; +static const char * const i2s1_ws_groups[] = { "gpio9" }; +static const char * const i2s1_data_groups[] = { "gpio10", "gpio11" }; +static const char * const lpi_cdc_rst_groups[] = { "gpio29" }; +static const char * const mclk0_groups[] = { "gpio19" }; +static const char * const pdm_rx_groups[] = { "gpio21", "gpio23", "gpio25" }; +static const char * const pdm_sync_groups[] = { "gpio19" }; +static const char * const pdm_tx_groups[] = { "gpio20" }; +static const char * const slimbus_clk_groups[] = { "gpio18" }; + +const struct lpi_pingroup sdm670_lpi_pinctrl_groups[] = { + LPI_PINGROUP(0, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(1, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(2, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(3, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(4, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(5, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(6, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, _, _, i2s1_clk, _), + LPI_PINGROUP(9, LPI_NO_SLEW, _, _, i2s1_ws, _), + LPI_PINGROUP(10, LPI_NO_SLEW, _, _, _, i2s1_data), + LPI_PINGROUP(11, LPI_NO_SLEW, _, i2s1_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(14, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(15, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(16, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(18, LPI_NO_SLEW, _, slimbus_clk, _, _), + LPI_PINGROUP(19, LPI_NO_SLEW, mclk0, _, pdm_sync, _), + LPI_PINGROUP(20, LPI_NO_SLEW, _, pdm_tx, _, _), + LPI_PINGROUP(21, LPI_NO_SLEW, _, pdm_rx, _, _), + LPI_PINGROUP(22, LPI_NO_SLEW, _, comp_rx, _, _), + LPI_PINGROUP(23, LPI_NO_SLEW, pdm_rx, _, _, _), + LPI_PINGROUP(24, LPI_NO_SLEW, comp_rx, _, _, _), + LPI_PINGROUP(25, LPI_NO_SLEW, pdm_rx, _, _, _), + LPI_PINGROUP(26, LPI_NO_SLEW, dmic1_clk, _, _, _), + LPI_PINGROUP(27, LPI_NO_SLEW, dmic1_data, _, _, _), + LPI_PINGROUP(28, LPI_NO_SLEW, dmic2_clk, _, _, _), + LPI_PINGROUP(29, LPI_NO_SLEW, dmic2_data, lpi_cdc_rst, _, _), + LPI_PINGROUP(30, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(31, LPI_NO_SLEW, _, _, _, _), +}; + +const struct lpi_function sdm670_lpi_pinctrl_functions[] = { + LPI_FUNCTION(comp_rx), + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(lpi_cdc_rst), + LPI_FUNCTION(mclk0), + LPI_FUNCTION(pdm_tx), + LPI_FUNCTION(pdm_rx), + LPI_FUNCTION(pdm_sync), + LPI_FUNCTION(slimbus_clk), +}; + +static const struct lpi_pinctrl_variant_data sdm670_lpi_pinctrl_data = { + .pins = sdm670_lpi_pinctrl_pins, + .npins = ARRAY_SIZE(sdm670_lpi_pinctrl_pins), + .groups = sdm670_lpi_pinctrl_groups, + .ngroups = ARRAY_SIZE(sdm670_lpi_pinctrl_groups), + .functions = sdm670_lpi_pinctrl_functions, + .nfunctions = ARRAY_SIZE(sdm670_lpi_pinctrl_functions), + .flags = LPI_FLAG_SLEW_RATE_SAME_REG, +}; + +static const struct of_device_id sdm670_lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,sdm670-lpass-lpi-pinctrl", + .data = &sdm670_lpi_pinctrl_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, sdm670_lpi_pinctrl_of_match); + +static struct platform_driver sdm670_lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sdm670-lpass-lpi-pinctrl", + .of_match_table = sdm670_lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; +module_platform_driver(sdm670_lpi_pinctrl_driver); + +MODULE_AUTHOR("Richard Acayan "); +MODULE_DESCRIPTION("QTI SDM670 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); From ca1c2ddff00480c213903a1479b56203536e92de Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Wed, 1 Apr 2026 08:35:49 +0800 Subject: [PATCH 76/84] pinctrl: sophgo: pinctrl-sg2042: Fix wrong module description Fix the SoC model in module description string, it should be sg2042 instead of sg2002. Fixes: 1e67465d3b74 ("pinctrl: sophgo: add support for SG2042 SoC") Signed-off-by: Inochi Amaoto Reviewed-by: Chen Wang Signed-off-by: Linus Walleij --- drivers/pinctrl/sophgo/pinctrl-sg2042.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/sophgo/pinctrl-sg2042.c b/drivers/pinctrl/sophgo/pinctrl-sg2042.c index 185305ac897d..8dba12e122a4 100644 --- a/drivers/pinctrl/sophgo/pinctrl-sg2042.c +++ b/drivers/pinctrl/sophgo/pinctrl-sg2042.c @@ -651,5 +651,5 @@ static struct platform_driver sg2042_pinctrl_driver = { }; module_platform_driver(sg2042_pinctrl_driver); -MODULE_DESCRIPTION("Pinctrl driver for the SG2002 series SoC"); +MODULE_DESCRIPTION("Pinctrl driver for the SG2042 series SoC"); MODULE_LICENSE("GPL"); From 7648112358a4207916d3e38bfee49f85552fe95f Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Wed, 1 Apr 2026 08:35:50 +0800 Subject: [PATCH 77/84] pinctrl: sophgo: pinctrl-sg2044: Fix wrong module description Fix the SoC model in module description string, it should be sg2044 instead of sg2002. Fixes: 614a54cb5ac3 ("pinctrl: sophgo: add support for SG2044 SoC") Signed-off-by: Inochi Amaoto Reviewed-by: Chen Wang Signed-off-by: Linus Walleij --- drivers/pinctrl/sophgo/pinctrl-sg2044.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/sophgo/pinctrl-sg2044.c b/drivers/pinctrl/sophgo/pinctrl-sg2044.c index b0c46d8954ca..cf0b674c038f 100644 --- a/drivers/pinctrl/sophgo/pinctrl-sg2044.c +++ b/drivers/pinctrl/sophgo/pinctrl-sg2044.c @@ -714,5 +714,5 @@ static struct platform_driver sg2044_pinctrl_driver = { }; module_platform_driver(sg2044_pinctrl_driver); -MODULE_DESCRIPTION("Pinctrl driver for the SG2002 series SoC"); +MODULE_DESCRIPTION("Pinctrl driver for the SG2044 series SoC"); MODULE_LICENSE("GPL"); From 7fe21f1ef74f2f4b95896789db656c84b22f01c1 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Wed, 8 Apr 2026 18:30:38 -0400 Subject: [PATCH 78/84] pinctrl: qcom: sdm670-lpass-lpi: label variables as static These variables are local to the driver and have no need to be exported to the global namespace. Label them as static to fix compiler warnings. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202604080950.Mvm8aN0a-lkp@intel.com/ Fixes: 9826035a75da ("pinctrl: qcom: add sdm670 lpi tlmm") Signed-off-by: Richard Acayan Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c index 6270c6d09c22..858146c408d0 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c @@ -80,7 +80,7 @@ static const char * const pdm_sync_groups[] = { "gpio19" }; static const char * const pdm_tx_groups[] = { "gpio20" }; static const char * const slimbus_clk_groups[] = { "gpio18" }; -const struct lpi_pingroup sdm670_lpi_pinctrl_groups[] = { +static const struct lpi_pingroup sdm670_lpi_pinctrl_groups[] = { LPI_PINGROUP(0, LPI_NO_SLEW, _, _, _, _), LPI_PINGROUP(1, LPI_NO_SLEW, _, _, _, _), LPI_PINGROUP(2, LPI_NO_SLEW, _, _, _, _), @@ -115,7 +115,7 @@ const struct lpi_pingroup sdm670_lpi_pinctrl_groups[] = { LPI_PINGROUP(31, LPI_NO_SLEW, _, _, _, _), }; -const struct lpi_function sdm670_lpi_pinctrl_functions[] = { +static const struct lpi_function sdm670_lpi_pinctrl_functions[] = { LPI_FUNCTION(comp_rx), LPI_FUNCTION(dmic1_clk), LPI_FUNCTION(dmic1_data), From 4ef01cf208367014ceac7b81f60515a66b3f2ce5 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Fri, 20 Mar 2026 13:23:23 +0100 Subject: [PATCH 79/84] dt-bindings: pinctrl: apple,pinctrl: Add t8122 compatible The pin controller on the Apple silicon t8122 (M3) SoC is compatible with the existing driver. Add "apple,t8122-pinctrl" as SoC specific compatible under "apple,t8103-pinctrl" used by the driver. Signed-off-by: Janne Grunau Acked-by: Rob Herring (Arm) Reviewed-by: Linus Walleij Reviewed-by: Neal Gompa Reviewed-by: Joshua Peisach Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml index 665ec79a69f1..41073176bc69 100644 --- a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -18,7 +18,9 @@ properties: compatible: oneOf: - items: - - const: apple,t6020-pinctrl + - enum: + - apple,t6020-pinctrl + - apple,t8122-pinctrl - const: apple,t8103-pinctrl - items: # Do not add additional SoC to this list. From ee2d43699e255fa8f2c5e4b1c4d2d783ca3047b6 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 7 Apr 2026 16:56:10 -0700 Subject: [PATCH 80/84] dt-bindings: pinctrl: pinctrl-single: Add brcm,bcm7038-padconf Add the "brcm,bcm7038-padconf" compatible to the pinctrl-single binding. Signed-off-by: Florian Fainelli Acked-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml index 9135788cf62e..afe7329a1df2 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml @@ -38,6 +38,10 @@ properties: - enum: - marvell,pxa1908-padconf - const: pinconf-single + - items: + - enum: + - brcm,bcm7038-padconf + - const: pinctrl-single reg: maxItems: 1 From 6ea7185731ada6bb0633f3347fc8eb2a013e54c7 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 7 Apr 2026 16:56:11 -0700 Subject: [PATCH 81/84] pinctrl: single: Add bcm7038-padconf compatible matching Just like the TI J7200 padconf, we lose the context and therefore need to save it and restore it across suspend/resume states. Signed-off-by: Florian Fainelli [linusw@kernel.org: rebased on am62l changes] Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 288c9c9bce9a..7e022a46ee42 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1960,7 +1960,7 @@ static const struct pcs_soc_data pinctrl_single_am654 = { .irq_status_mask = (1 << 30), /* WKUP_EVT */ }; -static const struct pcs_soc_data pinctrl_single_j7200 = { +static const struct pcs_soc_data pinctrl_single_loss_off = { .flags = PCS_CONTEXT_LOSS_OFF, }; @@ -1972,6 +1972,7 @@ static const struct pcs_soc_data pinconf_single = { }; static const struct of_device_id pcs_of_match[] = { + { .compatible = "brcm,bcm7038-padconf", .data = &pinctrl_single_loss_off }, { .compatible = "marvell,pxa1908-padconf", .data = &pinconf_single }, { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x }, { .compatible = "ti,am654-padconf", .data = &pinctrl_single_am654 }, @@ -1979,8 +1980,8 @@ static const struct of_device_id pcs_of_match[] = { { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup }, { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup }, - { .compatible = "ti,j7200-padconf", .data = &pinctrl_single_j7200 }, - { .compatible = "ti,am62l-padconf", .data = &pinctrl_single_j7200 }, + { .compatible = "ti,j7200-padconf", .data = &pinctrl_single_loss_off }, + { .compatible = "ti,am62l-padconf", .data = &pinctrl_single_loss_off }, { .compatible = "pinctrl-single", .data = &pinctrl_single }, { .compatible = "pinconf-single", .data = &pinconf_single }, { }, From c43b91eef8eaf29ee895ab1becb799279bc789d6 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 6 Apr 2026 10:51:14 +0300 Subject: [PATCH 82/84] dt-bindings: pinctrl: pinctrl-max77620: convert to DT schema Convert pinctrl-max77620 devicetree bindings for the MAX77620 PMIC from TXT to YAML format. This patch does not change any functionality; the bindings remain the same. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../pinctrl/maxim,max77620-pinctrl.yaml | 98 ++++++++++++++ .../bindings/pinctrl/pinctrl-max77620.txt | 127 ------------------ 2 files changed, 98 insertions(+), 127 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/maxim,max77620-pinctrl.yaml delete mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt diff --git a/Documentation/devicetree/bindings/pinctrl/maxim,max77620-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/maxim,max77620-pinctrl.yaml new file mode 100644 index 000000000000..b3ea36474317 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/maxim,max77620-pinctrl.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/maxim,max77620-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pinmux controller function for Maxim MAX77620 Power management IC + +maintainers: + - Svyatoslav Ryhel + +description: + Device has 8 GPIO pins which can be configured as GPIO as well as the + special IO functions. + +allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + +patternProperties: + "^(pin|gpio).": + type: object + additionalProperties: false + + properties: + pins: + items: + enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7 ] + + function: + items: + enum: [ gpio, lpm-control-in, fps-out, 32k-out1, sd0-dvs-in, sd1-dvs-in, + reference-out ] + + drive-push-pull: true + drive-open-drain: true + bias-pull-up: true + bias-pull-down: true + + maxim,active-fps-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + FPS source for the GPIOs to get enabled/disabled when system is in + active state. Valid values are: + - MAX77620_FPS_SRC_0: FPS source is FPS0. + - MAX77620_FPS_SRC_1: FPS source is FPS1 + - MAX77620_FPS_SRC_2: FPS source is FPS2 + - MAX77620_FPS_SRC_NONE: GPIO is not controlled by FPS events and + it gets enabled/disabled by register access. + Absence of this property will leave the FPS configuration register + for that GPIO to default configuration. + + maxim,active-fps-power-up-slot: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Sequencing event slot number on which the GPIO get enabled when + master FPS input event set to HIGH. This is applicable if FPS source + is selected as FPS0, FPS1 or FPS2. + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + maxim,active-fps-power-down-slot: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Sequencing event slot number on which the GPIO get disabled when + master FPS input event set to LOW. This is applicable if FPS source + is selected as FPS0, FPS1 or FPS2. + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + maxim,suspend-fps-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + This is same as property "maxim,active-fps-source" but value get + configured when system enters in to suspend state. + + maxim,suspend-fps-power-up-slot: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + This is same as property "maxim,active-fps-power-up-slot" but this + value get configured into FPS configuration register when system + enters into suspend. This is applicable if suspend state FPS source + is selected as FPS0, FPS1 or FPS2. + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + maxim,suspend-fps-power-down-slot: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + This is same as property "maxim,active-fps-power-down-slot" but this + value get configured into FPS configuration register when system + enters into suspend. This is applicable if suspend state FPS source + is selected as FPS0, FPS1 or FPS2. + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + required: + - pins + +additionalProperties: false + +# see maxim,max77620.yaml for an example diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt deleted file mode 100644 index 28fbca180068..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt +++ /dev/null @@ -1,127 +0,0 @@ -Pincontrol driver for MAX77620 Power management IC from Maxim Semiconductor. - -Device has 8 GPIO pins which can be configured as GPIO as well as the -special IO functions. - -Please refer file -for details of the common pinctrl bindings used by client devices, -including the meaning of the phrase "pin configuration node". - -Optional Pinmux properties: --------------------------- -Following properties are required if default setting of pins are required -at boot. -- pinctrl-names: A pinctrl state named per . -- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per - . - -The pin configurations are defined as child of the pinctrl states node. Each -sub-node have following properties: - -Required properties: ------------------- -- pins: List of pins. Valid values of pins properties are: - gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7. - -Optional properties: -------------------- -Following are optional properties defined as pinmux DT binding document -. Absence of properties will leave the configuration -on default. - function, - drive-push-pull, - drive-open-drain, - bias-pull-up, - bias-pull-down. - -Valid values for function properties are: - gpio, lpm-control-in, fps-out, 32k-out, sd0-dvs-in, sd1-dvs-in, - reference-out - -There are also customised properties for the GPIO1, GPIO2 and GPIO3. These -customised properties are required to configure FPS configuration parameters -of these GPIOs. Please refer for more -detail of Flexible Power Sequence (FPS). - -- maxim,active-fps-source: FPS source for the GPIOs to get - enabled/disabled when system is in - active state. Valid values are: - - MAX77620_FPS_SRC_0, - FPS source is FPS0. - - MAX77620_FPS_SRC_1, - FPS source is FPS1 - - MAX77620_FPS_SRC_2 and - FPS source is FPS2 - - MAX77620_FPS_SRC_NONE. - GPIO is not controlled - by FPS events and it gets - enabled/disabled by register - access. - Absence of this property will leave - the FPS configuration register for that - GPIO to default configuration. - -- maxim,active-fps-power-up-slot: Sequencing event slot number on which - the GPIO get enabled when - master FPS input event set to HIGH. - Valid values are 0 to 7. - This is applicable if FPS source is - selected as FPS0, FPS1 or FPS2. - -- maxim,active-fps-power-down-slot: Sequencing event slot number on which - the GPIO get disabled when master - FPS input event set to LOW. - Valid values are 0 to 7. - This is applicable if FPS source is - selected as FPS0, FPS1 or FPS2. - -- maxim,suspend-fps-source: This is same as property - "maxim,active-fps-source" but value - get configured when system enters in - to suspend state. - -- maxim,suspend-fps-power-up-slot: This is same as property - "maxim,active-fps-power-up-slot" but - this value get configured into FPS - configuration register when system - enters into suspend. - This is applicable if suspend state - FPS source is selected as FPS0, FPS1 or - -- maxim,suspend-fps-power-down-slot: This is same as property - "maxim,active-fps-power-down-slot" but - this value get configured into FPS - configuration register when system - enters into suspend. - This is applicable if suspend state - FPS source is selected as FPS0, FPS1 or - FPS2. - -Example: --------- -#include -... -max77620@3c { - - pinctrl-names = "default"; - pinctrl-0 = <&spmic_default>; - - spmic_default: pinmux@0 { - pin_gpio0 { - pins = "gpio0"; - function = "gpio"; - }; - - pin_gpio1 { - pins = "gpio1"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - - pin_gpio2 { - pins = "gpio2"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - }; -}; From ec25710ce8c55295b92f3547a71f376350ad2048 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 8 Apr 2026 19:45:47 +0530 Subject: [PATCH 83/84] dt-bindings: pinctrl: qcom: Describe Hawi TLMM block The Top Level Mode Multiplexer (TLMM) in the Qualcomm Hawi SoC provides GPIO and pinctrl functionality for UFS, SDC and 226 GPIO pins. Add a DeviceTree binding to describe the TLMM block on Qualcomm's Hawi SoC. Signed-off-by: Mukesh Ojha Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,hawi-tlmm.yaml | 120 ++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml new file mode 100644 index 000000000000..3b3961789860 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,hawi-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Hawi TLMM block + +maintainers: + - Mukesh Ojha + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Hawi SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,hawi-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 113 + + gpio-line-names: + maxItems: 226 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-hawi-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-hawi-tlmm-state" + additionalProperties: false + +$defs: + qcom-hawi-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-9]|22[0-5])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk, + audio_ref_clk, cam_mclk, cci_async_in, cci_i2c0, cci_i2c1, + cci_i2c2, cci_i2c3, cci_i2c4, cci_i2c5, cci_timer, coex_espmi, + coex_uart1_rx, coex_uart1_tx, dbg_out_clk, ddr_bist, ddr_pxi, + dp_hot, egpio, gcc_gp, gnss_adc, host_rst, i2chub0_se0, + i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4, i2s0, i2s1, + ibi_i3c, jitter_bist, mdp_esync0, mdp_esync1, mdp_esync2, + mdp_vsync, mdp_vsync_e, mdp_vsync_p, mdp_vsync0_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out, + modem_pps_in, modem_pps_out, nav_gpio, nav_gpio0, nav_gpio3, + nav_rffe, pcie0_clk_req_n, pcie0_rst_n, pcie1_clk_req_n, + phase_flag, pll_bist_sync, pll_clk_aux, qdss_cti, qlink, + qspi, qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, + qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, + qup2_se1, qup2_se2, qup2_se3, qup2_se4_01, qup2_se4_23, + qup3_se0_01, qup3_se0_23, qup3_se1, qup3_se2, qup3_se3, + qup3_se4, qup3_se5, qup4_se0, qup4_se1, qup4_se2, qup4_se3_01, + qup4_se3_23, qup4_se3_l3, qup4_se4_01, qup4_se4_23, qup4_se4_l3, + rng_rosc, sd_write_protect, sdc4_clk, sdc4_cmd, sdc4_data, + sys_throttle, tb_trig_sdc, tmess_rng, tsense_clm, tsense_pwm, + uim0, uim1, usb0_hs, usb_phy, vfr, vsense_trigger_mirnat, + wcn_sw_ctrl ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@f100000 { + compatible = "qcom,hawi-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 227>; + interrupt-controller; + #interrupt-cells = <2>; + + qup-uart7-state { + pins = "gpio62", "gpio63"; + function = "qup1_se7"; + }; + }; +... From 90700e10d2ad61c13a5117cfa5e08d9f2e497dcc Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 8 Apr 2026 19:45:48 +0530 Subject: [PATCH 84/84] pinctrl: qcom: Add Hawi pinctrl driver Add pinctrl driver for TLMM block found in the Hawi SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Reviewed-by: Bjorn Andersson Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig.msm | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-hawi.c | 1610 +++++++++++++++++++++++++++ 3 files changed, 1621 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-hawi.c diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm index 17416dce8e70..836cdeca1006 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -35,6 +35,16 @@ config PINCTRL_GLYMUR Say Y here to compile statically, or M here to compile it as a module. If unsure, say N. +config PINCTRL_HAWI + tristate "Qualcomm Technologies Inc Hawi pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM) + block found on the Qualcomm Technologies Inc Hawi platform. + Say Y here to compile statically, or M here to compile it as a module. + If unsure, say N. + config PINCTRL_IPQ4019 tristate "Qualcomm IPQ4019 pin controller driver" depends on ARM || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 4c585bad813c..84bda3ada874 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o obj-$(CONFIG_PINCTRL_ELIZA) += pinctrl-eliza.o obj-$(CONFIG_PINCTRL_GLYMUR) += pinctrl-glymur.o +obj-$(CONFIG_PINCTRL_HAWI) += pinctrl-hawi.o obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o diff --git a/drivers/pinctrl/qcom/pinctrl-hawi.c b/drivers/pinctrl/qcom/pinctrl-hawi.c new file mode 100644 index 000000000000..5c7894f3b9cb --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-hawi.c @@ -0,0 +1,1610 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 /* egpio mode */ \ + }, \ + .nfuncs = 12, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_wakeup_present_bit = 6, \ + .intr_wakeup_enable_bit = 7, \ + .intr_target_bit = 8, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, ctl, io) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = io, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc hawi_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "GPIO_185"), + PINCTRL_PIN(186, "GPIO_186"), + PINCTRL_PIN(187, "GPIO_187"), + PINCTRL_PIN(188, "GPIO_188"), + PINCTRL_PIN(189, "GPIO_189"), + PINCTRL_PIN(190, "GPIO_190"), + PINCTRL_PIN(191, "GPIO_191"), + PINCTRL_PIN(192, "GPIO_192"), + PINCTRL_PIN(193, "GPIO_193"), + PINCTRL_PIN(194, "GPIO_194"), + PINCTRL_PIN(195, "GPIO_195"), + PINCTRL_PIN(196, "GPIO_196"), + PINCTRL_PIN(197, "GPIO_197"), + PINCTRL_PIN(198, "GPIO_198"), + PINCTRL_PIN(199, "GPIO_199"), + PINCTRL_PIN(200, "GPIO_200"), + PINCTRL_PIN(201, "GPIO_201"), + PINCTRL_PIN(202, "GPIO_202"), + PINCTRL_PIN(203, "GPIO_203"), + PINCTRL_PIN(204, "GPIO_204"), + PINCTRL_PIN(205, "GPIO_205"), + PINCTRL_PIN(206, "GPIO_206"), + PINCTRL_PIN(207, "GPIO_207"), + PINCTRL_PIN(208, "GPIO_208"), + PINCTRL_PIN(209, "GPIO_209"), + PINCTRL_PIN(210, "GPIO_210"), + PINCTRL_PIN(211, "GPIO_211"), + PINCTRL_PIN(212, "GPIO_212"), + PINCTRL_PIN(213, "GPIO_213"), + PINCTRL_PIN(214, "GPIO_214"), + PINCTRL_PIN(215, "GPIO_215"), + PINCTRL_PIN(216, "GPIO_216"), + PINCTRL_PIN(217, "GPIO_217"), + PINCTRL_PIN(218, "GPIO_218"), + PINCTRL_PIN(219, "GPIO_219"), + PINCTRL_PIN(220, "GPIO_220"), + PINCTRL_PIN(221, "GPIO_221"), + PINCTRL_PIN(222, "GPIO_222"), + PINCTRL_PIN(223, "GPIO_223"), + PINCTRL_PIN(224, "GPIO_224"), + PINCTRL_PIN(225, "GPIO_225"), + PINCTRL_PIN(226, "UFS_RESET"), + PINCTRL_PIN(227, "SDC2_CLK"), + PINCTRL_PIN(228, "SDC2_CMD"), + PINCTRL_PIN(229, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); +DECLARE_MSM_GPIO_PINS(185); +DECLARE_MSM_GPIO_PINS(186); +DECLARE_MSM_GPIO_PINS(187); +DECLARE_MSM_GPIO_PINS(188); +DECLARE_MSM_GPIO_PINS(189); +DECLARE_MSM_GPIO_PINS(190); +DECLARE_MSM_GPIO_PINS(191); +DECLARE_MSM_GPIO_PINS(192); +DECLARE_MSM_GPIO_PINS(193); +DECLARE_MSM_GPIO_PINS(194); +DECLARE_MSM_GPIO_PINS(195); +DECLARE_MSM_GPIO_PINS(196); +DECLARE_MSM_GPIO_PINS(197); +DECLARE_MSM_GPIO_PINS(198); +DECLARE_MSM_GPIO_PINS(199); +DECLARE_MSM_GPIO_PINS(200); +DECLARE_MSM_GPIO_PINS(201); +DECLARE_MSM_GPIO_PINS(202); +DECLARE_MSM_GPIO_PINS(203); +DECLARE_MSM_GPIO_PINS(204); +DECLARE_MSM_GPIO_PINS(205); +DECLARE_MSM_GPIO_PINS(206); +DECLARE_MSM_GPIO_PINS(207); +DECLARE_MSM_GPIO_PINS(208); +DECLARE_MSM_GPIO_PINS(209); +DECLARE_MSM_GPIO_PINS(210); +DECLARE_MSM_GPIO_PINS(211); +DECLARE_MSM_GPIO_PINS(212); +DECLARE_MSM_GPIO_PINS(213); +DECLARE_MSM_GPIO_PINS(214); +DECLARE_MSM_GPIO_PINS(215); +DECLARE_MSM_GPIO_PINS(216); +DECLARE_MSM_GPIO_PINS(217); +DECLARE_MSM_GPIO_PINS(218); +DECLARE_MSM_GPIO_PINS(219); +DECLARE_MSM_GPIO_PINS(220); +DECLARE_MSM_GPIO_PINS(221); +DECLARE_MSM_GPIO_PINS(222); +DECLARE_MSM_GPIO_PINS(223); +DECLARE_MSM_GPIO_PINS(224); +DECLARE_MSM_GPIO_PINS(225); + +static const unsigned int ufs_reset_pins[] = { 226 }; +static const unsigned int sdc2_clk_pins[] = { 227 }; +static const unsigned int sdc2_cmd_pins[] = { 228 }; +static const unsigned int sdc2_data_pins[] = { 229 }; + +enum hawi_functions { + msm_mux_gpio, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ext_mclk, + msm_mux_audio_ref_clk, + msm_mux_cam_mclk, + msm_mux_cci_async_in, + msm_mux_cci_i2c0, + msm_mux_cci_i2c1, + msm_mux_cci_i2c2, + msm_mux_cci_i2c3, + msm_mux_cci_i2c4, + msm_mux_cci_i2c5, + msm_mux_cci_timer, + msm_mux_coex_espmi, + msm_mux_coex_uart1_rx, + msm_mux_coex_uart1_tx, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist, + msm_mux_ddr_pxi, + msm_mux_dp_hot, + msm_mux_egpio, + msm_mux_gcc_gp, + msm_mux_gnss_adc, + msm_mux_host_rst, + msm_mux_i2chub0_se0, + msm_mux_i2chub0_se1, + msm_mux_i2chub0_se2, + msm_mux_i2chub0_se3, + msm_mux_i2chub0_se4, + msm_mux_i2s0, + msm_mux_i2s1, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_mdp_esync0, + msm_mux_mdp_esync1, + msm_mux_mdp_esync2, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync_e, + msm_mux_mdp_vsync_p, + msm_mux_mdp_vsync0_out, + msm_mux_mdp_vsync1_out, + msm_mux_mdp_vsync2_out, + msm_mux_mdp_vsync3_out, + msm_mux_mdp_vsync5_out, + msm_mux_modem_pps_in, + msm_mux_modem_pps_out, + msm_mux_nav_gpio, + msm_mux_nav_gpio0, + msm_mux_nav_gpio3, + msm_mux_nav_rffe, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie0_rst_n, + msm_mux_pcie1_clk_req_n, + msm_mux_phase_flag, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_qdss_cti, + msm_mux_qlink, + msm_mux_qspi, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup1_se0, + msm_mux_qup1_se1, + msm_mux_qup1_se2, + msm_mux_qup1_se3, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_qup1_se7, + msm_mux_qup2_se0, + msm_mux_qup2_se1, + msm_mux_qup2_se2, + msm_mux_qup2_se3, + msm_mux_qup2_se4_01, + msm_mux_qup2_se4_23, + msm_mux_qup3_se0_01, + msm_mux_qup3_se0_23, + msm_mux_qup3_se1, + msm_mux_qup3_se2, + msm_mux_qup3_se3, + msm_mux_qup3_se4, + msm_mux_qup3_se5, + msm_mux_qup4_se0, + msm_mux_qup4_se1, + msm_mux_qup4_se2, + msm_mux_qup4_se3_01, + msm_mux_qup4_se3_23, + msm_mux_qup4_se3_l3, + msm_mux_qup4_se4_01, + msm_mux_qup4_se4_23, + msm_mux_qup4_se4_l3, + msm_mux_rng_rosc, + msm_mux_sd_write_protect, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sdc4_data, + msm_mux_sys_throttle, + msm_mux_tb_trig_sdc, + msm_mux_tmess_rng, + msm_mux_tsense_clm, + msm_mux_tsense_pwm, + msm_mux_uim0, + msm_mux_uim1, + msm_mux_usb0_hs, + msm_mux_usb_phy, + msm_mux_vfr, + msm_mux_vsense_trigger_mirnat, + msm_mux_wcn_sw_ctrl, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167", + "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", + "gpio174", "gpio175", "gpio176", "gpio177", "gpio178", "gpio179", + "gpio180", "gpio181", "gpio182", "gpio183", "gpio184", "gpio185", + "gpio186", "gpio187", "gpio188", "gpio189", "gpio190", "gpio191", + "gpio192", "gpio193", "gpio194", "gpio195", "gpio196", "gpio197", + "gpio198", "gpio199", "gpio200", "gpio201", "gpio202", "gpio203", + "gpio204", "gpio205", "gpio206", "gpio207", "gpio208", "gpio209", + "gpio210", "gpio211", "gpio212", "gpio213", "gpio214", "gpio215", + "gpio216", "gpio217", "gpio218", "gpio219", "gpio220", "gpio221", + "gpio222", "gpio223", "gpio224", "gpio225", +}; + +static const char *const aoss_cti_groups[] = { + "gpio74", "gpio75", "gpio76", "gpio77", +}; + +static const char *const atest_char_groups[] = { + "gpio126", "gpio127", "gpio128", "gpio129", "gpio133", +}; + +static const char *const atest_usb_groups[] = { + "gpio70", "gpio71", "gpio72", "gpio73", "gpio129", +}; + +static const char *const audio_ext_mclk_groups[] = { + "gpio120", "gpio121", +}; + +static const char *const audio_ref_clk_groups[] = { + "gpio120", +}; + +static const char *const cam_mclk_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", + "gpio95", "gpio96", +}; + +static const char *const cci_async_in_groups[] = { + "gpio15", "gpio109", "gpio110", +}; + +static const char *const cci_i2c0_groups[] = { + "gpio109", "gpio110", +}; + +static const char *const cci_i2c1_groups[] = { + "gpio111", "gpio112", +}; + +static const char *const cci_i2c2_groups[] = { + "gpio113", "gpio114", +}; + +static const char *const cci_i2c3_groups[] = { + "gpio107", "gpio160", +}; + +static const char *const cci_i2c4_groups[] = { + "gpio108", "gpio149", +}; + +static const char *const cci_i2c5_groups[] = { + "gpio115", "gpio116", +}; + +static const char *const cci_timer_groups[] = { + "gpio105", "gpio106", "gpio107", "gpio159", "gpio160", +}; + +static const char *const coex_espmi_groups[] = { + "gpio144", "gpio145", +}; + +static const char *const coex_uart1_rx_groups[] = { + "gpio144", +}; + +static const char *const coex_uart1_tx_groups[] = { + "gpio145", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio82", +}; + +static const char *const ddr_bist_groups[] = { + "gpio40", "gpio41", "gpio44", "gpio45", +}; + +static const char *const ddr_pxi_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46", + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char *const dp_hot_groups[] = { + "gpio47", +}; + +static const char *const egpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio28", "gpio29", "gpio30", "gpio31", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", + "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", + "gpio207", "gpio208", "gpio209", "gpio212", "gpio213", "gpio214", + "gpio215", "gpio216", "gpio217", "gpio218", +}; + +static const char *const gcc_gp_groups[] = { + "gpio86", "gpio87", "gpio130", "gpio131", "gpio132", "gpio158", +}; + +static const char *const gnss_adc_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio77", +}; + +static const char *const host_rst_groups[] = { + "gpio106", +}; + +static const char *const i2chub0_se0_groups[] = { + "gpio66", "gpio67", +}; + +static const char *const i2chub0_se1_groups[] = { + "gpio78", "gpio79", +}; + +static const char *const i2chub0_se2_groups[] = { + "gpio68", "gpio69", +}; + +static const char *const i2chub0_se3_groups[] = { + "gpio70", "gpio71", +}; + +static const char *const i2chub0_se4_groups[] = { + "gpio72", "gpio73", +}; + +static const char *const i2s0_groups[] = { + "gpio122", "gpio123", "gpio124", "gpio125", +}; + +static const char *const i2s1_groups[] = { + "gpio117", "gpio118", "gpio119", "gpio120", +}; + +static const char *const ibi_i3c_groups[] = { + "gpio0", "gpio1", "gpio4", "gpio5", "gpio8", "gpio9", + "gpio12", "gpio13", "gpio28", "gpio29", "gpio32", "gpio33", + "gpio36", "gpio37", "gpio48", "gpio49", "gpio60", "gpio61", +}; + +static const char *const jitter_bist_groups[] = { + "gpio73", +}; + +static const char *const mdp_esync0_groups[] = { + "gpio88", "gpio100", +}; + +static const char *const mdp_esync1_groups[] = { + "gpio86", "gpio100", +}; + +static const char *const mdp_esync2_groups[] = { + "gpio87", "gpio97", +}; + +static const char *const mdp_vsync_groups[] = { + "gpio86", "gpio87", "gpio88", "gpio97", +}; + +static const char *const mdp_vsync_e_groups[] = { + "gpio98", +}; + +static const char *const mdp_vsync_p_groups[] = { + "gpio98", +}; + +static const char *const mdp_vsync0_out_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync1_out_groups[] = { + "gpio86", +}; + +static const char *const mdp_vsync2_out_groups[] = { + "gpio87", +}; + +static const char *const mdp_vsync3_out_groups[] = { + "gpio87", +}; + +static const char *const mdp_vsync5_out_groups[] = { + "gpio87", +}; + +static const char *const modem_pps_in_groups[] = { + "gpio151", +}; + +static const char *const modem_pps_out_groups[] = { + "gpio151", +}; + +static const char *const nav_gpio_groups[] = { + "gpio146", "gpio147", "gpio148", "gpio151", +}; + +static const char *const nav_gpio0_groups[] = { + "gpio150", +}; + +static const char *const nav_gpio3_groups[] = { + "gpio150", +}; + +static const char *const nav_rffe_groups[] = { + "gpio134", "gpio135", "gpio138", "gpio139", +}; + +static const char *const pcie0_clk_req_n_groups[] = { + "gpio103", +}; + +static const char *const pcie0_rst_n_groups[] = { + "gpio102", +}; + +static const char *const pcie1_clk_req_n_groups[] = { + "gpio221", +}; + +static const char *const phase_flag_groups[] = { + "gpio117", "gpio118", "gpio119", "gpio123", "gpio124", "gpio125", + "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", "gpio175", + "gpio176", "gpio179", "gpio180", "gpio181", "gpio184", "gpio185", + "gpio192", "gpio196", "gpio197", "gpio198", "gpio199", "gpio204", + "gpio206", "gpio207", "gpio208", "gpio210", "gpio211", "gpio214", + "gpio215", "gpio216", +}; + +static const char *const pll_bist_sync_groups[] = { + "gpio104", +}; + +static const char *const pll_clk_aux_groups[] = { + "gpio94", +}; + +static const char *const qdss_cti_groups[] = { + "gpio27", "gpio31", "gpio72", "gpio73", "gpio82", "gpio83", + "gpio152", "gpio158", +}; + +static const char *const qlink_groups[] = { + "gpio152", "gpio153", "gpio154", +}; + +static const char *const qspi_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio147", +}; + +static const char *const qspi_clk_groups[] = { + "gpio83", +}; + +static const char *const qspi_cs_groups[] = { + "gpio146", "gpio148", +}; + +static const char *const qup1_se0_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio83", +}; + +static const char *const qup1_se1_groups[] = { + "gpio74", "gpio75", "gpio76", "gpio77", +}; + +static const char *const qup1_se2_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio130", "gpio131", "gpio132", +}; + +static const char *const qup1_se3_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char *const qup1_se4_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char *const qup1_se5_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char *const qup1_se6_groups[] = { + "gpio56", "gpio57", "gpio58", "gpio59", +}; + +static const char *const qup1_se7_groups[] = { + "gpio60", "gpio61", "gpio62", "gpio63", +}; + +static const char *const qup2_se0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const qup2_se1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char *const qup2_se2_groups[] = { + "gpio117", "gpio118", "gpio119", "gpio120", +}; + +static const char *const qup2_se3_groups[] = { + "gpio97", "gpio122", "gpio123", "gpio124", "gpio125", +}; + +static const char *const qup2_se4_01_groups[] = { + "gpio208", "gpio209", +}; + +static const char *const qup2_se4_23_groups[] = { + "gpio208", "gpio209", +}; + +static const char *const qup3_se0_01_groups[] = { + "gpio64", "gpio65", +}; + +static const char *const qup3_se0_23_groups[] = { + "gpio64", "gpio65", +}; + +static const char *const qup3_se1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio15", +}; + +static const char *const qup3_se2_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char *const qup3_se3_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char *const qup3_se4_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char *const qup3_se5_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; + +static const char *const qup4_se0_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; + +static const char *const qup4_se1_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char *const qup4_se2_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char *const qup4_se3_01_groups[] = { + "gpio84", "gpio121", +}; + +static const char *const qup4_se3_23_groups[] = { + "gpio84", "gpio121", +}; + +static const char *const qup4_se3_l3_groups[] = { + "gpio98", +}; + +static const char *const qup4_se4_01_groups[] = { + "gpio161", "gpio162", +}; + +static const char *const qup4_se4_23_groups[] = { + "gpio161", "gpio162", +}; + +static const char *const qup4_se4_l3_groups[] = { + "gpio88", +}; + +static const char *const rng_rosc_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio84", +}; + +static const char *const sd_write_protect_groups[] = { + "gpio85", +}; + +static const char *const sdc4_clk_groups[] = { + "gpio83", +}; + +static const char *const sdc4_cmd_groups[] = { + "gpio148", +}; + +static const char *const sdc4_data_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio147", +}; + +static const char *const sys_throttle_groups[] = { + "gpio99", +}; + +static const char *const tb_trig_sdc_groups[] = { + "gpio88", "gpio146", +}; + +static const char *const tmess_rng_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio84", +}; + +static const char *const tsense_clm_groups[] = { + "gpio10", "gpio87", "gpio97", "gpio99", "gpio105", "gpio106", + "gpio159", +}; + +static const char *const tsense_pwm_groups[] = { + "gpio10", "gpio87", "gpio97", "gpio99", "gpio223", "gpio224", + "gpio225", +}; + +static const char *const uim0_groups[] = { + "gpio126", "gpio127", "gpio128", "gpio129", +}; + +static const char *const uim1_groups[] = { + "gpio36", "gpio37", "gpio39", "gpio54", "gpio55", "gpio56", + "gpio70", "gpio71", "gpio72", "gpio130", "gpio131", "gpio132", + "gpio133", +}; + +static const char *const usb0_hs_groups[] = { + "gpio79", +}; + +static const char *const usb_phy_groups[] = { + "gpio59", "gpio60", +}; + +static const char *const vfr_groups[] = { + "gpio146", "gpio151", +}; + +static const char *const vsense_trigger_mirnat_groups[] = { + "gpio59", +}; + +static const char *const wcn_sw_ctrl_groups[] = { + "gpio18", "gpio19", "gpio155", "gpio156", +}; + +static const struct pinfunction hawi_functions[] = { + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(audio_ext_mclk), + MSM_PIN_FUNCTION(audio_ref_clk), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async_in), + MSM_PIN_FUNCTION(cci_i2c0), + MSM_PIN_FUNCTION(cci_i2c1), + MSM_PIN_FUNCTION(cci_i2c2), + MSM_PIN_FUNCTION(cci_i2c3), + MSM_PIN_FUNCTION(cci_i2c4), + MSM_PIN_FUNCTION(cci_i2c5), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(coex_espmi), + MSM_PIN_FUNCTION(coex_uart1_rx), + MSM_PIN_FUNCTION(coex_uart1_tx), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist), + MSM_PIN_FUNCTION(ddr_pxi), + MSM_PIN_FUNCTION(dp_hot), + MSM_PIN_FUNCTION(egpio), + MSM_PIN_FUNCTION(gcc_gp), + MSM_PIN_FUNCTION(gnss_adc), + MSM_PIN_FUNCTION(host_rst), + MSM_PIN_FUNCTION(i2chub0_se0), + MSM_PIN_FUNCTION(i2chub0_se1), + MSM_PIN_FUNCTION(i2chub0_se2), + MSM_PIN_FUNCTION(i2chub0_se3), + MSM_PIN_FUNCTION(i2chub0_se4), + MSM_PIN_FUNCTION(i2s0), + MSM_PIN_FUNCTION(i2s1), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(mdp_esync0), + MSM_PIN_FUNCTION(mdp_esync1), + MSM_PIN_FUNCTION(mdp_esync2), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(mdp_vsync_p), + MSM_PIN_FUNCTION(mdp_vsync0_out), + MSM_PIN_FUNCTION(mdp_vsync1_out), + MSM_PIN_FUNCTION(mdp_vsync2_out), + MSM_PIN_FUNCTION(mdp_vsync3_out), + MSM_PIN_FUNCTION(mdp_vsync5_out), + MSM_PIN_FUNCTION(modem_pps_in), + MSM_PIN_FUNCTION(modem_pps_out), + MSM_PIN_FUNCTION(nav_gpio), + MSM_PIN_FUNCTION(nav_gpio0), + MSM_PIN_FUNCTION(nav_gpio3), + MSM_PIN_FUNCTION(nav_rffe), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie0_rst_n), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qlink), + MSM_PIN_FUNCTION(qspi), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qup1_se0), + MSM_PIN_FUNCTION(qup1_se1), + MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se3), + MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se5), + MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup1_se7), + MSM_PIN_FUNCTION(qup2_se0), + MSM_PIN_FUNCTION(qup2_se1), + MSM_PIN_FUNCTION(qup2_se2), + MSM_PIN_FUNCTION(qup2_se3), + MSM_PIN_FUNCTION(qup2_se4_01), + MSM_PIN_FUNCTION(qup2_se4_23), + MSM_PIN_FUNCTION(qup3_se0_01), + MSM_PIN_FUNCTION(qup3_se0_23), + MSM_PIN_FUNCTION(qup3_se1), + MSM_PIN_FUNCTION(qup3_se2), + MSM_PIN_FUNCTION(qup3_se3), + MSM_PIN_FUNCTION(qup3_se4), + MSM_PIN_FUNCTION(qup3_se5), + MSM_PIN_FUNCTION(qup4_se0), + MSM_PIN_FUNCTION(qup4_se1), + MSM_PIN_FUNCTION(qup4_se2), + MSM_PIN_FUNCTION(qup4_se3_01), + MSM_PIN_FUNCTION(qup4_se3_23), + MSM_PIN_FUNCTION(qup4_se3_l3), + MSM_PIN_FUNCTION(qup4_se4_01), + MSM_PIN_FUNCTION(qup4_se4_23), + MSM_PIN_FUNCTION(qup4_se4_l3), + MSM_PIN_FUNCTION(rng_rosc), + MSM_PIN_FUNCTION(sd_write_protect), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sdc4_data), + MSM_PIN_FUNCTION(sys_throttle), + MSM_PIN_FUNCTION(tb_trig_sdc), + MSM_PIN_FUNCTION(tmess_rng), + MSM_PIN_FUNCTION(tsense_clm), + MSM_PIN_FUNCTION(tsense_pwm), + MSM_PIN_FUNCTION(uim0), + MSM_PIN_FUNCTION(uim1), + MSM_PIN_FUNCTION(usb0_hs), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), + MSM_PIN_FUNCTION(wcn_sw_ctrl), +}; + +/* + * Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup hawi_groups[] = { + [0] = PINGROUP(0, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [1] = PINGROUP(1, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [2] = PINGROUP(2, qup2_se0, _, _, _, _, _, _, _, _, _, egpio), + [3] = PINGROUP(3, qup2_se0, _, _, _, _, _, _, _, _, _, egpio), + [4] = PINGROUP(4, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [5] = PINGROUP(5, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [6] = PINGROUP(6, qup2_se1, _, _, _, _, _, _, _, _, _, egpio), + [7] = PINGROUP(7, qup2_se1, _, _, _, _, _, _, _, _, _, egpio), + [8] = PINGROUP(8, qup3_se1, ibi_i3c, _, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, qup3_se1, ibi_i3c, _, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, qup3_se1, _, tsense_clm, tsense_pwm, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup3_se1, _, _, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup3_se2, ibi_i3c, qup3_se1, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, qup3_se2, ibi_i3c, qup3_se1, _, _, _, _, _, _, _, _), + [14] = PINGROUP(14, qup3_se2, _, _, _, _, _, _, _, _, _, _), + [15] = PINGROUP(15, qup3_se2, cci_async_in, qup3_se1, _, _, _, _, _, _, _, _), + [16] = PINGROUP(16, qup3_se3, _, _, _, _, _, _, _, _, _, _), + [17] = PINGROUP(17, qup3_se3, _, _, _, _, _, _, _, _, _, _), + [18] = PINGROUP(18, wcn_sw_ctrl, qup3_se3, _, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, wcn_sw_ctrl, qup3_se3, _, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, qup3_se4, _, _, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, qup3_se4, _, _, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, qup3_se4, _, _, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, qup3_se4, _, _, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, qup3_se5, _, _, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, qup3_se5, _, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, qup3_se5, _, _, _, _, _, _, _, _, _, _), + [27] = PINGROUP(27, qup3_se5, qdss_cti, _, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [29] = PINGROUP(29, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [30] = PINGROUP(30, qup4_se1, _, _, _, _, _, _, _, _, _, egpio), + [31] = PINGROUP(31, qup4_se1, qdss_cti, _, _, _, _, _, _, _, _, egpio), + [32] = PINGROUP(32, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, qup4_se2, _, _, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qup4_se2, _, _, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup1_se4, uim1, ibi_i3c, _, _, _, _, _, _, _, _), + [37] = PINGROUP(37, qup1_se4, uim1, ibi_i3c, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, qup1_se4, _, _, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, qup1_se4, uim1, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, qup1_se2, ddr_bist, _, gnss_adc, _, _, _, _, _, _, _), + [41] = PINGROUP(41, qup1_se2, ddr_bist, _, gnss_adc, _, _, _, _, _, _, _), + [42] = PINGROUP(42, qup1_se2, gnss_adc, _, _, _, _, _, _, _, _, _), + [43] = PINGROUP(43, qup1_se2, _, ddr_pxi, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, qup1_se3, ddr_bist, ddr_pxi, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, qup1_se3, ddr_bist, ddr_pxi, _, _, _, _, _, _, _, _), + [46] = PINGROUP(46, qup1_se3, ddr_pxi, _, _, _, _, _, _, _, _, _), + [47] = PINGROUP(47, qup1_se3, dp_hot, _, _, _, _, _, _, _, _, _), + [48] = PINGROUP(48, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [49] = PINGROUP(49, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [50] = PINGROUP(50, qup4_se0, _, _, _, _, _, _, _, _, _, egpio), + [51] = PINGROUP(51, qup4_se0, _, _, _, _, _, _, _, _, _, egpio), + [52] = PINGROUP(52, qup1_se5, ddr_pxi, _, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, qup1_se5, _, ddr_pxi, _, _, _, _, _, _, _, _), + [54] = PINGROUP(54, qup1_se5, uim1, ddr_pxi, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qup1_se5, uim1, ddr_pxi, _, _, _, _, _, _, _, _), + [56] = PINGROUP(56, qup1_se6, uim1, _, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, qup1_se6, _, _, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, qup1_se6, _, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, qup1_se6, usb_phy, vsense_trigger_mirnat, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, qup1_se7, usb_phy, ibi_i3c, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, qup1_se7, ibi_i3c, _, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, qup1_se7, _, _, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, qup1_se7, _, _, _, _, _, _, _, _, _, _), + [64] = PINGROUP(64, qup3_se0_01, qup3_se0_23, rng_rosc, tmess_rng, _, _, _, _, _, _, _), + [65] = PINGROUP(65, qup3_se0_01, qup3_se0_23, rng_rosc, tmess_rng, _, _, _, _, _, _, _), + [66] = PINGROUP(66, i2chub0_se0, rng_rosc, tmess_rng, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, i2chub0_se0, _, _, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, i2chub0_se2, _, _, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, i2chub0_se2, _, _, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, i2chub0_se3, uim1, _, atest_usb, _, _, _, _, _, _, _), + [71] = PINGROUP(71, i2chub0_se3, uim1, _, atest_usb, _, _, _, _, _, _, _), + [72] = PINGROUP(72, i2chub0_se4, uim1, qdss_cti, _, atest_usb, _, _, _, _, _, _), + [73] = PINGROUP(73, i2chub0_se4, qdss_cti, jitter_bist, atest_usb, _, _, _, _, _, _, _), + [74] = PINGROUP(74, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, qup1_se1, aoss_cti, gnss_adc, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, i2chub0_se1, _, _, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, i2chub0_se1, usb0_hs, _, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, qup1_se0, sdc4_data, qspi, _, _, _, _, _, _, _, _), + [81] = PINGROUP(81, qup1_se0, sdc4_data, qspi, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, qup1_se0, sdc4_data, qdss_cti, qspi, dbg_out_clk, _, _, _, _, _, _), + [83] = PINGROUP(83, qup1_se0, sdc4_clk, qdss_cti, qspi_clk, _, _, _, _, _, _, _), + [84] = PINGROUP(84, qup4_se3_01, qup4_se3_23, rng_rosc, tmess_rng, _, _, _, _, _, _, _), + [85] = PINGROUP(85, sd_write_protect, _, _, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_esync1, gcc_gp, + _, _, _, _, _, _), + [87] = PINGROUP(87, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out, + mdp_esync2, gcc_gp, _, tsense_clm, tsense_pwm, _, _), + [88] = PINGROUP(88, mdp_esync0, mdp_vsync, qup4_se4_l3, tb_trig_sdc, _, _, _, _, _, _, _), + [89] = PINGROUP(89, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [91] = PINGROUP(91, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, cam_mclk, pll_clk_aux, _, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, mdp_esync2, qup2_se3, mdp_vsync, tsense_clm, tsense_pwm, _, _, + _, _, _, _), + [98] = PINGROUP(98, mdp_vsync_e, qup4_se3_l3, mdp_vsync_p, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, sys_throttle, tsense_clm, tsense_pwm, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, mdp_esync1, mdp_esync0, _, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, pcie0_rst_n, _, _, _, _, _, _, _, _, _, _), + [103] = PINGROUP(103, pcie0_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, pll_bist_sync, _, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, cci_timer, tsense_clm, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, host_rst, cci_timer, tsense_clm, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, cci_i2c3, cci_timer, _, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, cci_i2c4, _, _, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, cci_i2c0, cci_async_in, _, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, cci_i2c0, cci_async_in, _, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, cci_i2c1, _, _, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, cci_i2c1, _, _, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, cci_i2c2, _, _, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, cci_i2c2, _, _, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, cci_i2c5, _, _, _, _, _, _, _, _, _, _), + [116] = PINGROUP(116, cci_i2c5, _, _, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, i2s1, qup2_se2, phase_flag, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, i2s1, qup2_se2, phase_flag, _, _, _, _, _, _, _, _), + [119] = PINGROUP(119, i2s1, qup2_se2, phase_flag, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, i2s1, qup2_se2, audio_ext_mclk, audio_ref_clk, _, _, + _, _, _, _, _), + [121] = PINGROUP(121, audio_ext_mclk, qup4_se3_01, qup4_se3_23, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, i2s0, qup2_se3, _, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, i2s0, qup2_se3, _, phase_flag, _, _, _, _, _, _, _), + [124] = PINGROUP(124, i2s0, qup2_se3, _, phase_flag, _, _, _, _, _, _, _), + [125] = PINGROUP(125, i2s0, qup2_se3, phase_flag, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, uim0, atest_char, _, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, uim0, atest_char, _, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, uim0, atest_char, _, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, uim0, atest_usb, atest_char, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, uim1, qup1_se2, gcc_gp, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, uim1, qup1_se2, gcc_gp, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, uim1, qup1_se2, gcc_gp, _, _, _, _, _, _, _, _), + [133] = PINGROUP(133, uim1, atest_char, _, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, _, _, nav_rffe, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, _, _, nav_rffe, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _, _, _), + [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, _, _, nav_rffe, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, _, _, nav_rffe, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, coex_uart1_rx, coex_espmi, _, _, _, _, _, _, _, _, _), + [145] = PINGROUP(145, coex_uart1_tx, coex_espmi, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, _, vfr, nav_gpio, tb_trig_sdc, qspi_cs, _, _, _, _, _, _), + [147] = PINGROUP(147, _, nav_gpio, sdc4_data, qspi, _, _, _, _, _, _, _), + [148] = PINGROUP(148, nav_gpio, _, sdc4_cmd, qspi_cs, _, _, _, _, _, _, _), + [149] = PINGROUP(149, cci_i2c4, _, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, nav_gpio0, nav_gpio3, _, _, _, _, _, _, _, _, _), + [151] = PINGROUP(151, nav_gpio, vfr, modem_pps_in, modem_pps_out, _, _, _, _, _, _, _), + [152] = PINGROUP(152, qlink, qdss_cti, _, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, qlink, _, _, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, qlink, _, _, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _), + [156] = PINGROUP(156, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, qdss_cti, gcc_gp, _, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, cci_timer, tsense_clm, _, _, _, _, _, _, _, _, _), + [160] = PINGROUP(160, cci_timer, cci_i2c3, _, _, _, _, _, _, _, _, _), + [161] = PINGROUP(161, qup4_se4_01, qup4_se4_23, _, _, _, _, _, _, _, _, _), + [162] = PINGROUP(162, qup4_se4_01, qup4_se4_23, _, _, _, _, _, _, _, _, _), + [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _, _, egpio), + [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _, _, egpio), + [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, egpio), + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _, _, egpio), + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _, _, egpio), + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _, _, egpio), + [169] = PINGROUP(169, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [170] = PINGROUP(170, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [171] = PINGROUP(171, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [172] = PINGROUP(172, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [173] = PINGROUP(173, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [174] = PINGROUP(174, _, _, _, _, _, _, _, _, _, _, egpio), + [175] = PINGROUP(175, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [176] = PINGROUP(176, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _, _, egpio), + [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _, _, egpio), + [179] = PINGROUP(179, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [180] = PINGROUP(180, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [181] = PINGROUP(181, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [182] = PINGROUP(182, _, _, _, _, _, _, _, _, _, _, egpio), + [183] = PINGROUP(183, _, _, _, _, _, _, _, _, _, _, egpio), + [184] = PINGROUP(184, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [185] = PINGROUP(185, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [186] = PINGROUP(186, _, _, _, _, _, _, _, _, _, _, egpio), + [187] = PINGROUP(187, _, _, _, _, _, _, _, _, _, _, egpio), + [188] = PINGROUP(188, _, _, _, _, _, _, _, _, _, _, egpio), + [189] = PINGROUP(189, _, _, _, _, _, _, _, _, _, _, egpio), + [190] = PINGROUP(190, _, _, _, _, _, _, _, _, _, _, egpio), + [191] = PINGROUP(191, _, _, _, _, _, _, _, _, _, _, egpio), + [192] = PINGROUP(192, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [193] = PINGROUP(193, _, _, _, _, _, _, _, _, _, _, egpio), + [194] = PINGROUP(194, _, _, _, _, _, _, _, _, _, _, egpio), + [195] = PINGROUP(195, _, _, _, _, _, _, _, _, _, _, egpio), + [196] = PINGROUP(196, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [197] = PINGROUP(197, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [198] = PINGROUP(198, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [199] = PINGROUP(199, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [200] = PINGROUP(200, _, _, _, _, _, _, _, _, _, _, egpio), + [201] = PINGROUP(201, _, _, _, _, _, _, _, _, _, _, egpio), + [202] = PINGROUP(202, _, _, _, _, _, _, _, _, _, _, egpio), + [203] = PINGROUP(203, _, _, _, _, _, _, _, _, _, _, egpio), + [204] = PINGROUP(204, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [205] = PINGROUP(205, _, _, _, _, _, _, _, _, _, _, egpio), + [206] = PINGROUP(206, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [207] = PINGROUP(207, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [208] = PINGROUP(208, qup2_se4_01, qup2_se4_23, phase_flag, _, _, _, _, _, _, _, egpio), + [209] = PINGROUP(209, qup2_se4_01, qup2_se4_23, _, _, _, _, _, _, _, _, egpio), + [210] = PINGROUP(210, phase_flag, _, _, _, _, _, _, _, _, _, _), + [211] = PINGROUP(211, phase_flag, _, _, _, _, _, _, _, _, _, _), + [212] = PINGROUP(212, _, _, _, _, _, _, _, _, _, _, egpio), + [213] = PINGROUP(213, _, _, _, _, _, _, _, _, _, _, egpio), + [214] = PINGROUP(214, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [215] = PINGROUP(215, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [216] = PINGROUP(216, phase_flag, _, _, _, _, _, _, _, _, _, egpio), + [217] = PINGROUP(217, _, _, _, _, _, _, _, _, _, _, egpio), + [218] = PINGROUP(218, _, _, _, _, _, _, _, _, _, _, egpio), + [219] = PINGROUP(219, _, _, _, _, _, _, _, _, _, _, _), + [220] = PINGROUP(220, _, _, _, _, _, _, _, _, _, _, _), + [221] = PINGROUP(221, pcie1_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [222] = PINGROUP(222, _, _, _, _, _, _, _, _, _, _, _), + [223] = PINGROUP(223, tsense_pwm, _, _, _, _, _, _, _, _, _, _), + [224] = PINGROUP(224, tsense_pwm, _, _, _, _, _, _, _, _, _, _), + [225] = PINGROUP(225, tsense_pwm, _, _, _, _, _, _, _, _, _, _), + [226] = UFS_RESET(ufs_reset, 0xf1004, 0xf2000), + [227] = SDC_QDSD_PINGROUP(sdc2_clk, 0xe6000, 14, 6), + [228] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xe6000, 11, 3), + [229] = SDC_QDSD_PINGROUP(sdc2_data, 0xe6000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map hawi_pdc_map[] = { + { 0, 105 }, { 3, 113 }, { 4, 106 }, { 7, 107 }, { 8, 108 }, { 11, 109 }, + { 12, 115 }, { 15, 131 }, { 16, 116 }, { 17, 141 }, { 18, 143 }, { 19, 112 }, + { 23, 117 }, { 24, 118 }, { 27, 119 }, { 28, 125 }, { 31, 126 }, { 32, 127 }, + { 35, 101 }, { 36, 128 }, { 39, 129 }, { 43, 130 }, { 47, 154 }, { 48, 135 }, + { 51, 114 }, { 55, 104 }, { 57, 136 }, { 58, 137 }, { 59, 138 }, { 60, 139 }, + { 61, 145 }, { 63, 124 }, { 64, 110 }, { 65, 123 }, { 67, 132 }, { 68, 146 }, + { 69, 147 }, { 75, 151 }, { 77, 148 }, { 78, 149 }, { 79, 155 }, { 80, 156 }, + { 81, 157 }, { 82, 158 }, { 84, 134 }, { 85, 159 }, { 86, 160 }, { 87, 161 }, + { 88, 162 }, { 95, 163 }, { 96, 164 }, { 97, 133 }, { 98, 150 }, { 99, 111 }, + { 101, 165 }, { 102, 166 }, { 103, 167 }, { 104, 168 }, { 120, 169 }, { 123, 170 }, + { 125, 171 }, { 129, 153 }, { 133, 100 }, { 144, 172 }, { 146, 173 }, { 151, 174 }, + { 152, 175 }, { 155, 122 }, { 158, 120 }, { 162, 142 }, { 164, 176 }, { 165, 177 }, + { 167, 178 }, { 168, 179 }, { 174, 180 }, { 177, 181 }, { 179, 182 }, { 183, 183 }, + { 184, 184 }, { 185, 185 }, { 186, 152 }, { 188, 144 }, { 202, 102 }, { 203, 103 }, + { 205, 140 }, { 209, 186 }, { 213, 121 }, { 216, 187 }, { 221, 188 }, { 222, 189 }, + { 223, 190 }, { 224, 191 }, { 225, 192 }, +}; + +static const struct msm_pinctrl_soc_data hawi_tlmm = { + .pins = hawi_pins, + .npins = ARRAY_SIZE(hawi_pins), + .functions = hawi_functions, + .nfunctions = ARRAY_SIZE(hawi_functions), + .groups = hawi_groups, + .ngroups = ARRAY_SIZE(hawi_groups), + .ngpios = 227, + .wakeirq_map = hawi_pdc_map, + .nwakeirq_map = ARRAY_SIZE(hawi_pdc_map), + .egpio_func = 11, +}; + +static int hawi_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &hawi_tlmm); +} + +static const struct of_device_id hawi_tlmm_of_match[] = { + { .compatible = "qcom,hawi-tlmm", }, + {}, +}; + +static struct platform_driver hawi_tlmm_driver = { + .driver = { + .name = "hawi-tlmm", + .of_match_table = hawi_tlmm_of_match, + }, + .probe = hawi_tlmm_probe, +}; + +static int __init hawi_tlmm_init(void) +{ + return platform_driver_register(&hawi_tlmm_driver); +} +arch_initcall(hawi_tlmm_init); + +static void __exit hawi_tlmm_exit(void) +{ + platform_driver_unregister(&hawi_tlmm_driver); +} +module_exit(hawi_tlmm_exit); + +MODULE_DESCRIPTION("QTI Hawi TLMM driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, hawi_tlmm_of_match);