loanchen f88192d233 drm/amd/display: Correct register address in dcn35 ... [Why] the offset address of mmCLK5_spll_field_8 was incorrect for dcn35 which causes SSC not to be enabled. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Lo-An Chen <lo-an.chen@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org		2025-01-28 16:23:30 -05:00
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amdgpu_dm	drm/amd/display: Fix error pointers in amdgpu_dm_crtc_mem_type_changed	2025-01-24 09:55:19 -05:00
dc	drm/amd/display: Correct register address in dcn35	2025-01-28 16:23:30 -05:00
dmub	drm/amd/display: [FW Promotion] Release 0.0.248.0	2025-01-10 12:00:01 -05:00
include	drm/amd/display: Remove last parts of timing_trace	2024-11-04 11:26:36 -05:00
modules	drm/amd/display: Revised for Replay Pseudo vblank control	2025-01-10 12:11:38 -05:00
Kconfig	drm/amd/display: add CEC notifier to amdgpu driver	2025-01-10 11:58:57 -05:00
Makefile	drm/amd/display: Refactor DCN3X into component folder	2024-06-14 16:18:55 -04:00