loanchen f88192d233 drm/amd/display: Correct register address in dcn35 ... [Why] the offset address of mmCLK5_spll_field_8 was incorrect for dcn35 which causes SSC not to be enabled. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Lo-An Chen <lo-an.chen@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org		2025-01-28 16:23:30 -05:00
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drm	drm/amd/display: Correct register address in dcn35	2025-01-28 16:23:30 -05:00
host1x	Get rid of 'remove_new' relic from platform driver struct	2024-12-01 15:12:43 -08:00
ipu-v3	Get rid of 'remove_new' relic from platform driver struct	2024-12-01 15:12:43 -08:00
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