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drm/amd/display: Remove last parts of timing_trace

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Commit c2c2ce1e96 ("drm/amd/display: Optimize passive update planes.")
removed the last caller of context_timing_trace.
Remove it.

With that gone, no one is now looking at the 'timing_trace' flag, remove
it and all the places that set it.

Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dr. David Alan Gilbert 2024-10-10 21:51:54 +01:00 committed by Alex Deucher
parent 8b89acc0b2
commit 5fd95dab60
20 changed files with 0 additions and 65 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
drivers/gpu/drm/amd/display/dc/core/dc_debug.c
View File

@ -46,11 +46,6 @@
DC_LOG_IF_TRACE(__VA_ARGS__); \
} while (0)
#define TIMING_TRACE(...) do {\
if (dc->debug.timing_trace) \
DC_LOG_SYNC(__VA_ARGS__); \
} while (0)
#define CLOCK_TRACE(...) do {\
if (dc->debug.clock_trace) \
DC_LOG_BANDWIDTH_CALCS(__VA_ARGS__); \
@ -306,43 +301,6 @@ void post_surface_trace(struct dc *dc)
}
void context_timing_trace(
struct dc *dc,
struct resource_context *res_ctx)
{
int i;
int h_pos[MAX_PIPES] = {0}, v_pos[MAX_PIPES] = {0};
struct crtc_position position;
unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
DC_LOGGER_INIT(dc->ctx->logger);
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
/* get_position() returns CRTC vertical/horizontal counter
* hence not applicable for underlay pipe
*/
if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx)
continue;
pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position);
h_pos[i] = position.horizontal_count;
v_pos[i] = position.vertical_count;
}
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx)
continue;
TIMING_TRACE("OTG_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n",
pipe_ctx->stream_res.tg->inst,
pipe_ctx->stream->timing.h_total,
pipe_ctx->stream->timing.v_total,
h_pos[i], v_pos[i]);
}
}
void context_clock_trace(
struct dc *dc,
struct dc_state *context)

1
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -868,7 +868,6 @@ struct dc_debug_options {
bool sanity_checks;
bool max_disp_clk;
bool surface_trace;
bool timing_trace;
bool clock_trace;
bool validation_trace;
bool bandwidth_calcs_trace;

2
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
View File

@ -533,7 +533,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.sanity_checks = true,
.disable_dmcu = false,
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
/* raven smu dones't allow 0 disp clk,
@ -563,7 +562,6 @@ static const struct dc_debug_options debug_defaults_drv = {
static const struct dc_debug_options debug_defaults_diags = {
.disable_dmcu = false,
.force_abm_enable = false,
.timing_trace = true,
.clock_trace = true,
.disable_stutter = true,
.disable_pplib_clock_request = true,

1
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
View File

@ -706,7 +706,6 @@ static const struct resource_caps res_cap_nv14 = {
static const struct dc_debug_options debug_defaults_drv = {
.disable_dmcu = false,
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = true,
.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,

1
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
View File

@ -600,7 +600,6 @@ static const struct dc_plane_cap plane_cap = {
static const struct dc_debug_options debug_defaults_drv = {
.disable_dmcu = true,
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = true,
.pipe_split_policy = MPC_SPLIT_DYNAMIC,

1
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
View File

@ -610,7 +610,6 @@ static const struct dc_plane_cap plane_cap = {
static const struct dc_debug_options debug_defaults_drv = {
.disable_dmcu = false,
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = true,
.min_disp_clk_khz = 100000,

1
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
View File

@ -711,7 +711,6 @@ static const struct dc_plane_cap plane_cap = {
static const struct dc_debug_options debug_defaults_drv = {
.disable_dmcu = true, //No DMCU on DCN30
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = true,
.pipe_split_policy = MPC_SPLIT_DYNAMIC,

1
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
View File

@ -682,7 +682,6 @@ static const struct dc_plane_cap plane_cap = {
static const struct dc_debug_options debug_defaults_drv = {
.disable_dmcu = true,
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
.disable_dpp_power_gate = false,
.disable_hubp_power_gate = false,

1
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
View File

@ -81,7 +81,6 @@
static const struct dc_debug_options debug_defaults_drv = {
.disable_dmcu = true,
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = true,
.pipe_split_policy = MPC_SPLIT_DYNAMIC,

1
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
View File

@ -82,7 +82,6 @@
static const struct dc_debug_options debug_defaults_drv = {
.disable_dmcu = true,
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = true,
.pipe_split_policy = MPC_SPLIT_AVOID,

1
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
View File

@ -858,7 +858,6 @@ static const struct dc_plane_cap plane_cap = {
static const struct dc_debug_options debug_defaults_drv = {
.disable_dmcu = true,
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = false,
.pipe_split_policy = MPC_SPLIT_DYNAMIC,

1
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
View File

@ -876,7 +876,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.replay_skip_crtc_disabled = true,
.disable_dmcu = true,
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
.disable_dpp_power_gate = false,
.disable_hubp_power_gate = false,

1
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
View File

@ -858,7 +858,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.disable_z10 = true, /*hw not support it*/
.disable_dmcu = true,
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = false,
.pipe_split_policy = MPC_SPLIT_DYNAMIC,

1
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
View File

@ -853,7 +853,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.disable_z10 = true, /*hw not support it*/
.disable_dmcu = true,
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = false,
.pipe_split_policy = MPC_SPLIT_DYNAMIC,

1
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
View File

@ -689,7 +689,6 @@ static const struct dc_plane_cap plane_cap = {
static const struct dc_debug_options debug_defaults_drv = {
.disable_dmcu = true,
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = false,
.pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore

1
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
View File

@ -686,7 +686,6 @@ static const struct dc_plane_cap plane_cap = {
static const struct dc_debug_options debug_defaults_drv = {
.disable_dmcu = true,
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = false,
.pipe_split_policy = MPC_SPLIT_AVOID,

1
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
View File

@ -712,7 +712,6 @@ static const struct dc_plane_cap plane_cap = {
static const struct dc_debug_options debug_defaults_drv = {
.disable_dmcu = true,
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = false,
.pipe_split_policy = MPC_SPLIT_AVOID,

1
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
View File

@ -692,7 +692,6 @@ static const struct dc_plane_cap plane_cap = {
static const struct dc_debug_options debug_defaults_drv = {
.disable_dmcu = true,
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = false,
.pipe_split_policy = MPC_SPLIT_AVOID,

1
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
View File

@ -685,7 +685,6 @@ static const struct dc_plane_cap plane_cap = {
static const struct dc_debug_options debug_defaults_drv = {
.disable_dmcu = true,
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = false,
.pipe_split_policy = MPC_SPLIT_AVOID,

4
drivers/gpu/drm/amd/display/include/logger_interface.h
View File

@ -52,10 +52,6 @@ void update_surface_trace(
void post_surface_trace(struct dc *dc);
void context_timing_trace(
struct dc *dc,
struct resource_context *res_ctx);
void context_clock_trace(
struct dc *dc,
struct dc_state *context);