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2ac2fe765e
dcn30_apply_idle_power_optimizations() derives the MALL frame cache hysteresis timer with tmr_delay = (uint32_t)(div_u64(..., denom) - 64LL); div_u64() returns a u64, so when the quotient is smaller than 64 the subtraction wraps instead of going negative and tmr_delay ends up huge. The loop that follows tries to squeeze it into the 6 bit register field by doubling denom, but that only makes the quotient smaller, so tmr_delay can never converge. tmr_scale is bumped past 3 and the function gives up with /* Delay exceeds range of hysteresis timer */ ASSERT(false); even though the requested delay is too *short* to encode, not too long. With mall_additional_timer_percent left at its default of 0, the quotient drops below 64 once the refresh rate used for the calculation goes above ~243 Hz. Every DCN 3.0 display above that loses MALL static screen entirely and splats a WARN once per boot. Reproduced on Navi 23 (RX 6600) driving 1920x1080, resetting /sys/kernel/debug/clear_warn_once between modes: refresh MALL ASSERT 144 Hz enabled no 240 Hz enabled no 280 Hz skipped yes 360 Hz skipped yes Commit |
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| .. | ||
| dce | ||
| dce60 | ||
| dce80 | ||
| dce100 | ||
| dce110 | ||
| dce112 | ||
| dce120 | ||
| dcn10 | ||
| dcn20 | ||
| dcn21 | ||
| dcn30 | ||
| dcn31 | ||
| dcn32 | ||
| dcn35 | ||
| dcn42 | ||
| dcn42b | ||
| dcn50 | ||
| dcn60 | ||
| dcn201 | ||
| dcn301 | ||
| dcn302 | ||
| dcn303 | ||
| dcn314 | ||
| dcn351 | ||
| dcn401 | ||
| hw_sequencer_private.h | ||
| hw_sequencer.h | ||
| Makefile | ||