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drm/amd/display: Add DCN42B DC resource files

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[Why & How]
Add DC resource files for DCN42B.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Matthew Stewart 2026-05-17 20:07:20 -04:00 committed by Alex Deucher
parent 1a1751507e
commit a3d3758b2e
12 changed files with 4423 additions and 0 deletions
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483
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c Normal file
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/*
* SPDX-License-Identifier: MIT
*
* Copyright 2026 Advanced Micro Devices, Inc.
*/
#include "dcn42b_clk_mgr.h"
#include "dccg.h"
#include "clk_mgr_internal.h"
// For dce12_get_dp_ref_freq_khz
#include "dce100/dce_clk_mgr.h"
// For dcn20_update_clocks_update_dpp_dto
#include "dcn20/dcn20_clk_mgr.h"
#include "reg_helper.h"
#include "core_types.h"
#include "dcn42/dcn42_smu.h"
#include "dcn42/dcn42_clk_mgr.h"
#include "dm_helpers.h"
/* TODO: remove this include once we ported over remaining clk mgr functions*/
#include "dcn30/dcn30_clk_mgr.h"
#include "dcn31/dcn31_clk_mgr.h"
#include "dcn35/dcn35_clk_mgr.h"
#include "dc_dmub_srv.h"
#include "link_service.h"
#include "logger_types.h"
#include "clk/clk_15_0_5_offset.h"
#include "clk/clk_15_0_5_sh_mask.h"
#include "dcn/dcn_4_2_1_offset.h"
#include "dcn/dcn_4_2_1_sh_mask.h"
#define DCN_BASE__INST0_SEG0 0x00000012
#define DCN_BASE__INST0_SEG1 0x000000C0
#undef DC_LOGGER
#define DC_LOGGER \
dc_logger
#define DC_LOGGER_INIT(logger) \
struct dal_logger *dc_logger = logger
#define mmCLK5_CLK_TICK_CNT_CONFIG_REG 0x1B229
#define mmCLK5_CLK0_CURRENT_CNT 0x1B22B //DISPCLK
#define mmCLK5_CLK1_CURRENT_CNT 0x1B22C //DPPCLK
#define mmCLK5_CLK2_CURRENT_CNT 0x1B22D //DPREFCLK
#define mmCLK5_CLK3_CURRENT_CNT 0x1B22E //DCFCLK
#define mmCLK5_CLK0_DS_CNTL 0x1B204
#define mmCLK5_CLK1_DS_CNTL 0x1B20C
#define mmCLK5_CLK2_DS_CNTL 0x1B214
#define mmCLK5_CLK3_DS_CNTL 0x1B21C
#define mmCLK5_CLK0_BYPASS_CNTL 0x1B20A
#define mmCLK5_CLK1_BYPASS_CNTL 0x1B212
#define mmCLK5_CLK2_BYPASS_CNTL 0x1B21A
#define mmCLK5_CLK3_BYPASS_CNTL 0x1B222
#undef FN
#define FN(reg_name, field_name) \
clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
#define REG(reg) \
(clk_mgr->regs->reg)
#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
#define BASE(seg) BASE_INNER(seg)
#define SR(reg_name)\
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
reg ## reg_name
#define CLK_SR_DCN42B(reg_name)\
.reg_name = mm ## reg_name
static const struct clk_mgr_registers clk_mgr_regs_dcn42b = {
CLK_REG_LIST_DCN42B()
};
static const struct clk_mgr_shift clk_mgr_shift_dcn42b = {
CLK_COMMON_MASK_SH_LIST_DCN42B(__SHIFT)
};
static const struct clk_mgr_mask clk_mgr_mask_dcn42b = {
CLK_COMMON_MASK_SH_LIST_DCN42B(_MASK)
};
#define TO_CLK_MGR_DCN42B(clk_mgr_int)\
container_of(clk_mgr_int, struct clk_mgr_dcn42, base)
static void dcn42b_dump_clk_registers_internal(struct dcn42b_clk_internal *internal, struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
REG_GET(CLK5_CLK_TICK_CNT_CONFIG_REG, TIMER_THRESHOLD, &internal->CLK5_CLK_TICK_CNT__TIMER_THRESHOLD);
// read dcf deep sleep divider
internal->CLK5_CLK0_DS_CNTL = REG_READ(CLK5_CLK0_DS_CNTL);
internal->CLK5_CLK3_DS_CNTL = REG_READ(CLK5_CLK3_DS_CNTL);
// read dispclk
internal->CLK5_CLK0_CURRENT_CNT = dcn42b_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dispclk);
internal->CLK5_CLK0_BYPASS_CNTL = REG_READ(CLK5_CLK0_BYPASS_CNTL);
// read dppclk
internal->CLK5_CLK1_CURRENT_CNT = dcn42b_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dppclk);
internal->CLK5_CLK1_BYPASS_CNTL = REG_READ(CLK5_CLK1_BYPASS_CNTL);
// read dprefclk
internal->CLK5_CLK2_CURRENT_CNT = dcn42b_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dprefclk);
internal->CLK5_CLK2_BYPASS_CNTL = REG_READ(CLK5_CLK2_BYPASS_CNTL);
// read dcfclk
internal->CLK5_CLK3_CURRENT_CNT = dcn42b_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dcfclk);
internal->CLK5_CLK3_BYPASS_CNTL = REG_READ(CLK5_CLK3_BYPASS_CNTL);
/* read dtbclk - DTBCLK tied off in DCN42B
* internal->CLK5_CLK4_CURRENT_CNT = REG_READ(CLK5_CLK4_CURRENT_CNT) / ratio;
* internal->CLK5_CLK4_BYPASS_CNTL = REG_READ(CLK5_CLK4_BYPASS_CNTL);
*/
}
static void dcn42b_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
struct clk_mgr_dcn42 *clk_mgr)
{
struct dcn42b_clk_internal internal = {0};
char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
DC_LOGGER_INIT(clk_mgr->base.base.ctx->logger);
(void)dc_logger;
dcn42b_dump_clk_registers_internal(&internal, &clk_mgr->base.base);
regs_and_bypass->timer_threshold = internal.CLK5_CLK_TICK_CNT__TIMER_THRESHOLD;
regs_and_bypass->dcfclk = internal.CLK5_CLK3_CURRENT_CNT / 10;
regs_and_bypass->dcf_deep_sleep_divider = internal.CLK5_CLK3_DS_CNTL / 10;
regs_and_bypass->dcf_deep_sleep_allow = internal.CLK5_CLK3_DS_CNTL & 0x10; /*bit 4: CLK0_ALLOW_DS*/
regs_and_bypass->dprefclk = internal.CLK5_CLK2_CURRENT_CNT / 10;
regs_and_bypass->dispclk = internal.CLK5_CLK0_CURRENT_CNT / 10;
regs_and_bypass->dppclk = internal.CLK5_CLK1_CURRENT_CNT / 10;
/* regs_and_bypass->dtbclk = internal.CLK5_CLK4_CURRENT_CNT / 10; */ /* DTBCLK tied off in DCN42B */
regs_and_bypass->dispclk_bypass = get_reg_field_value(internal.CLK5_CLK0_BYPASS_CNTL, CLK5_CLK0_BYPASS_CNTL, CLK0_BYPASS_SEL);
regs_and_bypass->dppclk_bypass = get_reg_field_value(internal.CLK5_CLK1_BYPASS_CNTL, CLK5_CLK1_BYPASS_CNTL, CLK1_BYPASS_SEL);
regs_and_bypass->dprefclk_bypass = get_reg_field_value(internal.CLK5_CLK2_BYPASS_CNTL, CLK5_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL);
regs_and_bypass->dcfclk_bypass = get_reg_field_value(internal.CLK5_CLK3_BYPASS_CNTL, CLK5_CLK3_BYPASS_CNTL, CLK3_BYPASS_SEL);
if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
DC_LOG_SMU("clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
DC_LOG_SMU("dcfclk,%d,%d,%d,%s\n",
regs_and_bypass->dcfclk,
regs_and_bypass->dcf_deep_sleep_divider,
regs_and_bypass->dcf_deep_sleep_allow,
bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
DC_LOG_SMU("dprefclk,%d,N/A,N/A,%s\n",
regs_and_bypass->dprefclk,
bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
DC_LOG_SMU("dispclk,%d,N/A,N/A,%s\n",
regs_and_bypass->dispclk,
bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
//split
DC_LOG_SMU("SPLIT\n");
// REGISTER VALUES
DC_LOG_SMU("reg_name,value,clk_type\n");
DC_LOG_SMU("CLK5_CLK3_CURRENT_CNT,%d,dcfclk\n",
internal.CLK5_CLK3_CURRENT_CNT);
DC_LOG_SMU("CLK5_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
internal.CLK5_CLK3_DS_CNTL);
DC_LOG_SMU("CLK5_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n",
(internal.CLK5_CLK3_DS_CNTL & 0x10));
DC_LOG_SMU("CLK5_CLK2_CURRENT_CNT,%d,dprefclk\n",
internal.CLK5_CLK2_CURRENT_CNT);
DC_LOG_SMU("CLK5_CLK0_CURRENT_CNT,%d,dispclk\n",
internal.CLK5_CLK0_CURRENT_CNT);
DC_LOG_SMU("CLK5_CLK1_CURRENT_CNT,%d,dppclk\n",
internal.CLK5_CLK1_CURRENT_CNT);
DC_LOG_SMU("CLK5_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n",
internal.CLK5_CLK3_BYPASS_CNTL);
DC_LOG_SMU("CLK5_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n",
internal.CLK5_CLK2_BYPASS_CNTL);
DC_LOG_SMU("CLK5_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n",
internal.CLK5_CLK0_BYPASS_CNTL);
DC_LOG_SMU("CLK5_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n",
internal.CLK5_CLK1_BYPASS_CNTL);
}
}
static void init_clk_states(struct clk_mgr *clk_mgr)
{
/*
* DTBCLK is tied off in DCN42B - no save/restore needed
* uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;
*/
memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
clk_mgr->clks.dtbclk_en = false; /* DTBCLK tied off in DCN42B */
clk_mgr->clks.ref_dtbclk_khz = 0;
clk_mgr->clks.p_state_change_support = true;
clk_mgr->clks.prev_p_state_change_support = true;
clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
}
/* dcn42b_get_dpm_table_from_smu removed: reuse dcn42_get_dpm_table_from_smu.
* Function is identical - only uses SMU calls, no hardware register differences.
*/
void dcn42b_init_clocks(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr_base);
struct clk_mgr_dcn42 *clk_mgr = TO_CLK_MGR_DCN42B(clk_mgr_int);
DC_LOGGER_INIT(clk_mgr_base->ctx->logger);
(void)dc_logger;
init_clk_states(clk_mgr_base);
// to adjust dp_dto reference clock if ssc is enable otherwise to apply dprefclk
if (dcn42_is_spll_ssc_enabled(clk_mgr_base))
clk_mgr_base->dp_dto_source_clock_in_khz =
dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr_base->dprefclk_khz);
else
clk_mgr_base->dp_dto_source_clock_in_khz = clk_mgr_base->dprefclk_khz;
DC_LOG_SMU("dp_dto_source_clock %d, dprefclk %d\n", clk_mgr_base->dp_dto_source_clock_in_khz, clk_mgr_base->dprefclk_khz);
dcn42b_dump_clk_registers(&clk_mgr_base->boot_snapshot, clk_mgr);
}
static struct clk_bw_params dcn42b_bw_params = {
.vram_type = Ddr4MemType,
.num_channels = 1,
.clk_table = {
.num_entries = 4,
},
};
static struct wm_table ddr5_wm_table = {
.entries = {
{
.wm_inst = WM_A,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72,
.sr_exit_time_us = 28.0,
.sr_enter_plus_exit_time_us = 30.0,
.valid = true,
},
{
.wm_inst = WM_B,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72,
.sr_exit_time_us = 28.0,
.sr_enter_plus_exit_time_us = 30.0,
.valid = true,
},
{
.wm_inst = WM_C,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72,
.sr_exit_time_us = 28.0,
.sr_enter_plus_exit_time_us = 30.0,
.valid = true,
},
{
.wm_inst = WM_D,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.72,
.sr_exit_time_us = 28.0,
.sr_enter_plus_exit_time_us = 30.0,
.valid = true,
},
}
};
static struct wm_table lpddr5_wm_table = {
.entries = {
{
.wm_inst = WM_A,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
.sr_exit_time_us = 28.0,
.sr_enter_plus_exit_time_us = 30.0,
.valid = true,
},
{
.wm_inst = WM_B,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
.sr_exit_time_us = 28.0,
.sr_enter_plus_exit_time_us = 30.0,
.valid = true,
},
{
.wm_inst = WM_C,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
.sr_exit_time_us = 28.0,
.sr_enter_plus_exit_time_us = 30.0,
.valid = true,
},
{
.wm_inst = WM_D,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
.sr_exit_time_us = 28.0,
.sr_enter_plus_exit_time_us = 30.0,
.valid = true,
},
}
};
static void dcn42b_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)
{
uint32_t clock_source;
clock_source = (REG_READ(CLK5_CLK2_BYPASS_CNTL) & CLK5_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK);
// If it's DFS mode, clock_source is 0.
if (dcn42_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(dcn42_ss_info_table.ss_percentage))) {
clk_mgr->dprefclk_ss_percentage = dcn42_ss_info_table.ss_percentage[clock_source];
if (clk_mgr->dprefclk_ss_percentage != 0) {
clk_mgr->ss_on_dprefclk = true;
clk_mgr->dprefclk_ss_divider = dcn42_ss_info_table.ss_divider;
}
}
}
uint32_t dcn42b_get_clock_freq_from_clkip(struct clk_mgr *clk_mgr_base, enum clock_type clock)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
uint64_t clock_freq_mhz = 0;
uint32_t timer_threshold = 0;
// always safer to read the timer threshold instead of using cached value
REG_GET(CLK5_CLK_TICK_CNT_CONFIG_REG, TIMER_THRESHOLD, &timer_threshold);
if (timer_threshold == 0) {
BREAK_TO_DEBUGGER();
return 0;
}
switch (clock) {
case clock_type_dispclk:
clock_freq_mhz = REG_READ(CLK5_CLK0_CURRENT_CNT);
break;
case clock_type_dppclk:
clock_freq_mhz = REG_READ(CLK5_CLK1_CURRENT_CNT);
break;
case clock_type_dprefclk:
clock_freq_mhz = REG_READ(CLK5_CLK2_CURRENT_CNT);
break;
case clock_type_dcfclk:
clock_freq_mhz = REG_READ(CLK5_CLK3_CURRENT_CNT);
break;
case clock_type_dtbclk:
/* DTBCLK tied off in DCN42B - CLK5_CLK4 register doesn't exist.
* Should never be called since dtbclk_en is always false.
*/
ASSERT(false);
clock_freq_mhz = 0;
break;
default:
break;
}
clock_freq_mhz *= DCN42_CLKIP_REFCLK;
clock_freq_mhz = div_u64(clock_freq_mhz, timer_threshold);
// there are no DCN clocks over 0xFFFFFFFF MHz
ASSERT(clock_freq_mhz <= 0xFFFFFFFF);
return (uint32_t)clock_freq_mhz;
}
/* dcn42b_get_dispclk_from_dentist removed: reuse dcn42_get_dispclk_from_dentist.
* DENTIST_DISPCLK_CNTL is a DCN register with the same offset on both dcn42 and dcn42b.
*/
static struct clk_mgr_funcs dcn42b_funcs = {
.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
.update_clocks = dcn42_update_clocks,
.init_clocks = dcn42b_init_clocks,
.enable_pme_wa = dcn42_enable_pme_wa,
.are_clock_states_equal = dcn42_are_clock_states_equal,
.notify_wm_ranges = NULL,
.set_low_power_state = dcn42_set_low_power_state,
.exit_low_power_state = dcn42_exit_low_power_state,
.get_max_clock_khz = dcn42_get_max_clock_khz,
.get_dispclk_from_dentist = dcn42_get_dispclk_from_dentist,
.is_smu_present = dcn42_is_smu_present,
};
void dcn42b_clk_mgr_construct(
struct dc_context *ctx,
struct clk_mgr_dcn42 *clk_mgr,
struct pp_smu_funcs *pp_smu,
struct dccg *dccg)
{
clk_mgr->base.base.ctx = ctx;
clk_mgr->base.base.funcs = &dcn42b_funcs;
clk_mgr->base.regs = &clk_mgr_regs_dcn42b;
clk_mgr->base.clk_mgr_shift = &clk_mgr_shift_dcn42b;
clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn42b;
clk_mgr->base.pp_smu = pp_smu;
clk_mgr->base.dccg = dccg;
clk_mgr->base.dfs_bypass_disp_clk = 0;
clk_mgr->base.dprefclk_ss_percentage = 0;
clk_mgr->base.dprefclk_ss_divider = 1000;
clk_mgr->base.ss_on_dprefclk = false;
clk_mgr->base.dfs_ref_freq_khz = 48000; /*sync with pmfw*/
clk_mgr->base.base.clks.ref_dtbclk_khz = 0;
/* Changed from DCN3.2_clock_frequency doc to match
* dcn32_dump_clk_registers from 4 * dentist_vco_freq_khz /
* dprefclk DID divider
*/
clk_mgr->base.base.dprefclk_khz = 600000;
clk_mgr->base.smu_present = false;
clk_mgr->base.smu_ver = dcn42_smu_get_pmfw_version(&clk_mgr->base);
if (clk_mgr->base.smu_ver && clk_mgr->base.smu_ver != -1)
clk_mgr->base.smu_present = true;
if (ctx->dc_bios->integrated_info) {
clk_mgr->base.base.dentist_vco_freq_khz = ctx->dc_bios->integrated_info->dentist_vco_freq;
if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType)
dcn42b_bw_params.wm_table = lpddr5_wm_table;
else
dcn42b_bw_params.wm_table = ddr5_wm_table;
dcn42b_bw_params.vram_type = ctx->dc_bios->integrated_info->memory_type;
dcn42b_bw_params.dram_channel_width_bytes = ctx->dc_bios->integrated_info->memory_type == 0x22 ? 8 : 4;
dcn42b_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 2;
if (clk_mgr->base.smu_present)
clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base);
}
/* in case we don't get a value from the BIOS, use default */
if (clk_mgr->base.base.dentist_vco_freq_khz == 0)
clk_mgr->base.base.dentist_vco_freq_khz = 3000000; /* 3000MHz */
/* Saved clocks configured at boot for debug purposes */
dcn42b_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr);
dce_clock_read_ss_info(&clk_mgr->base);
/*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/
dcn42b_read_ss_info_from_lut(&clk_mgr->base);
clk_mgr->base.base.bw_params = &dcn42b_bw_params;
if (clk_mgr->base.smu_present) {
dcn42_get_smu_clocks(&clk_mgr->base);
//overwrite values from dcn42_get_smu_clocks since dtbclk is tied off in DCN42B
clk_mgr->base.base.bw_params->clk_table.entries[0].dtbclk_mhz = 0;
clk_mgr->base.base.bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels = 0;
clk_mgr->base.base.clks.ref_dtbclk_khz = 0;
}
}

48
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.h Normal file
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// SPDX-License-Identifier: MIT
//
// Copyright 2026 Advanced Micro Devices, Inc.
#ifndef __DCN42B_CLK_MGR_H__
#define __DCN42B_CLK_MGR_H__
#include "clk_mgr_internal.h"
#include "dcn42/dcn42_clk_mgr.h"
/* DCN42B reuses the following from DCN42:
* - dcn42_update_clocks (dtbclk_en=false so all dtbclk branches are skipped)
* - dcn42_get_dispclk_from_dentist (DENTIST_DISPCLK_CNTL has same DCN offset)
* - dcn42_get_dpm_table_from_smu (identical, only SMU calls)
* - dcn42_are_clock_states_equal
* - dcn42_enable_pme_wa
* - dcn42_update_clocks_update_dpp_dto
* - dcn42_update_clocks_update_dtb_dto
* - dcn42_build_watermark_ranges
* - dcn42_is_spll_ssc_enabled
* - dcn42_has_active_display
* - dcn42_notify_wm_ranges
* - dcn42_set_low_power_state
* - dcn42_exit_low_power_state
* - dcn42_get_max_clock_khz
* - dcn42_is_smu_present
*
* CANNOT reuse from DCN42 (hardware register differences):
* - dcn42_read_ss_info_from_lut (CLK8 vs CLK5 registers)
* - dcn42_dump_clk_registers* (CLK8 vs CLK5 registers)
* - dcn42_get_clock_freq_from_clkip (CLK8 vs CLK5 registers)
* - dcn42_init_clocks (calls CLK8-specific functions, dtbclk logic)
* - init_clk_states (dtbclk_en difference: true for dcn42, false for dcn42b)
*
* See dcn42_clk_mgr.h for declarations
*/
#define NUM_CLOCK_SOURCES 5
void dcn42b_init_clocks(struct clk_mgr *clk_mgr);
void dcn42b_clk_mgr_construct(struct dc_context *ctx,
struct clk_mgr_dcn42 *clk_mgr,
struct pp_smu_funcs *pp_smu,
struct dccg *dccg);
uint32_t dcn42b_get_clock_freq_from_clkip(struct clk_mgr *clk_mgr_base,
enum clock_type clock);
#endif //__DCN42B_CLK_MGR_H__

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// SPDX-License-Identifier: MIT
//
// Copyright 2026 Advanced Micro Devices, Inc.
#include "dm_services.h"
#include "include/gpio_types.h"
#include "../hw_factory.h"
#include "../hw_gpio.h"
#include "../hw_ddc.h"
#include "../hw_hpd.h"
#include "../hw_generic.h"
#include "dcn/dcn_4_2_1_offset.h"
#include "dcn/dcn_4_2_1_sh_mask.h"
#include "dpcs/dpcs_4_0_1_offset.h"
#include "dpcs/dpcs_4_0_1_sh_mask.h"
#include "reg_helper.h"
#include "../hpd_regs.h"
#include "hw_factory_dcn42b.h"
#define DCN_BASE__INST0_SEG2 0x000034C0
/* DCN */
#define block HPD
#define reg_num 0
#undef BASE_INNER
#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
#define BASE(seg) BASE_INNER(seg)
#define REG(reg_name) \
BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
#define SF_HPD(reg_name, field_name, post_fix) \
.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
#define REGI(reg_name, block, id) \
BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
reg ## block ## id ## _ ## reg_name
#define SF(reg_name, field_name, post_fix) \
.field_name = reg_name ## __ ## field_name ## post_fix
/* macros to expend register list macro defined in HW object header file
* end *********************/
#undef HPD_REG_LIST
#define HPD_REG_LIST(id) \
.int_status = REGI(DC_HPD_INT_STATUS, HPD, id), \
.toggle_filt_cntl = REGI(DC_HPD_TOGGLE_FILT_CNTL, HPD, id)
#define hpd_regs(id) \
{ \
HPD_REG_LIST(id) \
}
static const struct hpd_registers hpd_regs[] = {
hpd_regs(0),
hpd_regs(1),
hpd_regs(2),
//hpd_regs(3),
//hpd_regs(4),
};
static const struct hpd_sh_mask hpd_shift = {
HPD_MASK_SH_LIST(__SHIFT)
};
static const struct hpd_sh_mask hpd_mask = {
HPD_MASK_SH_LIST(_MASK)
};
#include "../ddc_regs.h"
#define SF_DDC(reg_name, field_name, post_fix) \
.field_name = reg_name ## __ ## field_name ## post_fix
static const struct ddc_registers ddc_data_regs_dcn[] = {
{
// add a dummy entry for cases no such port
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
},
{
// add a dummy entry for cases no such port
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
},
{
// add a dummy entry for cases no such port
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
},
{
// add a dummy entry for cases no such port
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
},
{
// add a dummy entry for cases no such port
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
},
{
// add a dummy entry for cases no such port
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
},
{
// add a dummy entry for cases no such port
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
},
{
DDC_GPIO_VGA_REG_LIST(DATA),
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
}
};
static const struct ddc_registers ddc_clk_regs_dcn[] = {
{
// add a dummy entry for cases no such port
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
},
{
// add a dummy entry for cases no such port
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
},
{
// add a dummy entry for cases no such port
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
},
{
// add a dummy entry for cases no such port
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
},
{
// add a dummy entry for cases no such port
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
},
{
// add a dummy entry for cases no such port
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
},
{
DDC_GPIO_VGA_REG_LIST(CLK),
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
}
};
//static const struct ddc_sh_mask ddc_shift[] = {
//DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),
//DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),
//DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
//DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
//DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
//DDC_MASK_SH_LIST_DCN2(__SHIFT, 6),
//DDC_MASK_SH_LIST_DCN2_VGA(__SHIFT)
//};
//static const struct ddc_sh_mask ddc_mask[] = {
//DDC_MASK_SH_LIST_DCN2(_MASK, 1),
//DDC_MASK_SH_LIST_DCN2(_MASK, 2),
//DDC_MASK_SH_LIST_DCN2(_MASK, 3),
//DDC_MASK_SH_LIST_DCN2(_MASK, 4),
//DDC_MASK_SH_LIST_DCN2(_MASK, 5),
//DDC_MASK_SH_LIST_DCN2(_MASK, 6),
//DDC_MASK_SH_LIST_DCN2_VGA(_MASK)
//};
#include "../generic_regs.h"
/* set field name */
#define SF_GENERIC(reg_name, field_name, post_fix)\
.field_name = 0
static const struct generic_registers generic_regs[] = {
{{ 0 }},
{{ 0 }},
};
static const struct generic_sh_mask generic_shift[] = {
{ 0 },
{ 0 },
};
static const struct generic_sh_mask generic_mask[] = {
{ 0 },
{ 0 },
};
static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
{
struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
generic->regs = &generic_regs[en];
generic->shifts = &generic_shift[en];
generic->masks = &generic_mask[en];
generic->base.regs = &generic_regs[en].gpio;
}
static void define_ddc_registers(
struct hw_gpio_pin *pin,
uint32_t en)
{
struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
switch (pin->id) {
case GPIO_ID_DDC_DATA:
ddc->regs = &ddc_data_regs_dcn[en];
ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
break;
case GPIO_ID_DDC_CLOCK:
ddc->regs = &ddc_clk_regs_dcn[en];
ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
break;
default:
ASSERT_CRITICAL(false);
return;
}
//ddc->shifts = &ddc_shift[en];
//ddc->masks = &ddc_mask[en];
ddc->shifts = NULL;
ddc->masks = NULL;
}
static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
{
struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
hpd->regs = &hpd_regs[en];
hpd->shifts = &hpd_shift;
hpd->masks = &hpd_mask;
hpd->base.regs = &hpd_regs[en].gpio;
}
/* function table */
static const struct hw_factory_funcs funcs = {
.init_ddc_data = dal_hw_ddc_init,
.init_generic = dal_hw_generic_init,
.init_hpd = dal_hw_hpd_init,
.get_ddc_pin = dal_hw_ddc_get_pin,
.get_hpd_pin = dal_hw_hpd_get_pin,
.get_generic_pin = dal_hw_generic_get_pin,
.define_hpd_registers = define_hpd_registers,
.define_ddc_registers = define_ddc_registers,
.define_generic_registers = define_generic_registers
};
/*
* dal_hw_factory_dcn42_init
*
* @brief
* Initialize HW factory function pointers and pin info
*
* @param
* struct hw_factory *factory - [out] struct of function pointers
*/
void dal_hw_factory_dcn42b_init(struct hw_factory *factory)
{
factory->number_of_pins[GPIO_ID_DDC_DATA] = 1; // VGA
factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 1; // VGA
factory->number_of_pins[GPIO_ID_GENERIC] = 4;
factory->number_of_pins[GPIO_ID_HPD] = 3; // only 3 HPD
factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
factory->number_of_pins[GPIO_ID_SYNC] = 0;
factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/
factory->funcs = &funcs;
}

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drivers/gpu/drm/amd/display/dc/gpio/dcn42b/hw_factory_dcn42b.h Normal file
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// SPDX-License-Identifier: MIT
//
// Copyright 2026 Advanced Micro Devices, Inc.
#ifndef __DAL_HW_FACTORY_DCN42B_H__
#define __DAL_HW_FACTORY_DCN42B_H__
/* Initialize HW factory function pointers and pin info */
void dal_hw_factory_dcn42b_init(struct hw_factory *factory);
#endif /* __DAL_HW_FACTORY_DCN42B_H__ */

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drivers/gpu/drm/amd/display/dc/gpio/dcn42b/hw_translate_dcn42b.c Normal file
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// SPDX-License-Identifier: MIT
//
// Copyright 2026 Advanced Micro Devices, Inc.
#include "hw_translate_dcn42b.h"
#include "dm_services.h"
#include "include/gpio_types.h"
#include "../hw_translate.h"
#include "dcn/dcn_4_2_1_offset.h"
#include "dcn/dcn_4_2_1_sh_mask.h"
#include "dpcs/dpcs_4_0_1_offset.h"
#include "dpcs/dpcs_4_0_1_sh_mask.h"
#define DCN_BASE__INST0_SEG2 0x000034C0
#define block HPD
#define reg_num 0
#undef BASE_INNER
#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
#define BASE(seg) BASE_INNER(seg)
#undef REG
#define REG(reg_name) \
BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
#define SF_HPD(reg_name, field_name, post_fix) \
.field_name = reg_name ## __ ## field_name ## post_fix
static bool offset_to_id(
uint32_t offset,
uint32_t mask,
enum gpio_id *id,
uint32_t *en)
{
(void)mask;
switch (offset) {
/* HPD */
case REG(HPD0_DC_HPD_INT_STATUS):
*id = GPIO_ID_HPD;
*en = GPIO_HPD_1;
return true;
case REG(HPD1_DC_HPD_INT_STATUS):
*id = GPIO_ID_HPD;
*en = GPIO_HPD_2;
return true;
case REG(HPD2_DC_HPD_INT_STATUS):
*id = GPIO_ID_HPD;
*en = GPIO_HPD_3;
return true;
/* Not in DNC42B
case REG(HPD3_DC_HPD_INT_STATUS):
*id = GPIO_ID_HPD;
*en = GPIO_HPD_4;
return true;
case REG(HPD4_DC_HPD_INT_STATUS):
*id = GPIO_ID_HPD;
*en = GPIO_HPD_5;
return true;
case REG(DC_GPIO_DDC1_A):
*en = GPIO_DDC_LINE_DDC1;
return true;
case REG(DC_GPIO_DDC2_A):
*en = GPIO_DDC_LINE_DDC2;
return true;
case REG(DC_GPIO_DDC3_A):
*en = GPIO_DDC_LINE_DDC3;
return true;
case REG(DC_GPIO_DDC4_A):
*en = GPIO_DDC_LINE_DDC4;
return true;
case REG(DC_GPIO_DDC5_A):
*en = GPIO_DDC_LINE_DDC5;
return true;
*/
case REG(DC_GPIO_DDCVGA_A):
*en = GPIO_DDC_LINE_DDC_VGA;
return true;
default:
//ASSERT_CRITICAL(false);
return false;
}
}
static bool id_to_offset(
enum gpio_id id,
uint32_t en,
struct gpio_pin_info *info)
{
bool result = true;
switch (id) {
case GPIO_ID_DDC_DATA:
info->mask = DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK;
switch (en) {
/* Not in DCN42B
case GPIO_DDC_LINE_DDC
info->offset = REG(DC_GPIO_DDC1_A);
break;
case GPIO_DDC_LINE_DDC
info->offset = REG(DC_GPIO_DDC2_A);
break;
case GPIO_DDC_LINE_DDC
info->offset = REG(DC_GPIO_DDC3_A);
break;
case GPIO_DDC_LINE_DDC
info->offset = REG(DC_GPIO_DDC4_A);
break;
case GPIO_DDC_LINE_DDC5:
info->offset = REG(DC_GPIO_DDC5_A);
break;
*/
case GPIO_DDC_LINE_DDC_VGA:
info->offset = REG(DC_GPIO_DDCVGA_A);
break;
case GPIO_DDC_LINE_I2C_PAD:
default:
ASSERT_CRITICAL(false);
result = false;
}
break;
case GPIO_ID_DDC_CLOCK:
info->mask = DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK;
switch (en) {
/* Not in DCN42B
case GPIO_DDC_LINE_DDC1:
info->offset = REG(DC_GPIO_DDC1_A);
break;
case GPIO_DDC_LINE_DDC2:
info->offset = REG(DC_GPIO_DDC2_A);
break;
case GPIO_DDC_LINE_DDC3:
info->offset = REG(DC_GPIO_DDC3_A);
break;
case GPIO_DDC_LINE_DDC4:
info->offset = REG(DC_GPIO_DDC4_A);
break;
case GPIO_DDC_LINE_DDC5:
info->offset = REG(DC_GPIO_DDC5_A);
break;
*/
case GPIO_DDC_LINE_DDC_VGA:
info->offset = REG(DC_GPIO_DDCVGA_A);
break;
case GPIO_DDC_LINE_I2C_PAD:
default:
ASSERT_CRITICAL(false);
result = false;
}
break;
case GPIO_ID_SYNC:
case GPIO_ID_VIP_PAD:
default:
ASSERT_CRITICAL(false);
result = false;
}
if (result) {
info->offset_y = info->offset + 2;
info->offset_en = info->offset + 1;
info->offset_mask = info->offset - 1;
info->mask_y = info->mask;
info->mask_en = info->mask;
info->mask_mask = info->mask;
}
return result;
}
/* function table */
static const struct hw_translate_funcs funcs = {
.offset_to_id = offset_to_id,
.id_to_offset = id_to_offset,
};
/*
* dal_hw_translate_dcn42b_init
*
* @brief
* Initialize Hw translate function pointers.
*
* @param
* struct hw_translate *tr - [out] struct of function pointers
*
*/
void dal_hw_translate_dcn42b_init(struct hw_translate *tr)
{
tr->funcs = &funcs;
}

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drivers/gpu/drm/amd/display/dc/gpio/dcn42b/hw_translate_dcn42b.h Normal file
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// SPDX-License-Identifier: MIT
//
// Copyright 2026 Advanced Micro Devices, Inc.
#ifndef __DAL_HW_TRANSLATE_DCN42B_H__
#define __DAL_HW_TRANSLATE_DCN42B_H__
struct hw_translate;
/* Initialize Hw translate function pointers */
void dal_hw_translate_dcn42b_init(struct hw_translate *tr);
#endif /* __DAL_HW_TRANSLATE_DCN42B_H__ */

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drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c Normal file
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/*
* SPDX-License-Identifier: MIT
*
* Copyright 2026 Advanced Micro Devices, Inc.
*/
#include "dm_services.h"
#include "core_types.h"
#include "resource.h"
#include "dce/dce_hwseq.h"
#include "dcn10/dcn10_hwseq.h"
#include "reg_helper.h"
#include "hubp.h"
#include "dchubbub.h"
#include "timing_generator.h"
#include "opp.h"
#include "mpc.h"
#include "dcn42b_hwseq.h"
#define CTX \
hws->ctx
#define REG(reg)\
hws->regs->reg
#define DC_LOGGER \
hws->ctx->logger
#undef FN
#define FN(reg_name, field_name) \
hws->shifts->field_name, hws->masks->field_name
/*
* dcn42b_init_pipes - Initialize pipes for dcn42b
*
* This function is modeled after dcn10_init_pipes but handles the case
* where num_timing_generator != num_pipes (e.g., 3 TGs but 4 pipes).
*
* For dcn42b:
* - num_timing_generator = 3
* - num_pipes (num_dpp) = 4
*
* The key difference is that we iterate over timing generators separately
* from pipes to avoid accessing timing_generators[i] when i >= num_timing_generator.
*/
void dcn42b_init_pipes(struct dc *dc, struct dc_state *context)
{
uint8_t i;
struct dce_hwseq *hws = dc->hwseq;
struct hubbub *hubbub = dc->res_pool->hubbub;
bool can_apply_seamless_boot = false;
bool tg_enabled[MAX_PIPES] = {false};
for (i = 0; i < context->stream_count; i++) {
if (context->streams[i]->apply_seamless_boot_optimization) {
can_apply_seamless_boot = true;
break;
}
}
for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
struct timing_generator *tg = dc->res_pool->timing_generators[i];
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
/* There is assumption that pipe_ctx is not mapping irregularly
* to non-preferred front end. If pipe_ctx->stream is not NULL,
* we will use the pipe, so don't disable
*/
if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
continue;
/* Blank controller using driver code instead of
* command table.
*/
if (tg->funcs->is_tg_enabled(tg)) {
if (hws->funcs.init_blank != NULL) {
hws->funcs.init_blank(dc, tg);
tg->funcs->lock(tg);
} else {
tg->funcs->lock(tg);
tg->funcs->set_blank(tg, true);
hwss_wait_for_blank_complete(tg);
}
}
}
/* Reset det size */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
struct hubp *hubp = dc->res_pool->hubps[i];
/* Do not need to reset for seamless boot */
if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
continue;
if (hubbub && hubp) {
if (hubbub->funcs->program_det_size)
hubbub->funcs->program_det_size(hubbub, hubp->inst, 0);
if (hubbub->funcs->program_det_segments)
hubbub->funcs->program_det_segments(hubbub, hubp->inst, 0);
}
}
/* num_opp will be equal to number of mpcc */
for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
/* Cannot reset the MPC mux if seamless boot */
if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
continue;
dc->res_pool->mpc->funcs->mpc_init_single_inst(
dc->res_pool->mpc, i);
}
/* initialize DWB pointer to MCIF_WB */
for (i = 0; i < dc->res_pool->res_cap->num_dwb; i++)
dc->res_pool->dwbc[i]->mcif = dc->res_pool->mcif_wb[i];
for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
struct timing_generator *tg = dc->res_pool->timing_generators[i];
struct hubp *hubp = dc->res_pool->hubps[i];
struct dpp *dpp = dc->res_pool->dpps[i];
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
/* There is assumption that pipe_ctx is not mapping irregularly
* to non-preferred front end. If pipe_ctx->stream is not NULL,
* we will use the pipe, so don't disable
*/
if (can_apply_seamless_boot &&
pipe_ctx->stream != NULL &&
pipe_ctx->stream_res.tg->funcs->is_tg_enabled(
pipe_ctx->stream_res.tg)) {
// Enable double buffering for OTG_BLANK no matter if
// seamless boot is enabled or not to suppress global sync
// signals when OTG blanked. This is to prevent pipe from
// requesting data while in PSR.
tg->funcs->tg_init(tg);
hubp->power_gated = true;
tg_enabled[i] = true;
continue;
}
/* Disable on the current state so the new one isn't cleared. */
pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
hubp->funcs->hubp_reset(hubp);
dpp->funcs->dpp_reset(dpp);
pipe_ctx->stream_res.tg = tg;
pipe_ctx->pipe_idx = i;
pipe_ctx->plane_res.hubp = hubp;
pipe_ctx->plane_res.dpp = dpp;
pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;
hubp->mpcc_id = dpp->inst;
hubp->opp_id = OPP_ID_INVALID;
hubp->power_gated = false;
dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);
if (tg->funcs->is_tg_enabled(tg))
tg->funcs->unlock(tg);
dc->hwss.disable_plane(dc, context, pipe_ctx);
pipe_ctx->stream_res.tg = NULL;
pipe_ctx->plane_res.hubp = NULL;
if (tg->funcs->is_tg_enabled(tg)) {
if (tg->funcs->init_odm)
tg->funcs->init_odm(tg);
}
tg->funcs->tg_init(tg);
}
/* Clean up MPC tree */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
if (tg_enabled[i]) {
if (dc->res_pool->opps[i]->mpc_tree_params.opp_list) {
if (dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot) {
int bot_id = dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot->mpcc_id;
if ((bot_id < MAX_MPCC) && (bot_id < MAX_PIPES) && (!tg_enabled[bot_id]))
dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
}
}
}
}
/* Power gate DSCs */
if (hws->funcs.dsc_pg_control != NULL) {
uint32_t num_opps = 0;
uint32_t opp_id_src0 = OPP_ID_INVALID;
uint32_t opp_id_src1 = OPP_ID_INVALID;
// Step 1: To find out which OPTC is running & OPTC DSC is ON
// We can't use res_pool->res_cap->num_timing_generator to check
// Because it records display pipes default setting built in driver,
// not display pipes of the current chip.
// Some ASICs would be fused display pipes less than the default setting.
// In dcnxx_resource_construct function, driver would obatin real information.
for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
uint32_t optc_dsc_state = 0;
struct timing_generator *tg = dc->res_pool->timing_generators[i];
if (tg->funcs->is_tg_enabled(tg)) {
if (tg->funcs->get_dsc_status)
tg->funcs->get_dsc_status(tg, &optc_dsc_state);
// Only one OPTC with DSC is ON, so if we got one result, we would exit this block.
// non-zero value is DSC enabled
if (optc_dsc_state != 0) {
tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
break;
}
}
}
// Step 2: To power down DSC but skip DSC of running OPTC
for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
struct dcn_dsc_state s = {0};
dc->res_pool->dscs[i]->funcs->dsc_read_state(dc->res_pool->dscs[i], &s);
if ((s.dsc_opp_source == opp_id_src0 || s.dsc_opp_source == opp_id_src1) &&
s.dsc_clock_en && s.dsc_fw_en)
continue;
hws->funcs.dsc_pg_control(hws, dc->res_pool->dscs[i]->inst, false);
}
}
}

15
drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.h Normal file
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@ -0,0 +1,15 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright 2026 Advanced Micro Devices, Inc.
*/
#ifndef __DC_HWSS_DCN42B_H__
#define __DC_HWSS_DCN42B_H__
#include "dc.h"
#include "hw_sequencer_private.h"
void dcn42b_init_pipes(struct dc *dc, struct dc_state *context);
#endif /* __DC_HWSS_DCN42B_H__ */

20
drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_init.c Normal file
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@ -0,0 +1,20 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright 2026 Advanced Micro Devices, Inc.
*/
#include "dcn20/dcn20_hwseq.h"
#include "dcn42/dcn42_init.h"
#include "dcn42b_hwseq.h"
#include "dcn42b_init.h"
void dcn42b_hw_sequencer_init_functions(struct dc *dc)
{
/* Initialize with dcn42 functions first */
dcn42_hw_sequencer_init_functions(dc);
/* Override only init_pipes with dcn42b version */
dc->hwseq->funcs.init_pipes = dcn42b_init_pipes;
}

14
drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_init.h Normal file
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/*
* SPDX-License-Identifier: MIT
*
* Copyright 2026 Advanced Micro Devices, Inc.
*/
#ifndef __DC_DCN42B_INIT_H__
#define __DC_DCN42B_INIT_H__
struct dc;
void dcn42b_hw_sequencer_init_functions(struct dc *dc);
#endif /* __DC_DCN42B_INIT_H__ */

2404
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c Normal file
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File diff suppressed because it is too large Load Diff

672
drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.h Normal file
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// SPDX-License-Identifier: MIT
//
// Copyright 2026 Advanced Micro Devices, Inc.
#ifndef _DCN42B_RESOURCE_H_
#define _DCN42B_RESOURCE_H_
#include "core_types.h"
#define TO_DCN42B_RES_POOL(pool) \
container_of(pool, struct dcn42b_resource_pool, base)
/* DPP */
#define DPP_REG_LIST_DCN42B_COMMON_RI(id) \
SRI_ARR(CM_DEALPHA, CM, id), SRI_ARR(CM_MEM_PWR_STATUS, CM, id), \
SRI_ARR(CM_BIAS_CR_R, CM, id), SRI_ARR(CM_BIAS_Y_G_CB_B, CM, id), \
SRI_ARR(PRE_DEGAM, CNVC_CFG, id), SRI_ARR(CM_GAMCOR_CONTROL, CM, id), \
SRI_ARR(CM_GAMCOR_LUT_CONTROL, CM, id), \
SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \
SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \
SRI_ARR(CM_GAMCOR_LUT_DATA, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_B, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_G, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_R, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_REGION_0_1, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_REGION_32_33, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_OFFSET_B, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_OFFSET_G, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_OFFSET_R, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id), \
SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_B, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_G, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_R, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_REGION_0_1, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_REGION_32_33, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_OFFSET_B, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_OFFSET_G, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_OFFSET_R, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id), \
SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id), \
SRI_ARR(CM_HIST_CNTL, CM, id), \
SRI_ARR(CM_HIST_LOCK, CM, id), \
SRI_ARR(CM_HIST_INDEX, CM, id), \
SRI_ARR(CM_HIST_DATA, CM, id), \
SRI_ARR(CM_HIST_STATUS, CM, id), \
SRI_ARR(CM_HIST_SCALE_SRC1, CM, id), \
SRI_ARR(CM_HIST_COEFA_SRC2, CM, id), \
SRI_ARR(CM_HIST_COEFB_SRC2, CM, id), \
SRI_ARR(CM_HIST_COEFC_SRC2, CM, id), \
SRI_ARR(CM_HIST_SCALE_SRC3, CM, id), \
SRI_ARR(CM_HIST_BIAS_SRC1, CM, id), \
SRI_ARR(CM_HIST_BIAS_SRC2, CM, id), \
SRI_ARR(CM_HIST_BIAS_SRC3, CM, id), \
SRI_ARR(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
SRI_ARR(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
SRI_ARR(OTG_H_BLANK, DSCL, id), SRI_ARR(OTG_V_BLANK, DSCL, id), \
SRI_ARR(SCL_MODE, DSCL, id), SRI_ARR(LB_DATA_FORMAT, DSCL, id), \
SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id), \
SRI_ARR(SCL_TAP_CONTROL, DSCL, id), \
SRI_ARR(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
SRI_ARR(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
SRI_ARR(DSCL_2TAP_CONTROL, DSCL, id), SRI_ARR(MPC_SIZE, DSCL, id), \
SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \
SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \
SRI_ARR(SCL_HORZ_FILTER_INIT, DSCL, id), \
SRI_ARR(SCL_HORZ_FILTER_INIT_C, DSCL, id), \
SRI_ARR(SCL_VERT_FILTER_INIT, DSCL, id), \
SRI_ARR(SCL_VERT_FILTER_INIT_C, DSCL, id), \
SRI_ARR(RECOUT_START, DSCL, id), SRI_ARR(RECOUT_SIZE, DSCL, id), \
SRI_ARR(PRE_DEALPHA, CNVC_CFG, id), SRI_ARR(PRE_REALPHA, CNVC_CFG, id), \
SRI_ARR(PRE_CSC_MODE, CNVC_CFG, id), \
SRI_ARR(PRE_CSC_C11_C12, CNVC_CFG, id), \
SRI_ARR(PRE_CSC_C33_C34, CNVC_CFG, id), \
SRI_ARR(PRE_CSC_B_C11_C12, CNVC_CFG, id), \
SRI_ARR(PRE_CSC_B_C33_C34, CNVC_CFG, id), \
SRI_ARR(CM_POST_CSC_CONTROL, CM, id), \
SRI_ARR(CM_POST_CSC_C11_C12, CM, id), \
SRI_ARR(CM_POST_CSC_C33_C34, CM, id), \
SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id), \
SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id), \
SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id), \
SRI_ARR(CM_TEST_DEBUG_INDEX, CM, id), \
SRI_ARR(CM_TEST_DEBUG_DATA, CM, id), \
SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id), \
SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
SRI_ARR(CURSOR0_CONTROL, CM_CUR, id), \
SRI_ARR(CURSOR0_COLOR0, CM_CUR, id), \
SRI_ARR(CURSOR0_COLOR1, CM_CUR, id), \
SRI_ARR(CURSOR0_FP_SCALE_BIAS_G_Y, CM_CUR, id), \
SRI_ARR(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CM_CUR, id), \
SRI_ARR(CUR0_MATRIX_MODE, CM_CUR, id), \
SRI_ARR(CUR0_MATRIX_C11_C12_A, CM_CUR, id), \
SRI_ARR(CUR0_MATRIX_C13_C14_A, CM_CUR, id), \
SRI_ARR(CUR0_MATRIX_C21_C22_A, CM_CUR, id), \
SRI_ARR(CUR0_MATRIX_C23_C24_A, CM_CUR, id), \
SRI_ARR(CUR0_MATRIX_C31_C32_A, CM_CUR, id), \
SRI_ARR(CUR0_MATRIX_C33_C34_A, CM_CUR, id), \
SRI_ARR(CUR0_MATRIX_C11_C12_B, CM_CUR, id), \
SRI_ARR(CUR0_MATRIX_C13_C14_B, CM_CUR, id), \
SRI_ARR(CUR0_MATRIX_C21_C22_B, CM_CUR, id), \
SRI_ARR(CUR0_MATRIX_C23_C24_B, CM_CUR, id), \
SRI_ARR(CUR0_MATRIX_C31_C32_B, CM_CUR, id), \
SRI_ARR(CUR0_MATRIX_C33_C34_B, CM_CUR, id), \
SRI_ARR(DPP_CONTROL, DPP_TOP, id), SRI_ARR(CM_HDR_MULT_COEF, CM, id), \
SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \
SRI_ARR(ALPHA_2BIT_LUT01, CNVC_CFG, id), \
SRI_ARR(ALPHA_2BIT_LUT23, CNVC_CFG, id), \
SRI_ARR(FCNV_FP_BIAS_R, CNVC_CFG, id), \
SRI_ARR(FCNV_FP_BIAS_G, CNVC_CFG, id), \
SRI_ARR(FCNV_FP_BIAS_B, CNVC_CFG, id), \
SRI_ARR(FCNV_FP_SCALE_R, CNVC_CFG, id), \
SRI_ARR(FCNV_FP_SCALE_G, CNVC_CFG, id), \
SRI_ARR(FCNV_FP_SCALE_B, CNVC_CFG, id), \
SRI_ARR(COLOR_KEYER_CONTROL, CNVC_CFG, id), \
SRI_ARR(COLOR_KEYER_ALPHA, CNVC_CFG, id), \
SRI_ARR(COLOR_KEYER_RED, CNVC_CFG, id), \
SRI_ARR(COLOR_KEYER_GREEN, CNVC_CFG, id), \
SRI_ARR(COLOR_KEYER_BLUE, CNVC_CFG, id), \
SRI_ARR(OBUF_MEM_PWR_CTRL, DSCL, id), \
SRI_ARR(DSCL_MEM_PWR_STATUS, DSCL, id), \
SRI_ARR(DSCL_MEM_PWR_CTRL, DSCL, id), \
SRI_ARR(DSCL_CONTROL, DSCL, id), \
SRI_ARR(DSCL_SC_MODE, DSCL, id), \
SRI_ARR(DSCL_EASF_H_MODE, DSCL, id), \
SRI_ARR(DSCL_EASF_H_BF_CNTL, DSCL, id), \
SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, DSCL, id), \
SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_GAIN, DSCL, id), \
SRI_ARR(DSCL_EASF_H_BF_FINAL_MAX_MIN, DSCL, id), \
SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG0, DSCL, id), \
SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG1, DSCL, id), \
SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG2, DSCL, id), \
SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG3, DSCL, id), \
SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG4, DSCL, id), \
SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG5, DSCL, id), \
SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG6, DSCL, id), \
SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG7, DSCL, id), \
SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG0, DSCL, id), \
SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG1, DSCL, id), \
SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG2, DSCL, id), \
SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG3, DSCL, id), \
SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG4, DSCL, id), \
SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG5, DSCL, id), \
SRI_ARR(DSCL_EASF_V_MODE, DSCL, id), \
SRI_ARR(DSCL_EASF_V_BF_CNTL, DSCL, id), \
SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL1, DSCL, id), \
SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL2, DSCL, id), \
SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL3, DSCL, id), \
SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, DSCL, id), \
SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_GAIN, DSCL, id), \
SRI_ARR(DSCL_EASF_V_BF_FINAL_MAX_MIN, DSCL, id), \
SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG0, DSCL, id), \
SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG1, DSCL, id), \
SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG2, DSCL, id), \
SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG3, DSCL, id), \
SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG4, DSCL, id), \
SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG5, DSCL, id), \
SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG6, DSCL, id), \
SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG7, DSCL, id), \
SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG0, DSCL, id), \
SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG1, DSCL, id), \
SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG2, DSCL, id), \
SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG3, DSCL, id), \
SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG4, DSCL, id), \
SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG5, DSCL, id), \
SRI_ARR(DSCL_SC_MATRIX_C0C1, DSCL, id), \
SRI_ARR(DSCL_SC_MATRIX_C2C3, DSCL, id), \
SRI_ARR(ISHARP_MODE, DSCL, id), \
SRI_ARR(ISHARP_DELTA_LUT_MEM_PWR_CTRL, DSCL, id), \
SRI_ARR(ISHARP_NOISEDET_THRESHOLD, DSCL, id), \
SRI_ARR(ISHARP_NOISE_GAIN_PWL, DSCL, id), \
SRI_ARR(ISHARP_LBA_PWL_SEG0, DSCL, id), \
SRI_ARR(ISHARP_LBA_PWL_SEG1, DSCL, id), \
SRI_ARR(ISHARP_LBA_PWL_SEG2, DSCL, id), \
SRI_ARR(ISHARP_LBA_PWL_SEG3, DSCL, id), \
SRI_ARR(ISHARP_LBA_PWL_SEG4, DSCL, id), \
SRI_ARR(ISHARP_LBA_PWL_SEG5, DSCL, id), \
SRI_ARR(ISHARP_DELTA_CTRL, DSCL, id), \
SRI_ARR(ISHARP_DELTA_DATA, DSCL, id), \
SRI_ARR(ISHARP_DELTA_INDEX, DSCL, id), \
SRI_ARR(ISHARP_NLDELTA_SOFT_CLIP, DSCL, id), \
SRI_ARR(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \
SRI_ARR(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id)
/* Stream encoder */
#define SE_DCN42B_REG_LIST_RI(id) \
SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id), \
SRI_ARR(HDMI_GC, DIG, id), \
SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \
SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \
SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \
SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \
SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \
SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \
SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \
SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id), \
SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \
SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id), \
SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id), \
SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \
SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \
SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id), \
SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id), \
SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \
SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \
SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \
SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \
SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \
SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \
SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \
SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \
SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \
SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id), \
SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \
SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id), \
SRI_ARR(DP_SEC_TIMESTAMP, DP, id), \
SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \
SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
SRI_ARR(DP_SEC_FRAMING4, DP, id), SRI_ARR(DP_GSP11_CNTL, DP, id), \
SRI_ARR(DME_CONTROL, DME, id), \
SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \
SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
SRI_ARR(DIG_FE_CNTL, DIG, id), \
SRI_ARR(DIG_FE_EN_CNTL, DIG, id), \
SRI_ARR(DIG_FE_CLK_CNTL, DIG, id), \
SRI_ARR(DIG_CLOCK_PATTERN, DIG, id), \
SRI_ARR(DIG_FIFO_CTRL0, DIG, id), \
SRI_ARR(STREAM_MAPPER_CONTROL, DIG, id),\
SRI_ARR(DIG_FE_AUDIO_CNTL, DIG, id)
/* HPO DP stream encoder */
/* Not in DCN42B:
* SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id),
* SRI_ARR(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id),
*/
#define DCN42B_HPO_DP_STREAM_ENC_REG_LIST_RI(id) \
SR_ARR(DP_STREAM_MAPPER_CONTROL0, id), \
SR_ARR(DP_STREAM_MAPPER_CONTROL1, id), \
SR_ARR(DP_STREAM_MAPPER_CONTROL2, id), \
SR_ARR(DP_STREAM_MAPPER_CONTROL3, id), \
SRI_ARR(DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC, id), \
SRI_ARR(DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC, id), \
SRI_ARR(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC, id), \
SRI_ARR(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, DP_STREAM_ENC, id), \
SRI_ARR(DP_SYM32_ENC_CONTROL, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA0, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA1, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA2, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA3, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA4, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA5, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA6, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA7, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA8, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA_CONTROL, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_FIFO_CONTROL, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_STREAM_CONTROL, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_VID_VBID_CONTROL, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_SDP_CONTROL, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL0, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL2, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL3, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL5, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL11, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, DP_SYM32_ENC, id), \
SRI_ARR(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, DP_SYM32_ENC, id)
/*HPO DP link encoder regs */
#define DCN42B_HPO_DP_LINK_ENC_REG_LIST_RI(id) \
SRI_ARR(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC, id), \
SRI_ARR(DP_DPHY_SYM32_CONTROL, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_STATUS, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_TP_CONFIG, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED0, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED1, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED2, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED3, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_TP_SQ_PULSE, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM0, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM1, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM2, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM3, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM4, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM5, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM6, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM7, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM8, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM9, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM10, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_SAT_VC0, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_SAT_VC1, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_SAT_VC2, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_SAT_VC3, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL0, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL1, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL2, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL3, DP_DPHY_SYM32, id), \
SRI_ARR(DP_DPHY_SYM32_SAT_UPDATE, DP_DPHY_SYM32, id)
#define VPG_DCN42B_REG_LIST_RI(id) \
SRI(VPG_GENERIC_STATUS, VPG, id), \
SRI(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \
SRI(VPG_GENERIC_PACKET_DATA, VPG, id), \
SRI(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \
SRI(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id), \
SRI(VPG_MEM_PWR, VPG, id)
/* DCCG */
/*
* Following registers are not used in DCN42B.
*
* DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),
* SR(PHYDSYMCLK_CLOCK_CNTL),
* DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),
* DCCG_SRII(PHASE, DP_DTO, 3),
* DCCG_SRII(MODULO, DP_DTO, 3),
* SR(DSCCLK3_DTO_PARAM),
* SR(HDMISTREAMCLK_CNTL),
* SR(SYMCLKD_CLOCK_ENABLE),
* SR(SYMCLKE_CLOCK_ENABLE)
*/
#define DCCG_REG_LIST_DCN42B_RI() \
SR(DPPCLK_DTO_CTRL), \
DCCG_SRII(DTO_PARAM, DPPCLK, 0), \
DCCG_SRII(DTO_PARAM, DPPCLK, 1), \
DCCG_SRII(DTO_PARAM, DPPCLK, 2), \
DCCG_SRII(DTO_PARAM, DPPCLK, 3), \
SR(DCCG_GLOBAL_FGCG_REP_CNTL),\
SR(DISPCLK_FREQ_CHANGE_CNTL), \
SR(PHYASYMCLK_CLOCK_CNTL), \
SR(PHYBSYMCLK_CLOCK_CNTL), \
SR(PHYCSYMCLK_CLOCK_CNTL), \
SR(DPSTREAMCLK_CNTL), \
SR(SYMCLK32_SE_CNTL), \
SR(SYMCLK32_LE_CNTL), \
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), \
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1), \
DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2), \
SR(OTG_PIXEL_RATE_DIV), \
SR(DTBCLK_P_CNTL), \
SR(DCCG_AUDIO_DTO_SOURCE), \
SR(DENTIST_DISPCLK_CNTL), \
SR(DPPCLK_CTRL), \
DCCG_SRII(MODULO, DP_DTO, 0), \
DCCG_SRII(MODULO, DP_DTO, 1), \
DCCG_SRII(MODULO, DP_DTO, 2), \
DCCG_SRII(PHASE, DP_DTO, 0), \
DCCG_SRII(PHASE, DP_DTO, 1), \
DCCG_SRII(PHASE, DP_DTO, 2), \
SR(OTG_ADD_DROP_PIXEL_CNTL), \
SR(DSCCLK0_DTO_PARAM), \
SR(DSCCLK1_DTO_PARAM), \
SR(DSCCLK2_DTO_PARAM), \
SR(DSCCLK_DTO_CTRL), \
SR(DCCG_GATE_DISABLE_CNTL), \
SR(DCCG_GATE_DISABLE_CNTL2), \
SR(DCCG_GATE_DISABLE_CNTL3), \
SR(DCCG_GATE_DISABLE_CNTL4), \
SR(DCCG_GATE_DISABLE_CNTL5), \
SR(DCCG_GATE_DISABLE_CNTL6), \
SR(SYMCLKA_CLOCK_ENABLE), \
SR(SYMCLKB_CLOCK_ENABLE), \
SR(SYMCLKC_CLOCK_ENABLE)
/* OPTC */
#define OPTC_COMMON_REG_LIST_DCN42B_RI(inst) \
SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \
SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \
SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \
SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \
SRI_ARR(OTG_MASTER_UPDATE_MODE, OTG, inst), \
SRI_ARR(OTG_V_COUNT_STOP_CONTROL, OTG, inst), \
SRI_ARR(OTG_V_COUNT_STOP_CONTROL2, OTG, inst), \
SRI_ARR(OTG_GSL_CONTROL, OTG, inst), \
SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst),\
SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \
SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \
SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \
SRI_ARR(OTG_H_TOTAL, OTG, inst), \
SRI_ARR(OTG_H_BLANK_START_END, OTG, inst), \
SRI_ARR(OTG_H_SYNC_A, OTG, inst),\
SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \
SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), \
SRI_ARR(OTG_V_TOTAL, OTG, inst), \
SRI_ARR(OTG_V_BLANK_START_END, OTG, inst), \
SRI_ARR(OTG_V_SYNC_A, OTG, inst), \
SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \
SRI_ARR(OTG_CONTROL, OTG, inst), \
SRI_ARR(OTG_MASTER_EN, OTG, inst), \
SRI_ARR(OTG_LONG_VBLANK_STATUS, OTG, inst), \
SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \
SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \
SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \
SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst), \
SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst), \
SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst), \
SRI_ARR(OTG_TRIGA_CNTL, OTG, inst), \
SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst), \
SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst), \
SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst), \
SRI_ARR(OTG_STATUS, OTG, inst), \
SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \
SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst), \
SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \
SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \
SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \
SRI_ARR(OTG_COUNT_CONTROL, OTG, inst), \
SRI_ARR(OTG_COUNT_RESET, OTG, inst), \
SRI_ARR(OTG_CRC_SIG_BLUE_CONTROL_MASK, OTG, inst), \
SRI_ARR(OTG_CRC_SIG_RED_GREEN_MASK, OTG, inst), \
SRI_ARR(OTG_DRR_TIMING_INT_STATUS, OTG, inst), \
SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \
SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \
SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \
SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst), \
SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst), \
SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst), \
SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst), \
SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst), \
SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst), \
SRI_ARR(OPTC_RSMU_UNDERFLOW, ODM, inst), \
SRI_ARR(OPTC_UNDERFLOW_THRESHOLD, ODM, inst), \
SRI_ARR(CONTROL, VTG, inst), \
SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \
SRI_ARR(OTG_GSL_CONTROL, OTG, inst), \
SRI_ARR(OTG_CRC_CNTL, OTG, inst), \
SRI_ARR(OTG_CRC0_DATA_R, OTG, inst), \
SRI_ARR(OTG_CRC0_DATA_G, OTG, inst), \
SRI_ARR(OTG_CRC0_DATA_B, OTG, inst), \
SRI_ARR(OTG_CRC1_DATA_R, OTG, inst), \
SRI_ARR(OTG_CRC1_DATA_G, OTG, inst), \
SRI_ARR(OTG_CRC1_DATA_B, OTG, inst), \
SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst), \
SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \
SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \
SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \
SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst), \
SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst), \
SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst), \
SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst), \
SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG, inst),\
SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\
SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG, inst),\
SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\
SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG, inst),\
SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\
SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG, inst),\
SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\
SR_ARR(GSL_SOURCE_SELECT, inst), \
SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \
SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \
SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \
SRI_ARR(OTG_GLOBAL_CONTROL3, OTG, inst), \
SRI_ARR(OTG_GLOBAL_SYNC_STATUS, OTG, inst), \
SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst), \
SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst), \
SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst), \
SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst), \
SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst), \
SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst), \
SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \
SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \
SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst), \
SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \
SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \
SRI_ARR(OTG_DRR_CONTOL2, OTG, inst), \
SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst), \
SRI_ARR(OTG_PWA_FRAME_SYNC_CONTROL, OTG, inst),\
SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst),\
SRI_ARR(INTERRUPT_DEST, OTG, inst)
/* CLK SRC */
/**
* Not used in DCN42B:
* SRII_ARR_2(PHASE, DP_DTO, 3, index), \
* SRII_ARR_2(MODULO, DP_DTO, 3, index), \
* SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 3, index)
*/
#define CS_COMMON_REG_LIST_DCN42B_RI(index, pllid) \
SRI_ARR_ALPHABET(PIXCLK_RESYNC_CNTL, PHYPLL, index, pllid), \
SRII_ARR_2(PHASE, DP_DTO, 0, index), \
SRII_ARR_2(PHASE, DP_DTO, 1, index), \
SRII_ARR_2(PHASE, DP_DTO, 2, index), \
SRII_ARR_2(MODULO, DP_DTO, 0, index), \
SRII_ARR_2(MODULO, DP_DTO, 1, index), \
SRII_ARR_2(MODULO, DP_DTO, 2, index), \
SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 0, index), \
SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 1, index), \
SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 2, index)
/* ABM */
#define ABM_DCN42B_REG_LIST_RI(id) \
SRI_ARR(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
SRI_ARR(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
SRI_ARR(DC_ABM1_HG_MISC_CTRL, ABM, id), \
SRI_ARR(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
SRI_ARR(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
SRI_ARR(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
SRI_ARR(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
SRI_ARR(BL1_PWM_USER_LEVEL, ABM, id), \
SRI_ARR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
SRI_ARR(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
SRI_ARR(DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, ABM, id), \
SRI_ARR(DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, ABM, id), \
SRI_ARR(DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, ABM, id), \
SRI_ARR(DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, ABM, id), \
SRI_ARR(DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, ABM, id), \
SRI_ARR(DC_ABM1_HG_RESULT_DATA, ABM, id), \
SRI_ARR(DC_ABM1_HG_RESULT_INDEX, ABM, id), \
SRI_ARR(DC_ABM1_ACE_OFFSET_SLOPE_DATA, ABM, id), \
SRI_ARR(DC_ABM1_ACE_PWL_CNTL, ABM, id)
/* HUBP */
/* Not in DCN42B: HUBPREQ_DEBUG_DB and HUBPREQ_DEBUG */
#define HUBP_REG_LIST_DCN42B_RI(id) \
SRI_ARR(DCN_DMDATA_VM_CNTL, HUBPREQ, id), \
SRI_ARR(FLIP_PARAMETERS_3, HUBPREQ, id), \
SRI_ARR(FLIP_PARAMETERS_4, HUBPREQ, id), \
SRI_ARR(FLIP_PARAMETERS_5, HUBPREQ, id), \
SRI_ARR(FLIP_PARAMETERS_6, HUBPREQ, id), \
SRI_ARR(VBLANK_PARAMETERS_5, HUBPREQ, id), \
SRI_ARR(VBLANK_PARAMETERS_6, HUBPREQ, id), \
HUBP_REG_LIST_DCN_VM_RI(id), \
SRI_ARR(PREFETCH_SETTINGS, HUBPREQ, id), \
SRI_ARR(PREFETCH_SETTINGS_C, HUBPREQ, id), \
SRI_ARR(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id), \
SRI_ARR(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id), \
SRI_ARR(CURSOR_SETTINGS, HUBPREQ, id), \
SRI_ARR(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \
SRI_ARR(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \
SRI_ARR(CURSOR_SIZE, CURSOR0_, id), \
SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \
SRI_ARR(CURSOR_POSITION, CURSOR0_, id), \
SRI_ARR(CURSOR_HOT_SPOT, CURSOR0_, id), \
SRI_ARR(CURSOR_DST_OFFSET, CURSOR0_, id), \
SRI_ARR(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \
SRI_ARR(DMDATA_ADDRESS_LOW, CURSOR0_, id), \
SRI_ARR(DMDATA_CNTL, CURSOR0_, id), \
SRI_ARR(DMDATA_SW_CNTL, CURSOR0_, id), \
SRI_ARR(DMDATA_QOS_CNTL, CURSOR0_, id), \
SRI_ARR(DMDATA_SW_DATA, CURSOR0_, id), \
SRI_ARR(DMDATA_STATUS, CURSOR0_, id), \
SRI_ARR(FLIP_PARAMETERS_0, HUBPREQ, id), \
SRI_ARR(FLIP_PARAMETERS_1, HUBPREQ, id), \
SRI_ARR(FLIP_PARAMETERS_2, HUBPREQ, id), \
SRI_ARR(DCN_CUR1_TTU_CNTL0, HUBPREQ, id), \
SRI_ARR(DCN_CUR1_TTU_CNTL1, HUBPREQ, id), \
SRI_ARR(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \
SRI_ARR(VMID_SETTINGS_0, HUBPREQ, id), \
SRI_ARR(DCHUBP_CNTL, HUBP, id), \
SRI_ARR(DCSURF_ADDR_CONFIG, HUBP, id), \
SRI_ARR(DCSURF_TILING_CONFIG, HUBP, id), \
SRI_ARR(DCSURF_SURFACE_PITCH, HUBPREQ, id), \
SRI_ARR(DCSURF_SURFACE_PITCH_C, HUBPREQ, id), \
SRI_ARR(DCSURF_SURFACE_CONFIG, HUBP, id), \
SRI_ARR(DCSURF_FLIP_CONTROL, HUBPREQ, id), \
SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \
SRI_ARR(DCSURF_PRI_VIEWPORT_START, HUBP, id), \
SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \
SRI_ARR(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
SRI_ARR(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id), \
SRI_ARR(DCSURF_SEC_VIEWPORT_START_C, HUBP, id), \
SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \
SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id), \
SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \
SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id), \
SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \
SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id), \
SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id), \
SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id), \
SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \
SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id), \
SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \
SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id), \
SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \
SRI_ARR(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id), \
SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id), \
SRI_ARR(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, HUBPREQ, id), \
SRI_ARR(DCSURF_SURFACE_INUSE, HUBPREQ, id), \
SRI_ARR(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id), \
SRI_ARR(DCSURF_SURFACE_INUSE_C, HUBPREQ, id), \
SRI_ARR(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id), \
SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id), \
SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id), \
SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id), \
SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id), \
SRI_ARR(DCSURF_SURFACE_CONTROL, HUBPREQ, id), \
SRI_ARR(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id), \
SRI_ARR(HUBPRET_CONTROL, HUBPRET, id), \
SRI_ARR(HUBPRET_READ_LINE_STATUS, HUBPRET, id), \
SRI_ARR(DCN_EXPANSION_MODE, HUBPREQ, id), \
SRI_ARR(DCHUBP_REQ_SIZE_CONFIG, HUBP, id), \
SRI_ARR(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id), \
SRI_ARR(BLANK_OFFSET_0, HUBPREQ, id), \
SRI_ARR(BLANK_OFFSET_1, HUBPREQ, id), \
SRI_ARR(DST_DIMENSIONS, HUBPREQ, id), \
SRI_ARR(DST_AFTER_SCALER, HUBPREQ, id), \
SRI_ARR(VBLANK_PARAMETERS_0, HUBPREQ, id), \
SRI_ARR(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id), \
SRI_ARR(VBLANK_PARAMETERS_1, HUBPREQ, id), \
SRI_ARR(VBLANK_PARAMETERS_3, HUBPREQ, id), \
SRI_ARR(NOM_PARAMETERS_4, HUBPREQ, id), \
SRI_ARR(NOM_PARAMETERS_5, HUBPREQ, id), \
SRI_ARR(PER_LINE_DELIVERY_PRE, HUBPREQ, id), \
SRI_ARR(PER_LINE_DELIVERY, HUBPREQ, id), \
SRI_ARR(VBLANK_PARAMETERS_2, HUBPREQ, id), \
SRI_ARR(VBLANK_PARAMETERS_4, HUBPREQ, id), \
SRI_ARR(NOM_PARAMETERS_6, HUBPREQ, id), \
SRI_ARR(NOM_PARAMETERS_7, HUBPREQ, id), \
SRI_ARR(DCN_TTU_QOS_WM, HUBPREQ, id), \
SRI_ARR(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id), \
SRI_ARR(DCN_SURF0_TTU_CNTL0, HUBPREQ, id), \
SRI_ARR(DCN_SURF0_TTU_CNTL1, HUBPREQ, id), \
SRI_ARR(DCN_SURF1_TTU_CNTL0, HUBPREQ, id), \
SRI_ARR(DCN_SURF1_TTU_CNTL1, HUBPREQ, id), \
SRI_ARR(DCN_CUR0_TTU_CNTL0, HUBPREQ, id), \
SRI_ARR(DCN_CUR0_TTU_CNTL1, HUBPREQ, id), \
SRI_ARR(HUBP_CLK_CNTL, HUBP, id), \
SRI_ARR(HUBPRET_READ_LINE_VALUE, HUBPRET, id), \
SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id), \
SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id), \
SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id), \
SRI_ARR(HUBP_3DLUT_DLG_PARAM, CURSOR0_, id), \
HUBP_3DLUT_FL_REG_LIST_DCN401(id)
struct dcn42b_resource_pool {
struct resource_pool base;
};
struct resource_pool *dcn42b_create_resource_pool(
const struct dc_init_data *init_data,
struct dc *dc);
enum dc_status dcn42b_validate_bandwidth(struct dc *dc,
struct dc_state *context,
enum dc_validate_mode validate_mode);
void dcn42b_prepare_mcache_programming(struct dc *dc, struct dc_state *context);
#endif /* _DCN42B_RESOURCE_H_ */