Dyllan Kobal db9c882f83 drm/amd/display: fix wrong register field in dccg35_set_hdmistreamclk_src_new ... dccg35_set_hdmistreamclk_src_new() updates HDMISTREAMCLK_CNTL but passes DPSTREAMCLK0_SRC_SEL as the field identifier in the second REG_UPDATE_2 slot. The current behavior is harmless on DCN3.5 because both fields share the same bit layout, but it is still incorrect and could break on future hardware revisions. Fixes: d36771a034 ("drm/amd/display: Add DCCG DIO, HPO, OPP, and OPTC support for FRL") Signed-off-by: Dyllan Kobal <dyllan.kobal@zetier.com> Reviewed-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2026-07-15 09:15:43 -04:00
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dcn35_dccg.c	drm/amd/display: fix wrong register field in dccg35_set_hdmistreamclk_src_new	2026-07-15 09:15:43 -04:00
dcn35_dccg.h	drm/amd/display: ensure dtbclk clk_src selected before hdmistream_clk_en	2026-07-14 19:12:35 -04:00