Stephen Boyd dd8eb789f1 Merge branches 'clk-pile' and 'clk-microchip' into clk-next ... * clk-pile: (111 commits) clk: microchip: mpfs: fix regmap_update_bits() mask/val order clk: visconti: Make sure clk_init_data is fully initialized clk: ti: Make sure clk_init_data is fully initialized MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem Drop Michael Turquette's clk maintainer entry clk: ti: composite: resolve parent clocks by DT index, not by name clk: ti: mux: resolve parent clocks by DT index, not by name clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate() dt-bindings: clock: ti,keystone-gate: Convert to DT schema dt-bindings: clock: ti: Convert APLL clock to DT schema clk: zynq: pll: Fix kernel-doc after determine_rate() conversion dt-bindings: clock: ti,clockdomain: Convert to DT schema dt-bindings: clock: Correct white-space style clk: tegra: set up proper EMC clock implementation for Tegra114 clk: clocking-wizard: remove 20kHz restriction clk: clocking-wizard: optimize clock search clk: clocking-wizard: fix clock difference detection clk: mediatek: mt8135: Fix inverted gate control for devapc_ck clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig clk: tegra: support 48MHz clock for pll_p_out1 ... * clk-microchip: clk: at91: Read "reg" with helper		2026-08-20 16:51:47 -07:00
..
clk-div6.c	Convert 'alloc_flex' family to use the new default GFP_KERNEL argument	2026-02-21 17:09:51 -08:00
clk-div6.h	We have two changes to the core framework this time around. The first being a	2017-11-17 20:04:24 -08:00
clk-emev2.c	clk: renesas: emev2: Remove obsolete clkdev registration	2023-07-27 14:32:41 +02:00
clk-mstp.c	Convert 'alloc_flex' family to use the new default GFP_KERNEL argument	2026-02-21 17:09:51 -08:00
clk-r8a73a4.c	clk: renesas: r8a73a4: Add ZT/ZTR trace clocks	2026-05-15 11:30:51 +02:00
clk-r8a7740.c	clk: renesas: r8a7740: Add ZT/ZTR trace clocks	2026-04-27 11:52:42 +02:00
clk-r8a7778.c	Convert 'alloc_obj' family to use the new default GFP_KERNEL argument	2026-02-21 17:09:51 -08:00
clk-r8a7779.c	Convert 'alloc_obj' family to use the new default GFP_KERNEL argument	2026-02-21 17:09:51 -08:00
clk-rz.c	Convert 'alloc_obj' family to use the new default GFP_KERNEL argument	2026-02-21 17:09:51 -08:00
clk-sh73a0.c	Convert 'alloc_obj' family to use the new default GFP_KERNEL argument	2026-02-21 17:09:51 -08:00
clk-vbattb.c	Replace <linux/mod_devicetable.h> by more specific <linux/device-id/*.h> (c files)	2026-07-03 07:38:17 +02:00
Kconfig	clk: renesas: Add R-Car X5H CPG driver	2026-08-06 10:00:14 +02:00
Makefile	clk: renesas: Add R-Car X5H CPG driver	2026-08-06 10:00:14 +02:00
r7s9210-cpg-mssr.c	clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register	2025-06-10 10:20:45 +02:00
r8a774a1-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a774b1-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a774c0-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a774e1-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a779a0-cpg-mssr.c	clk: renesas: r8a779a0: Add 3DGE module clock	2025-11-12 11:09:02 +01:00
r8a779f0-cpg-mssr.c	clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs	2024-07-30 10:44:19 +02:00
r8a779g0-cpg-mssr.c	clk: renesas: r8a779g0: Add DSC clock	2026-05-28 15:09:54 +02:00
r8a779h0-cpg-mssr.c	clk: renesas: r8a779h0: Add VSPX clock	2025-02-03 11:07:06 +01:00
r8a7742-cpg-mssr.c	clk: renesas: r8a7742: Add clk entry for VSPR	2020-09-04 09:42:01 +02:00
r8a7743-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7745-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7790-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7791-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7792-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7794-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7795-cpg-mssr.c	clk: renesas: r8a7795: Constify r8a7795_*_clks	2023-09-26 09:38:00 +02:00
r8a7796-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a77470-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a77965-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a77970-cpg-mssr.c	clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register	2025-06-10 10:20:45 +02:00
r8a77980-cpg-mssr.c	clk: renesas: r8a77980: Add I2C5 clock	2023-03-30 16:44:04 +02:00
r8a77990-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a77995-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a78000-cpg.c	clk: renesas: Add R-Car X5H CPG driver	2026-08-06 10:00:14 +02:00
r9a06g032-clocks.c	clk: renesas: r9a06g032: Enable watchdog reset sources	2026-03-25 18:29:00 +01:00
r9a07g043-cpg.c	clk: renesas: rzg2l: Simplify SAM PLL configuration macro	2026-05-22 10:24:32 +02:00
r9a07g044-cpg.c	clk: renesas: rzg2l: Simplify SAM PLL configuration macro	2026-05-22 10:24:32 +02:00
r9a08g045-cpg.c	clk: r9a08g045: Add clocks and resets for CAN-FD	2026-07-13 13:58:01 +02:00
r9a08g046-cpg.c	clk: renesas: r9a08g046: Add USB2.0 clock and reset entries	2026-06-30 11:55:37 +02:00
r9a09g011-cpg.c	clk: renesas: rzg2l: Simplify SAM PLL configuration macro	2026-05-22 10:24:32 +02:00
r9a09g047-cpg.c	clk: renesas: r9a09g047: Add LVDS clocks and resets	2026-06-30 12:01:00 +02:00
r9a09g056-cpg.c	clk: renesas: r9a09g056: Remove entries for WDT{0,2,3}	2026-03-25 18:29:29 +01:00
r9a09g057-cpg.c	clk: renesas: r9a09g057: Add PCIe clocks and reset	2026-03-20 11:17:15 +01:00
r9a09g077-cpg.c	clk: renesas: r9a09g077: Add LCDC and PLL3 clock support for RZ/T2H display pipeline	2026-06-30 11:55:37 +02:00
rcar-cpg-lib.c	Convert 'alloc_obj' family to use the new default GFP_KERNEL argument	2026-02-21 17:09:51 -08:00
rcar-cpg-lib.h	clk: renesas: rcar-gen3: Switch to new SD clock handling	2021-11-19 11:32:39 +01:00
rcar-gen2-cpg.c	Convert 'alloc_obj' family to use the new default GFP_KERNEL argument	2026-02-21 17:09:51 -08:00
rcar-gen2-cpg.h	clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register	2025-06-10 10:20:45 +02:00
rcar-gen3-cpg.c	Convert 'alloc_obj' family to use the new default GFP_KERNEL argument	2026-02-21 17:09:51 -08:00
rcar-gen3-cpg.h	clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register	2025-06-10 10:20:45 +02:00
rcar-gen4-cpg.c	Convert 'alloc_obj' family to use the new default GFP_KERNEL argument	2026-02-21 17:09:51 -08:00
rcar-gen4-cpg.h	clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register	2025-06-10 10:20:45 +02:00
rcar-usb2-clock-sel.c	clk: Switch back to struct platform_driver::remove()	2024-09-21 14:12:05 -07:00
renesas-cpg-mssr.c	Renesas R-Car X5H CPG DT Binding Definitions	2026-08-05 17:30:33 +02:00
renesas-cpg-mssr.h	clk: renesas: Add support for R9A09G077 SoC	2025-06-10 10:24:17 +02:00
rzg2l-cpg.c	clk: various improvements and fixes	2026-08-17 09:27:10 -07:00
rzg2l-cpg.h	clk: renesas: rzg3s/rzg3l: Simplify PLL configuration macro	2026-05-22 10:24:32 +02:00
rzv2h-cpg-lib.c	clk: renesas: rzv2h-cpg: Extract PLL calculation helpers into shared library	2026-06-30 11:55:37 +02:00
rzv2h-cpg.c	Renesas R-Car X5H CPG DT Binding Definitions	2026-08-05 17:30:33 +02:00
rzv2h-cpg.h	clk: renesas: r9a09g047: Add support for SMUX2_DSI{0,1}_CLK	2026-05-04 14:03:08 +02:00