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clk: renesas: r9a08g046: Add USB2.0 clock and reset entries

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Add module clock and reset definitions for the USB2.0 interfaces on the
RZ/G3L (r9a08g046) SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260616104459.410743-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2026-06-16 11:44:45 +01:00 committed by Geert Uytterhoeven
parent 182b03cbe8
commit 2bbc0f34ef
1 changed files with 15 additions and 0 deletions
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15
drivers/clk/renesas/r9a08g046-cpg.c
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@ -416,6 +416,16 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
MSTOP(BUS_MCPU1, BIT(13))),
DEF_MOD("ssi3_pclk_sfr", R9A08G046_SSI3_PCLK_SFR, R9A08G046_CLK_P0, 0x570, 7,
MSTOP(BUS_MCPU1, BIT(13))),
DEF_MOD("usb_u2h0_hclk", R9A08G046_USB_U2H0_HCLK, R9A08G046_CLK_P1, 0x578, 0,
MSTOP(BUS_PERI_COM, BIT(5))),
DEF_MOD("usb_u2h1_hclk", R9A08G046_USB_U2H1_HCLK, R9A08G046_CLK_P1, 0x578, 1,
MSTOP(BUS_PERI_COM, BIT(7))),
DEF_MOD("usb_u2p0_exr_cpuclk", R9A08G046_USB_U2P0_EXR_CPUCLK, R9A08G046_CLK_P1, 0x578, 2,
MSTOP(BUS_PERI_COM, BIT(6))),
DEF_MOD("usb_pclk", R9A08G046_USB_PCLK, R9A08G046_CLK_P1, 0x578, 3,
MSTOP(BUS_PERI_COM, BIT(4))),
DEF_MOD("usb_u2p1_exr_cpuclk", R9A08G046_USB_U2P1_EXR_CPUCLK, R9A08G046_CLK_P1, 0x578, 4,
MSTOP(BUS_PERI_COM, BIT(13))),
DEF_MOD("eth0_clk_axi", R9A08G046_ETH0_CLK_AXI, R9A08G046_CLK_P1, 0x57c, 0,
MSTOP(BUS_PERI_COM, BIT(2))),
DEF_MOD("eth1_clk_axi", R9A08G046_ETH1_CLK_AXI, R9A08G046_CLK_P1, 0x57c, 1,
@ -531,6 +541,11 @@ static const struct rzg2l_reset r9a08g046_resets[] = {
DEF_RST(R9A08G046_SSI1_RST_M2_REG, 0x870, 1),
DEF_RST(R9A08G046_SSI2_RST_M2_REG, 0x870, 2),
DEF_RST(R9A08G046_SSI3_RST_M2_REG, 0x870, 3),
DEF_RST(R9A08G046_USB_U2H0_HRESETN, 0x878, 0),
DEF_RST(R9A08G046_USB_U2H1_HRESETN, 0x878, 1),
DEF_RST(R9A08G046_USB_U2P0_EXL_SYSRST, 0x878, 2),
DEF_RST(R9A08G046_USB_PRESETN, 0x878, 3),
DEF_RST(R9A08G046_USB_U2P1_EXL_SYSRST, 0x878, 4),
DEF_RST(R9A08G046_ETH0_ARESET_N, 0x87c, 0),
DEF_RST(R9A08G046_ETH1_ARESET_N, 0x87c, 1),
DEF_RST(R9A08G046_I2C0_MRST, 0x880, 0),