Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch
of unnecessary head scratching. Add aliases using the skl+ plane
names.
And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1
as we only ever have 0-2 sprites per pipe on those platforms.
v2: Don't break icl_nv12_y_plane_mask() (Jani)
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240517171208.21313-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
In some scenarios, the DPT object gets shrunk but
the actual framebuffer did not and thus its still
there on the DPT's vm->bound_list. Then it tries to
rewrite the PTEs via a stale CPU mapping. This causes panic.
Cc: stable@vger.kernel.org
Reported-by: Shawn Lee <shawn.c.lee@intel.com>
Fixes: 0dc987b699 ("drm/i915/display: Add smem fallback allocation for dpt")
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
[vsyrjala: Add TODO comment]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240520165634.1162470-1-vidya.srinivas@intel.com
Now that the PCI ID macros allow us to pass in the macro to use, stop
redefining INTEL_VGA_DEVICE.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240515165651.1230465-2-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
The PCI ID macros in xe_pciids.h allow passing in the macro to operate
on each PCI ID, making it more flexible. Convert i915_pciids.h to the
same pattern.
INTEL_IVB_Q_IDS() for Quanta transcode remains a special case, and
unconditionally uses INTEL_QUANTA_VGA_DEVICE().
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240515165651.1230465-1-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
The drm-intel repo is moving from the classic fd.o git host to GitLab.
Update its location with a URL matching other fd.o GitLab kernel trees.
Signed-off-by: Ryszard Knop <ryszard.knop@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Tvrtko Ursulin <tursulin@ursulin.net>
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240424114159.38719-1-ryszard.knop@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
On LunarLake maximum for IO and Fast Wake time line counts are 68: 6 bits +
5 lines added by the HW. Take this into account in calculation and when
writing the IO Wake lines.
v2: maximum line count is 68 (6 bits + 5 lines added by HW)
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-2-jouni.hogander@intel.com
Commit 8d4ba9fc1c ("drm/i915/selftests: Pick correct caching mode.")
was not complete as for non LLC sharing platforms cpu read can happen
from LLC which probably doesn't have the latest changes made by GPU.
Cc: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
Fixes: 8d4ba9fc1c ("drm/i915/selftests: Pick correct caching mode.")
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516151403.2875-1-nirmoy.das@intel.com
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
It's confusing for INTEL_CFL_IDS() to include all WHL and CML PCI
IDs. Even if we treat them the same in a lot of places, CML is a
platform of its own, and the lists of PCI IDs should not conflate them.
Largely go by the idea that if a platform has a name, group its PCI IDs
together.
That said, AML is special, having both KBL and CFL variants. Leave that
alone.
v2: Also split out WHL not just CML (Rodrigo)
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patchwork.freedesktop.org/patch/msgid/7cca91dc78ed2b5982f14e400f03a1704645e475.1715340032.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Having the plane WM/DDB regitster write functions in skl_watermarks.c
is rather annoying when trying to implement DSB based plane updates.
Move them into the respective files that handle all other plane
register writes. Less places where I need to worry about the DSB
vs. MMIO decisions.
The downside is that we spread the wm struct details a bit further
afield. But if that becomes too annoying we can probably abstract
things a bit more with a few extra functions.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-17-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Get rid of skl_ddb_entry_write() and skl_write_wm_level() and
just call intel_de_write_fw() directly.
This is prep work towards DSB based plane updates where these
wrappers are more of a hinderance.
Done with cocci mostly:
@@
expression D, R, L;
@@
- skl_write_wm_level(D, R, L)
+ intel_de_write_fw(D, R, skl_plane_wm_reg_val(L))
@@
expression D, R, B;
@@
- skl_ddb_entry_write(D, R, B)
+ intel_de_write_fw(D, R, skl_plane_ddb_reg_val(B))
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-16-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Currently every skl+ plane register defines some intermediate
macros to calculate the final register offset. Pull all of that
into common macros, simplifying the final register offset stuff
into just five defines:
- raw register offsets for the planes 1 and 2 on pipes A and B
- the final parametrized macro
v2: Rebase
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513170040.15393-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Rearrange the plane skl+ universal plane register definitions:
- keep everything related to the same register in one place
- sort based on register offset
- unify the whitespace/etc a bit
v2: Define register contents after all offsets (Jani)
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513165909.15234-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
On SKL+ the watermark/DDB registers are proper per-plane
registers. Move the definitons to their respective files.
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Move most of the SKL+ universal plane register definitions
into their own file. Declutters i915_reg.h a bit more.
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-3-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Add panel replay selective update support to debugfs status interface. In
case of sink supporting panel replay we will print out:
Sink support: PSR = no, Panel Replay = yes, Panel Replay Selective Update = yes
and PSR mode will look like this if printing out enabled panel replay
selective update:
PSR mode: Panel Replay Selective Update Enabled
Current PSR and panel replay printouts remain same.
Cc: Kunal Joshi <kunal1.joshi@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-13-jouni.hogander@intel.com
Part of intel_psr2_config_valid is valid for panel replay. rename it as
intel_sel_update_config_valid. Split psr2 specific part and name it as
intel_psr2_config_valid.
v3:
- move early transport check to psr2 specific check
- check intel_psr2_config_valid only for non-Panel Replay case
v2:
- use psr2_global_enabled for panel replay as well
- goto unsupported instead of return when global enabled check fails
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-12-jouni.hogander@intel.com
We are re-using PSR module parameters for panel replay. Update module
parameter descriptions with panel replay information:
enable_psr:
-1 (default) == follow what is in VBT
0 == disable PSR/PR
1 == Allow PSR1 and PR full frame update
2 == allow PSR1/PSR2 and PR Selective Update
enable_psr2_sel_fetch
0 == disable selective fetch for PSR and PR
1 (default) == allow selective fetch for PSR PR
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-11-jouni.hogander@intel.com
DP Panel replay uses SRD_STATUS to track it's status despite selective
update mode.
Bspec: 53370, 68920
v4:
- use PSR2_STATUS for eDP Panel Replay
- handle intel_psr_wait_exit_locked as well
v3:
- do not use PSR2_STATUS for PSR1
v2:
- use intel_dp_is_edp to differentiate
- modify debugfs status as well
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-9-jouni.hogander@intel.com
