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drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define

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Stop hand rolling PLANE_AUX_OFFSET() and just use the real thing.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-7-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä 2024-05-10 18:23:19 +03:00
parent b86f87af34
commit 9d7d1e8b1c
3 changed files with 24 additions and 26 deletions
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24
drivers/gpu/drm/i915/gvt/handlers.c
View File

@ -2693,20 +2693,20 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);

2
drivers/gpu/drm/i915/gvt/reg.h
View File

@ -57,8 +57,6 @@
#define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100)
#define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))
#define REG50080_FLIP_TYPE_MASK 0x3

24
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
View File

@ -1018,18 +1018,18 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(PLANE_AUX_DIST(PIPE_C, 1));
MMIO_D(PLANE_AUX_DIST(PIPE_C, 2));
MMIO_D(PLANE_AUX_DIST(PIPE_C, 3));
MMIO_D(_MMIO(_REG_701C4(PIPE_A, 1)));
MMIO_D(_MMIO(_REG_701C4(PIPE_A, 2)));
MMIO_D(_MMIO(_REG_701C4(PIPE_A, 3)));
MMIO_D(_MMIO(_REG_701C4(PIPE_A, 4)));
MMIO_D(_MMIO(_REG_701C4(PIPE_B, 1)));
MMIO_D(_MMIO(_REG_701C4(PIPE_B, 2)));
MMIO_D(_MMIO(_REG_701C4(PIPE_B, 3)));
MMIO_D(_MMIO(_REG_701C4(PIPE_B, 4)));
MMIO_D(_MMIO(_REG_701C4(PIPE_C, 1)));
MMIO_D(_MMIO(_REG_701C4(PIPE_C, 2)));
MMIO_D(_MMIO(_REG_701C4(PIPE_C, 3)));
MMIO_D(_MMIO(_REG_701C4(PIPE_C, 4)));
MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 0));
MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 1));
MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 2));
MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 3));
MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 0));
MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 1));
MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 2));
MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 3));
MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 0));
MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1));
MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2));
MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3));
MMIO_D(_MMIO(_PLANE_CTL_3_A));
MMIO_D(_MMIO(_PLANE_CTL_3_B));
MMIO_D(_MMIO(0x72380));