Right now some device nodes set default pinctrl within msm8916.dtsi
(e.g. I2C, SPI), but for others it needs to be explicitly set in the
board-specific device tree (e.g. UART).
While it is theoretically possible that some super special board
needs different pinctrl for these, in practice pretty much every
board ends up using the common pinctrl definitions.
Make this consistent by also defining the common pinctrl properties
for blsp1_uart1 and blsp1_uart2 so we don't need to copy this for every
board. If there is really such a super special board it could just
override these properties with custom pinctrl or make minor modifications
to the common pinctrl configurations provided by msm8916-pins.dtsi.
Also move #address-cells/#size-cells for &dsi0 to msm8916.dtsi
since this is specific to the DSI node, not the board.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-10-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
So far we had some supplies defined for all boards in msm8916.dtsi,
while others were duplicated into every board-specific device tree.
Now that we have msm8916-pm8916.dtsi as a common include for all
standard MSM8916 devices using PM8916, move the remaining common
supplies to msm8916-pm8916.dtsi to reduce duplication a bit.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-9-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Device trees for newer SoCs avoid defining the regulator nodes directly
in the SoC device tree (here: msm8916.dtsi). The reason for this is that
theoretically it is possible to combine the SoC with a different PMIC,
or to use all the regulators in a board-specific way.
Therefore let's remove those from the SoC include (msm8916.dtsi).
In practice, pretty much all MSM8916 boards were combined with PM8916,
and use the regulators in similar ways. After looking at many different
MSM8916 boards (mostly smartphones and tablets), I haven't seen a single
device that isn't using the same regulators for components integrated
into the SoC.
If all boards end up defining all regulators and supplies in the same way
then it is useful to have an include for that, so we can avoid duplicating
it everywhere. If there is really a super special board that does it
differently it could just override some properties or avoid using the
include altogether.
This patch moves the regulator and common supply definitions to
a new include called "msm8916-pm8916.dtsi".
This is also going to be useful when introducing CPR (Core Power
Reduction) later because we can configure the CPU regulator
(pm8916_spmi_s2) for all devices in this common include.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-8-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Right now we define the entire pm8916 resin node separately in
the board-specific device tree part, including the interrupt that
belongs to PM8916.
As a feature of the PMIC it should be declared in pm8916.dtsi,
disabled by default. Like all other optional components it can then
by enabled and configured in the board-specific device tree part.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-7-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Device trees for newer SoCs avoid replicating the entire device
hierarchy in the board-specific device tree part. Instead,
they set additional properties only by referencing labels,
sorted alphabetically.
Now that we have labels for all relevant nodes, convert the MSM8916
board device trees to use the same style and remove the "soc" node
entirely.
Note: There is a large block of coresight nodes in apq8016-sbc.dtsi,
which are enabled by setting status = "okay". I kept them grouped
together (not alphabetically sorted with everything else),
since that would be just unnecessarily verbose and hard to see.
This commit only moves all existing properties to nodes that reference
the respective label. The resulting binary DTBs are exactly the same.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-6-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add a few more labels to device nodes declared in msm8916.dtsi
so that we can set all needed properties using labels in the
board-specific device tree part.
Also rename the "otg" label to "usb" to allow grouping it with
the USB PHY (usb_hs_phy) node when ordering referenced labels
alphabetically.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-5-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The leds node does not use any memory regions of the SoC and should
therefore be declared outside the "soc" node.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-4-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The "sound" node in apq8016-sbc.dtsi references memory regions
provided by the SoC and should be therefore declared in msm8916.dtsi.
Additionally, the machine driver used for the "qcom,apq8016-sbc-sndcard"
compatible also works on other MSM8916 devices (provided that audio
routing is set up properly). It is not really specific to apq8016-sbc.
Simplify setting up sound on other boards by moving the common part
to msm8916.dtsi. This also allows referencing the node by the label,
so that we can eventually drop the "soc" node entirely from the
board-specific device tree part and use labels exclusively.
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-3-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
apq8016-sbc.dtsi overrides several properties that are already the
default in msm8916.dtsi. Remove these to simplify the device tree
a bit.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200720085406.6716-2-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the necessary pinctrl, interrupt property and a suitable sleep config
to support Bluetooth wakeup feature.
GPIO mode is configured in sleep state to drive the RTS/RFR line low.
If QUP function is selected in sleep state, UART RTS/RFR is pulled high
during suspend and BT SoC not able to send wakeup bytes.
Tested-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: satya priya <skakit@codeaurora.org>
Link: https://lore.kernel.org/r/1600091917-7464-4-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the necessary pinctrl, interrupt property and a suitable sleep config
to support Bluetooth wakeup feature.
GPIO mode is configured in sleep state to drive the RTS/RFR line low.
If QUP function is selected in sleep state, UART RTS/RFR is pulled high
during suspend and BT SoC not able to send wakeup bytes.
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: satya priya <skakit@codeaurora.org>
Link: https://lore.kernel.org/r/1600091917-7464-3-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Remove output-high from CTS and TX as this is not really required. During
bringup to fix transfer failures this was added to match with console uart
settings. Probably some boot loader config was missing then. As it is
working fine now, remove it.
Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/1600091917-7464-2-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Some trogdor board variants only have one USB port, so add a couple
labels to these ports so we can modify them later.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20200914232218.658664-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Also add a space after '=' while at it.
Tested-by: Konrad Dybcio <konradybcio@gmail.com>
Signed-off-by: Łukasz Patron <priv.luk@gmail.com>
Link: https://lore.kernel.org/r/20200725082417.8507-1-priv.luk@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two
where the second cell is the irq flags. Drop the second cell to match
the binding.
Cc: Kalyan Thota <kalyan_t@codeaurora.org>
Cc: Harigovindan P <harigovi@codeaurora.org
Fixes: a3db7ad1af ("arm64: dts: sc7180: add display dt nodes")
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20200811192503.1811462-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Document the new device-tree bindings for boards
HK10-C1 and HK10-C2 based on ipq8074 SoC.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Link: https://lore.kernel.org/r/1596706332-12957-2-git-send-email-gokulsri@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
While the DT parser recognizes "ok" as a valid value for the
"status" property, it is actually mentioned nowhere. Use the
proper value "okay" instead, as done in the majority of files
already.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Link: https://lore.kernel.org/r/20200830200845.1771-1-freifunk@adrianschmutzler.de
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Removed voting for RPMH_RF_CLK2 which is not required as it is
getting managed by BT SoC through SW_CTRL line.
Signed-off-by: Venkata Lakshmi Narayana Gubba <gubbaven@codeaurora.org>
Link: https://lore.kernel.org/r/1599734980-22580-1-git-send-email-gubbaven@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add initial dts support for Xiaomi Poco F1 (Beryllium).
This initial support is based on upstream Dragonboard 845c
(sdm845) device. With this dts, Beryllium boots AOSP up to
ADB shell over USB-C.
Supported functionality includes UFS, USB-C (peripheral),
microSD card and Vol+/Vol-/power keys. Bluetooth should work
too but couldn't be verified from adb command line, it is
verified when enabled from UI with few WIP display patches.
Just like initial db845c support, initializing the SMMU is
clearing the mapping used for the splash screen framebuffer,
which causes the device to hang during boot and recovery
needs a hard power reset. This can be worked around using:
fastboot oem select-display-panel none
To switch ON the display back run:
fastboot oem select-display-panel
But this only works on Beryllium devices running bootloader
version BOOT.XF.2.0-00369-SDM845LZB-1 that shipped with
Android-9 based release. Newer bootloader version do not
support switching OFF the display panel at all.
Reviewed-by: Konrad Dybcio <konradybcio@gmail.com>
Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
Link: https://lore.kernel.org/r/1599840940-18144-1-git-send-email-amit.pundir@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Move the bus clock to mdp device node,in order
to facilitate bus band width scaling on sc7180
target.
The parent device MDSS will not vote for bus bw,
instead the vote will be triggered by mdp device
node. Since a minimum vote is required to turn
on bus clock, move the clock node to mdp device
from where the votes are requested.
This patch has dependency on the below series
https://patchwork.kernel.org/patch/11468783/
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Link: https://lore.kernel.org/r/1594899334-19772-2-git-send-email-kalyan_t@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the bandwidth domain supporting performance state and
the corresponding OPP tables for the sdhc device on sc7180.
Signed-off-by: Pradeep P V K <ppvk@codeaurora.org>
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Link: https://lore.kernel.org/r/1597646464-1863-1-git-send-email-sbhanu@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The 'sustainable_power' attribute provides an estimate of the sustained
power that can be dissipated at the desired control temperature. One
could argue that this value is not necessarily the same for all devices
with the same SoC, which may have different form factors or thermal
designs. However there are reasons to specify a (default) value at SoC
level for SC7180: most importantly, if no value is specified at all the
power_allocator thermal governor (aka 'IPA') estimates a value, using the
minimum power of all cooling devices of the zone, which can result in
overly aggressive thermal throttling. For most devices an approximate
conservative value should be more useful than the minimum guesstimate
of power_allocator. Devices that need a different value can overwrite
it in their <device>.dts. Also the thermal zones for SC7180 have a high
level of granularity (essentially one for each function block), which
makes it more likely that the default value just works for many devices.
The values correspond to 1901 MHz for the big cores, and 1804 MHz for
the small cores. The values were determined by limiting the CPU
frequencies to different max values and launching a bunch of processes
that cause high CPU load ('while true; do true; done &' is simple and
does a good job). A frequency is deemed sustainable if the CPU
temperatures don't rise (consistently) above the second trip point
('control temperature', 95 degC in this case). Once the highest
sustainable frequency is found, the sustainable power can be calculated
by multiplying the energy consumption per core at this frequency (which
can be found in /sys/kernel/debug/energy_model/) with the number of
cores that are specified as cooling devices.
The sustainable frequencies were determined at room temperature
on a device without heat sink or other passive cooling elements.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/20200813113030.1.I89c33c4119eaffb986b1e8c1bc6f0e30267089cd@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This change adds the interconnect bindings to the
MDSS node. This will establish Display to DDR path
for bus bandwidth voting.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Link: https://lore.kernel.org/r/1594899334-19772-1-git-send-email-kalyan_t@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Update the clock controller nodes for Low power audio subsystem
functionality.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1596305615-5894-2-git-send-email-tdas@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Only User4, WLAN and BT LEDs are added for now. These GPIOs are coming
from PM8150. Rest are coming from LPG block which is not supported yet!
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200904063637.28632-5-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add basic devicetree support for Qualcomm Technologies, Inc. Robotics
RB5 platform. This board is one of the 96Boards CE platform targeted for
Robotics usecases from Qualcomm.
This basic devicetree support includes regulators, onboard debug UART,
I2C, SPI, and UFS support.
Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200904063637.28632-4-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The UART12 node has been mistakenly mentioned as UART2. Let's fix that
for both SM8250 SoC and MTP board and also add pinctrl definition for
it.
Fixes: 60378f1a17 ("arm64: dts: qcom: sm8250: Add sm8250 dts file")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200904063637.28632-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This is essentialy a squash of a bunch of history of trogdor and lazor
dt updates from the chromium kernel tree.
I don't claim any credit other than wanting to more easily boot upstream
kernel on these devices.
I've tried to add cc tags for all the original authors.
Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Matthias Kaehlcke <mka@chromium.org>
Cc: Atul Dhudase <adhudase@codeaurora.org>
Cc: Venkata Lakshmi Narayana Gubba <gubbaven@codeaurora.org>
Cc: Evan Green <evgreen@chromium.org>
Cc: Cheng-Yi Chiang <cychiang@chromium.org>
Cc: Ajit Pandey <ajitp@codeaurora.org>
Cc: Alexandru Stan <amstan@chromium.org>
Cc: Sujit Kautkar <sujitka@chromium.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20200828204052.2085508-1-robdclark@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
There is one LLCC logical bank(LLCC0) on SC7180 SoC and the
size of the LLCC0 base is 0x50000(320KB) not 2MB, so correct
the size and fix copy paste mistake carried over from SDM845.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Fixes: 7cee5c7428 ("arm64: dts: qcom: sc7180: Fix node order")
Fixes: c831fa2999 ("arm64: dts: qcom: sc7180: Add Last level cache controller node")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/20200818145514.16262-1-saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Constants were used to allow merging separately from the dt-bindings,
switch to symbolic names now that dt-bindings have landed.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20200818160445.14008-3-jonathan@marek.ca
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Constants were used to allow merging separately from the dt-bindings,
switch to symbolic names now that dt-bindings have landed.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20200818160445.14008-2-jonathan@marek.ca
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The compatible for hsphy has out of place indentation, and the assigned
clock rate for GCC_USB30_PRIM_MASTER_CLK is incorrect, the clock doesn't
support a rate of 150000000. Use a rate of 200000000 to match downstream.
Fixes: b33d2868e8 ("arm64: dts: qcom: sm8150: Add USB and PHY device nodes")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20200818160445.14008-1-jonathan@marek.ca
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
As per binding documentation, we should have dsi as node 0 and hdmi
audio as node 1, so fix it
Reported-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: aef9a119df ("arm64: dts: qcom: sdm845-db845c: Add hdmi bridge nodes")
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20200828074347.3788518-1-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
