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arm64: dts: qcom: msm8916: Add more labels
Add a few more labels to device nodes declared in msm8916.dtsi so that we can set all needed properties using labels in the board-specific device tree part. Also rename the "otg" label to "usb" to allow grouping it with the USB PHY (usb_hs_phy) node when ordering referenced labels alphabetically. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200720085406.6716-5-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Stephan Gerhold
Bjorn Andersson
parent
48faf07941
commit
2329e5fb54
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@ -781,7 +781,7 @@ sdhc_2: sdhci@7864000 {
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status = "disabled";
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};
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otg: usb@78d9000 {
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usb: usb@78d9000 {
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compatible = "qcom,ci-hdrc";
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reg = <0x78d9000 0x200>,
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<0x78d9200 0x200>;
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@ -809,7 +809,7 @@ usb_hs_phy: phy {
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#phy-cells = <0>;
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clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
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clock-names = "ref", "sleep";
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resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
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resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
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reset-names = "phy", "por";
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qcom,init-seq = /bits/ 8 <0x0 0x44
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0x1 0x6b 0x2 0x24 0x3 0x13>;
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@ -1151,7 +1151,7 @@ dsi_phy0: dsi-phy@1a98300 {
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};
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hexagon@4080000 {
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mpss: hexagon@4080000 {
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compatible = "qcom,q6v5-pil";
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reg = <0x04080000 0x100>,
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<0x04020000 0x040>;
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@ -1289,7 +1289,7 @@ wifi {
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};
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};
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tpiu@820000 {
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tpiu: tpiu@820000 {
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compatible = "arm,coresight-tpiu", "arm,primecell";
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reg = <0x820000 0x1000>;
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@ -1307,7 +1307,7 @@ tpiu_in: endpoint {
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};
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};
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funnel@821000 {
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funnel0: funnel@821000 {
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0x821000 0x1000>;
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@ -1348,7 +1348,7 @@ funnel0_out: endpoint {
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};
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};
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replicator@824000 {
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replicator: replicator@824000 {
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compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
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reg = <0x824000 0x1000>;
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@ -1384,7 +1384,7 @@ replicator_in: endpoint {
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};
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};
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etf@825000 {
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etf: etf@825000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x825000 0x1000>;
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@ -1410,7 +1410,7 @@ etf_out: endpoint {
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};
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};
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etr@826000 {
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etr: etr@826000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x826000 0x1000>;
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@ -1428,7 +1428,7 @@ etr_in: endpoint {
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};
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};
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funnel@841000 { /* APSS funnel only 4 inputs are used */
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funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0x841000 0x1000>;
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@ -1476,7 +1476,7 @@ funnel1_out: endpoint {
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};
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};
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debug@850000 {
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debug0: debug@850000 {
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compatible = "arm,coresight-cpu-debug","arm,primecell";
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reg = <0x850000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>;
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@ -1485,7 +1485,7 @@ debug@850000 {
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status = "disabled";
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};
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debug@852000 {
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debug1: debug@852000 {
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compatible = "arm,coresight-cpu-debug","arm,primecell";
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reg = <0x852000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>;
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@ -1494,7 +1494,7 @@ debug@852000 {
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status = "disabled";
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};
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debug@854000 {
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debug2: debug@854000 {
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compatible = "arm,coresight-cpu-debug","arm,primecell";
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reg = <0x854000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>;
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@ -1503,7 +1503,7 @@ debug@854000 {
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status = "disabled";
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};
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debug@856000 {
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debug3: debug@856000 {
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compatible = "arm,coresight-cpu-debug","arm,primecell";
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reg = <0x856000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>;
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@ -1598,7 +1598,7 @@ etm3_out: endpoint {
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/* System CTIs */
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/* CTI 0 - TMC connections */
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cti@810000 {
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cti0: cti@810000 {
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compatible = "arm,coresight-cti", "arm,primecell";
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reg = <0x810000 0x1000>;
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@ -1609,7 +1609,7 @@ cti@810000 {
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};
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/* CTI 1 - TPIU connections */
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cti@811000 {
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cti1: cti@811000 {
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compatible = "arm,coresight-cti", "arm,primecell";
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reg = <0x811000 0x1000>;
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@ -1623,7 +1623,7 @@ cti@811000 {
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/* Core CTIs; CTIs 12-15 */
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/* CTI - CPU-0 */
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cti@858000 {
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cti12: cti@858000 {
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compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
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"arm,primecell";
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reg = <0x858000 0x1000>;
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@ -1638,7 +1638,7 @@ cti@858000 {
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};
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/* CTI - CPU-1 */
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cti@859000 {
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cti13: cti@859000 {
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compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
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"arm,primecell";
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reg = <0x859000 0x1000>;
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@ -1653,7 +1653,7 @@ cti@859000 {
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};
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/* CTI - CPU-2 */
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cti@85a000 {
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cti14: cti@85a000 {
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compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
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"arm,primecell";
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reg = <0x85a000 0x1000>;
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@ -1668,7 +1668,7 @@ cti@85a000 {
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};
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/* CTI - CPU-3 */
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cti@85b000 {
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cti15: cti@85b000 {
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compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
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"arm,primecell";
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reg = <0x85b000 0x1000>;
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@ -1821,7 +1821,7 @@ rpm {
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qcom,ipc = <&apcs 8 0>;
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qcom,smd-edge = <15>;
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rpm-requests {
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rpm_requests: rpm-requests {
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compatible = "qcom,rpm-msm8916";
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qcom,smd-channels = "rpm_requests";
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