Take a snapshot of our SMMU driver as of commit f843a80d2c45 ("Merge
"defconfig: gen3auto: Separated if_changed"") on msm-5.15. Change
the devm_request_threaded_irq() and devm_free_irq() calls in
arm_smmu_interrupt_selftest() to request_threaded_irq() and free_irq()
respectively, since we release the resources within the same function
that is also only being called during probe.
Change-Id: Ib3fea5b0cfb4e78eebacecfd7cb24e17000fda5e
Signed-off-by: Chris Goldsworthy <quic_cgoldswo@quicinc.com>
Add in qcom_iommu_util.ko as arm_smmu.ko depends on it.
Change-Id: I05c29816f0baff03fda8e5cb82f3e4876b9a1f1e
Signed-off-by: Chris Goldsworthy <quic_cgoldswo@quicinc.com>
This change adds APIs to start/stop camera RSC channels
which can be used by clients.
Update the rpmh_rsc_get_channel() to select unused channel
to flush the cached sleep and wake requests.
Also assume the 'solver' state during probe to disallow
RPMH_ACTIVE_ONLY_STATE requests.
Change-Id: I0ea6aa9f8d2961428636961d3cb53f5e67f37f54
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Add support to probe multiple DRVs in a single RSC device. Each
DRV can have TCSes spread in channels for use by a hardware directly
communicating with the RSC.
A 'channel' is a collection of TCS groups, that may independently
be used by the RSC sequencer. The channel number will be derrived
from the device that is making an RPMH request and to support same
add channel parameter to all RPMH requests.
Each channel can cache the sleep and wake requests independently
and when the rpmh_flush() is requested by a device the respective
channel's cached data will be written to the TCSes.
The existing RSCes can be considered running with a single channel.
Change-Id: Id0956136f37c28f2039e139d21f63ade5044ae1f
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
rpmh_rsc_debug() can race with tcs_tx_done() interrupt handler and
may not see any tcs busy and hence won't do bug_on(). Later it may
go ahead and free() the request which interrupt handler is processing.
Lets always bug_on() upon timeout.
Change-Id: I238a6a3639077850df158cb1f0190656e014bb57
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
rpm_msgs address is calculated from memory allocated during write_batch.
Correct the offset from where rpm_msgs actually starts and assign req
pointer to point to correct address.
Also add list_del before freeing memory in rpmh_invalidate.
Change-Id: Idca43fe73bd238e90911158b08b3889c001e1123
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
RSC major version 3.0 has different register offsets than previous
versions. Add support to read the current version during probe and
use register offsets accordingly.
Change-Id: I8174516ecd2ab7a370e1bb6592d4329c4ff1f81d
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
In addition to logging using FTRACE. let's also log in the IPC logging
for all RPMH transactions.
Change-Id: I2b19006bbc776053f63eee55b447428fdb023ba4
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
The RSC interrupt is issued only after the request is complete. For
fire-n-forget requests, the irq-done interrupt is sent after issuing the
RPMH request and for response-required request, the interrupt is
triggered only after all the requests are complete.
These unnecessary checks in the interrupt handler issues AHB reads from
a critical path. Let's remove them and clean up error handling in
rpmh_request data structures.
Change-Id: Ie3a3569603f001d6cdb59310c3f2752cdcd7a84d
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
When we crash the system and display the TCS controller state, let's
also dump the fast-path TCS information if there was an active
transaction going on at that time.
Change-Id: Iabc7b8af22dd148fca617e571f1392ba3d9a93ab
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Add fast-path interface for making a lock-less RPMH request. The
interface provides APIs that can be called from a interrupt/scheduler
context. The _init_ call shall be used to initialize the dedicated TCS
with {addr, data} and subsequent calls shall _update_ the data and
trigger the request immediately.
Only active state requests shall be sent through these interfaces.
Requests to remove the vote during sleep and re-apply the vote during
wake must use the regular rpmh_write/_async variants APIs (locking).
Change-Id: I2505fc487ddca1a32185b116c0d8680818dfd2b8
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
GPIOs that can be configured as wakeup are routed to the PDC wakeup
interrupt controller and from there to the GIC interrupt controller. On
some QCOM SoCs, the interface to the GIC for wakeup capable GPIOs have
additional hardware registers that need to be configured as well to
match the trigger type of the GPIO. This register interfaces the PDC to
the GIC and therefore updated from the PDC driver.
Typically, the firmware intializes the interface registers for the
wakeup capable GPIOs with commonly used GPIO trigger type, but it is
possible that a platform may want to use the GPIO differently. So, in
addition to configuring the PDC, configure the interface registers as
well.
Change-Id: I73250a04f67549dbf75c40b3672b6b1b78ff8adb
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
In order to support lockless RPMh request, let's dedicate a TCS for this
purpose. This TCS shall be defined as FAST_PATH_TCS in the TCS
configuration for the RSC.
The fast-path TCS will have the following properties -
- A single TCS shall be defined as a fast-path TCS.
- Fast-path TCS will not use interrupt for signalling request
completion.
- Fast path will poll controller status for idle before sending request.
- DRV properties are not updated during the fast-path use.
- Fast path requests must be first initialized with {addr, data}.
- Subsequent updates will only update the data in the TCS and trigger.
- Requests must be fire-n-forget only (no completion).
Change-Id: I235ea60159e40affa9ce1e4069e11eca3925a423
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Add a new definition for fast-path TCS configuration.
Change-Id: I610b14dcd893885e5b1c32c434caa7aa7102fd4c
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
In OS-Initiated mode of PSCI, a serialization is established in Linux
between the last CPU powering down the cluster / domain and the CPU
powering up back. The serialization is established by the genpd
framework and therefore it doesn't help to lock around the cache.
Refactor out the core of the flush functionality from the locking
wrappers. Calling the core functionality avoids a spin trylock, which
the RCU framework might consider suspicious under the circumstances.
Change-Id: I242fb4827b71152bda36ea5870393054b8703309
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
RSC is part the CPU subsystem and powers off the CPU domains when all
the CPUs and no RPMH transactions are pending from any of the drivers.
The RSC needs to flush the 'sleep' and 'wake' votes that are critical
for saving power when all the CPUs are in idle. Doing this every time a
CPU powers down, increases latency to enter idle state. So, we want to
do this, only when it makes sense - when the last CPU is powering down.
Let's make RSC part of the CPU PM domains, by attaching it to the
cluster PD (defined in DT). Registering for PM domain notifications, RSC
driver can be notified that the last CPU is powering down. When the last
CPU is powering down the domain, let's flush the 'sleep' and 'wake'
votes that are stored in the data buffers into the hardware.
Change-Id: Id748413f0f86a4ac73c37e0780b2b22a143a1e61
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
lockdep_assert_irqs_disabled() was added to check rpmh_flush() can
only be invoked when irqs are disabled, this is true for APPS RSC
as the last CPU going to deepest low power mode is writing sleep and
wake TCSes.
However for Display RSC, drivers can invoke rpmh_write_sleep_and_wake()
to immediately write cached sleep and wake sets to TCSes from any CPU.
Conditionally check if RSC controller supports solver mode then do not
check for irqs disabled as such RSC can write sleep and wake TCSes at any
point.
Change-Id: I8ad05cd81af15a0d57353b55d8098cf0e47f79f7
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Let clients call rpmh_write_sleep_and_wake() to immediately
write cached sleep and wake data to the TCSes.
Change-Id: I04a94ee622a39a0aa0e829f4c40190a870fb2fb1
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Allow RPMH requests to succeed even when the always-On subsystem is not
available. In standalone mode, requests are never sent to the TCS
mailbox driver. The command DB provides the information to make the
decision to run in standalone mode or not.
Change-Id: Ia2bc5024da0d7e6607347b1a481b2feb9584059a
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Controllers may be in 'solver' state, where they could be in autonomous
mode executing low power modes for their hardware and as such are not
available for sending active votes. Device driver may notify RPMH API
that the controller is in solver mode and when in such mode, disallow
requests from platform drivers for state change using the RSC.
Change-Id: Ibe777d23fd58489cfb8132c0168af8e29284084d
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Add xo_pad clk to capture xo_pad frequency separately from
bi_tcxo for chips where bi_tcxo and xo_pad frequencies are not
same. This allows consumers to query xo_pad frequency and also
vote on it.
Change-Id: I4af28c4aa23a58298ccbf3dda7b559dd3a95a97c
Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
Output the TCS state when the debug api is invoked. The state of the
TCS, the contents and the IRQ status is presented. Additionally, crash
the system if any TCS is busy to help with the debug.
Change-Id: I7ef5480cc6da7208d5f82351d863561fcc1abf68
Signed-off-by: Raju P.L.S.S.S.N" <rplsssn@codeaurora.org>
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
The command DB may be initialized outside the AOP, indicated by the
reserved bit 0. Export this information through a function.
Change-Id: I7b8c685cc03d919c5adb1b91134078bd96599bbd
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Enable CommandDB, RPMH communication and PDC irqchip drivers.
Change-Id: I1477df988732147a05e0fe87e344a9d4ff951ad3
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Take a snapshot of our qcom-iommu-util module as of commit
f843a80d2c45 ("Merge "defconfig: gen3auto: Separated if_changed"") on
msm-5.15. Update minor lint warnings with respect to header inclusions
and spacing.
Change-Id: Ib33f54f081eb029ade172254a6732c49dcf1f73d
Signed-off-by: Chris Goldsworthy <quic_cgoldswo@quicinc.com>
