Add remote debugger device configuration. The Remote Debugger driver
allows a debugger running on a host PC to communicate with a remote
stub running on peripheral subsystems.
Change-Id: Ib3faed59b8f54213341aa52248e33091fffea061
Signed-off-by: Devender Kaushik <quic_dkaushik@quicinc.com>
These changes enable IPCC_COMPUTE_L0 signals and
broadcast client. These will be used by the new IPCLite
communication protocol to communicate with
remote subsystems over compute_l0 interrupt line.
Change-Id: I7aac6f121c53136b8cc19f1d1e166ccc2d59caee
Signed-off-by: smaniar <smaniar@codeaurora.org>
Log qrtr rx packet in kernel logs which caused system wakeup.
This will help to easily identify wakeup packet.
The qrtr module is required to be in first stage init to support
the creation of qrtr sockets. The transport layers are often in second
stage init. The current wakeup prints depend on some information from
the second stage init. Rework the logic so the dependency is only
between the qrtr transport and transport drivers.
Change-Id: I4a6a35dd4d5449a671464c00f90712a79d6044fe
Signed-off-by: Deepak Kumar Singh <deesin@codeaurora.org>
Signed-off-by: Chris Lew <quic_clew@quicinc.com>
Add tmecom, hwkm and ice-crypto drivers for pineapple.
These are mainly used for supporting storage encryption
using HWKM (residing in TME).
Change-Id: I38c97654a643f8545bd56aa559ccba588aabbb90
Signed-off-by: Smita Ghosh <quic_smitag@quicinc.com>
Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
Enable the USB GSI driver to support tethering interfaces, such as RNDIS
and RmNET.
Change-Id: I0273e97f7656e1cca4a353b55e7254053352b2b9
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Add symbols being used by the USB f_gsi function driver.
Change-Id: I5102ae04665e5eca291855f05157159c3e37d313
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
The IPA framework will be moved outside of the kernel tree, which USB GSI
was referencing. In order to call USB IPA operations, the IPA module will
call an exported ready callback from the USB GSI driver, and pass along the
function pointers for the IPA ops.
Add the ready callback API, and modify pre-existing IPA ops to reference
the function pointers received from the IPA module.
Change-Id: I8e766548fa76ee4d838d113bb5b61577b99c90dd
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Kleaf replaces build.sh. Define pineapple target in Bazel
so it may be built with the following command:
tools/bazel run //msm-kernel:pineapple_gki
Change-Id: If78ea5482898f92b751cad8542401ba12d9663bf
Signed-off-by: John Moon <quic_johmoo@quicinc.com>
The Remote Debugger driver allows a debugger running
on a host PC to communicate with a remotestub running
on peripheral subsystems.
This snapshot was taken as of msm-5.15 'commit 095d029b5af0
("msm: rdbg: return correct error codes")'.
Change-Id: I4d0fb93fcb4fd0d7ffec8e900e4fd047f4579b5b
Signed-off-by: Devender Kaushik <quic_dkaushik@quicinc.com>
Currently ufs phy driver is voting for .8V as min range for
phy regulator but spec says it should be .88V
Update phy min phy voltage limit per spec.
Change-Id: Ib1ce7830ec91ef388030ffc3358b26ae4ae6cea2
Signed-off-by: Ram Prakash Gupta <quic_rampraka@quicinc.com>
Signed-off-by: Ziqi Chen <quic_ziqichen@quicinc.com>
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Add support to trigger the gpio when config the trigin and trigout.
Change-Id: I85813c091c9d6d389192827f51acf48f0189cec1
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Wakeup enable bit controls the interrupt routing to parent PDC irqchip.
These gets set during interrupt allocation for the GPIOs which are used
as interrupt or via firmware.
However sometimes clients may want to set it without requesting interrupt
line for it. This was done via msm_gpio_mpm_wake_set() API.
On newer targets the bit position for wakeup enable bit is changed to
interrupt config register. Modify msm_gpio_mpm_wake_set() accordingly.
Change-Id: I7441595b49e35181831b1015a41b054b435e07a9
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
When debugcc did not register, measure/mux will be NULL.
Avoid accessing it.
Change-Id: I037151e258ae85c89c9db87254e5b8ea850157a0
Signed-off-by: Veera Vegivada <quic_vvegivad@quicinc.com>
rebuild_sched_domains() is called during walt_init with the assumption
that cpufreq_online has actually completed before the execution of
walt_init. This is only partially true.
cpufreq_online() will notify update_topology_flags_workfn once the
policies have been created. However, the em creation is after this
point in time.
This creates a race condition between cpufreq_online's creation
of the energy model through it's call to register_em(policy), and
walt's execution of rebuild_sched_domains. If walt init completes
quickly, and rebuild_sched_domains() is executed quickly, it is
possible it will complete before the energy model is registered.
Thus, the perf domains will still be unpopulated, and the error
detection for perf domains will cause the system to crash.
Address this by ensuring that the energy model has run for each
cpu in the system by checking the same field that em_create_pd
must populate for build_perf_domains to work properly, the
em_pd field in the cpu device.
Additionally ensure that this is only attempted if the domains are
not yet setup properly and it is known that corrective action
must take place.
Change-Id: I8f5150fe4e2e37b3820e809232f26ff207723601
Signed-off-by: Stephen Dickey <quic_dickey@quicinc.com>
Ensure that all thermal pressure gets accounted in capacity_orig
as soon as it is set, rather than during the window rollover period.
Change-Id: Ia22cb87f0d1fcb23f1a932f9b70637861b56ae33
Signed-off-by: Shaleen Agrawal <quic_shalagra@quicinc.com>
If the energy model is not updated by the time rebalance_domains
is called for the first time, the root domain -> perf_domain
values will get erased completely, and will be invalid. The
responsibility for this race is outside of the walt module.
walt_find_energy_efficient_cpu() relies upon rd->pd being valid
and cannot function properly without it. This is critical to
proper walt functionality and it cannot move forward without it.
Decisvely catch the failure.
Change-Id: Iee8030afd487dcee1d9cc18c2d655ecc26938279
Signed-off-by: Stephen Dickey <quic_dickey@quicinc.com>
There is a race condition in cpufreq.c in which the energy model
is not updated until after rebuild domains has completed. If
this is performed out of order, the rebuild domains will fail and
the perf domains will be freed, causing
walt_find_energy_efficient_cpu to fail to perform active migration.
After topology update is complete and walt initialization moves
forward, rebuild the domains waiting for the completion of the
rebuild before performing the walt update of the toplogy,
guranteeing that the perf domains are populated properly even if
cpufreq builds the domains the first time, out of order.
Change-Id: I28499c4318580da54735347be0ea00867e68d94b
Signed-off-by: Stephen Dickey <quic_dickey@quicinc.com>
