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pinctrl: qcom: Allow setting wakeup enable bit

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Wakeup enable bit controls the interrupt routing to parent PDC irqchip.
These gets set during interrupt allocation for the GPIOs which are used
as interrupt or via firmware.

However sometimes clients may want to set it without requesting interrupt
line for it. This was done via msm_gpio_mpm_wake_set() API.

On newer targets the bit position for wakeup enable bit is changed to
interrupt config register. Modify msm_gpio_mpm_wake_set() accordingly.

Change-Id: I7441595b49e35181831b1015a41b054b435e07a9
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
This commit is contained in:
Maulik Shah 2022-10-31 15:26:42 +05:30
parent 67fde14ade
commit f7447781a2
1 changed files with 17 additions and 2 deletions
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19
drivers/pinctrl/qcom/pinctrl-msm.c
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@ -1549,13 +1549,26 @@ int msm_gpio_mpm_wake_set(unsigned int gpio, bool enable)
{
const struct msm_pingroup *g;
unsigned long flags;
u32 val;
u32 val, intr_cfg;
g = &msm_pinctrl_data->soc->groups[gpio];
if (g->wake_bit == -1)
if (g->wake_bit == -1 && !g->intr_wakeup_present_bit)
return -ENOENT;
raw_spin_lock_irqsave(&msm_pinctrl_data->lock, flags);
intr_cfg = msm_readl_intr_cfg(msm_pinctrl_data, g);
if (intr_cfg & BIT(g->intr_wakeup_present_bit)) {
if (enable)
intr_cfg |= BIT(g->intr_wakeup_enable_bit);
else
intr_cfg &= ~BIT(g->intr_wakeup_enable_bit);
msm_writel_intr_cfg(intr_cfg, msm_pinctrl_data, g);
goto exit;
}
val = readl_relaxed(msm_pinctrl_data->regs[g->tile] + g->wake_reg);
if (enable)
val |= BIT(g->wake_bit);
@ -1563,6 +1576,8 @@ int msm_gpio_mpm_wake_set(unsigned int gpio, bool enable)
val &= ~BIT(g->wake_bit);
writel_relaxed(val, msm_pinctrl_data->regs[g->tile] + g->wake_reg);
exit:
raw_spin_unlock_irqrestore(&msm_pinctrl_data->lock, flags);
return 0;