Just one change to get started on SoC yaml binding changes for omaps.
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Merge tag 'omap-for-v6.6/dt-bindings-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/dt
Devicetree binding changes for omaps for v6.6
Just one change to get started on SoC yaml binding changes for omaps.
* tag 'omap-for-v6.6/dt-bindings-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
dt-bindings: omap: Partially convert omap.txt to yaml
Link: https://lore.kernel.org/r/pull-1691658952-110529@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The defined value for "status" is "disabled", not "disable".
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230804225813.12493-1-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Just a single minor whitespace cleanup in couple of FVP device trees.
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Merge tag 'juno-update-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
Armv8 Juno/FVP update for v6.6
Just a single minor whitespace cleanup in couple of FVP device trees.
* tag 'juno-update-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: arm: minor whitespace cleanup around '='
Link: https://lore.kernel.org/r/20230804123223.3258086-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Miscellaneous fixes according the DTS coding style
- Correct the clocks order of the sd0 for the hi3798cv200
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Merge tag 'hisi-arm64-dt-for-6.6' of https://github.com/hisilicon/linux-hisi into soc/dt
ARM64: DT: HiSilicon ARM64 DT updates for v6.6
- Miscellaneous fixes according the DTS coding style
- Correct the clocks order of the sd0 for the hi3798cv200
* tag 'hisi-arm64-dt-for-6.6' of https://github.com/hisilicon/linux-hisi:
arm64: dts: hi3798cv200: Fix clocks order of sd0
arm64: dts: hisilicon: add missing space before {
arm64: dts: hisilicon: minor whitespace cleanup around '='
Link: https://lore.kernel.org/r/64CC99A3.5030701@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Each interrupt should be in its own cell. This is much more readable.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Link: https://lore.kernel.org/r/20230730111536.98164-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add Clocked Serial Interface (CSI) support for the RZ/V2M SoC,
- Add PMIC, RTC, and PWM support for the RZ/G2L, RZ/G2LC, and RZ/V2L
SMARC EVK development boards,
- Add PWM (MTU3a) support for the RZ/G2UL and RZ/Five SoCs,
- Add External interrupt (INTC-EX) support for the R-Car S4-8 SoC,
- Add LED support for the Spider development board,
- Miscellaneous fixes and improvements.
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Merge tag 'renesas-dts-for-v6.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.6
- Add Clocked Serial Interface (CSI) support for the RZ/V2M SoC,
- Add PMIC, RTC, and PWM support for the RZ/G2L, RZ/G2LC, and RZ/V2L
SMARC EVK development boards,
- Add PWM (MTU3a) support for the RZ/G2UL and RZ/Five SoCs,
- Add External interrupt (INTC-EX) support for the R-Car S4-8 SoC,
- Add LED support for the Spider development board,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: spider-cpu: Add GP LEDs
arm64: dts: renesas: r8a779f0: Add INTC-EX node
arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3
arm64: dts: renesas: r9a07g043: Add MTU3a node
ARM dts: renesas: armadillo800eva: Switch to enable-gpios
arm64: dts: renesas: rzg2lc-smarc-som: Enable PMIC and built-in RTC
arm64: dts: renesas: rzg2lc-smarc-som: Add PHY interrupt support for ETH0
riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node
arm64: dts: renesas: rzg2lc-smarc: Add support for enabling MTU3
arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3
arm64: dts: renesas: Add missing space before {
ARM: dts: renesas: Add missing space before {
arm64: dts: renesas: Minor whitespace cleanup around '='
arm64: dts: renesas: rzg2l-smarc-som: Enable PMIC and built-in RTC
arm64: dts: renesas: r9a09g011: Add CSI nodes
arm64: dts: renesas: rzg2l: Fix txdv-skew-psec typos
arm64: dts: renesas: rzg2l: Update overfow/underflow IRQ names for MTU3 channels
Link: https://lore.kernel.org/r/cover.1690545144.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The majority of this is fixes all over the place for DT schema
validation warnings. However, there are also cleanups for some things in
DT and audio support is added on IGX Orin. Jetson Orin NX and Nano also
gain a new thermal trip point to help keep the device cool at moderate
loads.
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Merge tag 'tegra-for-6.6-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
arm64: tegra: Device tree changes for v6.6-rc1
The majority of this is fixes all over the place for DT schema
validation warnings. However, there are also cleanups for some things in
DT and audio support is added on IGX Orin. Jetson Orin NX and Nano also
gain a new thermal trip point to help keep the device cool at moderate
loads.
* tag 'tegra-for-6.6-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (22 commits)
arm64: tegra: Add blank lines for better readability
arm64: tegra: Remove {clock,reset}-names from VIC powergate
arm64: tegra: Drop incorrect maxim,disable-etr on Smaug
arm64: tegra: Add SPI device tree nodes for Tegra234
arm64: tegra: Enable UARTA and UARTE for Orin Nano
arm64: tegra: Add UARTE device tree node on Tegra234
arm64: tegra: Adapt to LP855X bindings changes
arm64: tegra: Add PCIe and DP 3.3V supplies
arm64: tegra: Add missing reset-names for Tegra HS UART
arm64: tegra: Remove current-speed for SBSA UART
arm64: tegra: smaug: Remove reg-shift for high-speed UART
arm64: tegra: Remove dmas and dma-names for debug UART
arm64: tegra: Add 35°C trip point for Jetson Orin NX/Nano
arm64: tegra: Remove duplicate PCI nodes
arm64: tegra: Sort PCI nodes correctly on Orin
arm64: tegra: Add audio support for IGX Orin
arm64: tegra: Update CPU OPP tables
arm64: tegra: Fix HSUART for Smaug
arm64: tegra: Fix HSUART for Jetson AGX Orin
arm64: tegra: Add missing alias for NVIDIA IGX Orin
...
Link: https://lore.kernel.org/r/20230728094129.3587109-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This contains various fixes for DT schema validation and the Pegatron
Chagall and Nexus 7 get specific compatible strings for the panels that
they use.
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Merge tag 'tegra-for-6.6-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
ARM: tegra: Device tree changes for v6.6-rc1
This contains various fixes for DT schema validation and the Pegatron
Chagall and Nexus 7 get specific compatible strings for the panels that
they use.
* tag 'tegra-for-6.6-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Provide specific compatible string for Nexus 7 panel
ARM: tegra: Use Hannstar HSD101PWW2 on Pegatron Chagall
ARM: tegra: Reuse I2C3 for NVEC
ARM: tegra: Add missing reset-names for Tegra HS UART
ARM: tegra: Remove reset-names for UART devices
ARM: tegra: Remove dmas and dma-names for debug UART
Link: https://lore.kernel.org/r/20230728094129.3587109-3-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
A number of Tegra-specific bindings are converted to json-schema and the
reserved-memory and BPMP bindings get support for Tegra264.
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Merge tag 'tegra-for-6.6-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
dt-bindings: Changes for v6.6-rc1
A number of Tegra-specific bindings are converted to json-schema and the
reserved-memory and BPMP bindings get support for Tegra264.
* tag 'tegra-for-6.6-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: firmware: Add support for tegra186-bpmp DRAM MRQ GSCs
dt-bindings: reserved-memory: Add support for DRAM MRQ GSCs
dt-bindings: thermal: tegra: Convert to json-schema
dt-bindings: arm: tegra: nvec: Convert to json-schema
dt-bindings: clock: tegra: Document Tegra132 compatible
dt-bindings: cpu: Document NVIDIA Tegra186 CCPLEX cluster
dt-bindings: serial: tegra-hsuart: Convert to json-schema
dt-bindings: arm: tegra: ahb: Convert to json-schema
dt-bindings: arm: tegra: flowctrl: Convert to json-schema
Link: https://lore.kernel.org/r/20230728094129.3587109-2-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add the '-@' DTC option for the sun8i-h3 pi-class devices. This option
populates the '__symbols__' node that contains all the necessary symbols
for supporting device-tree overlays (for instance from the firmware or
the bootloader) on these devices.
These devices allow various modules to be connected and this enables
users to create out-of-tree device-tree overlays for these modules.
Please note that this change does increase the size of the resulting DTB
by ~30%. For example, with v6.4 increase in size is as follows:
22909 -> 29564 sun8i-h3-orangepi-lite.dtb
24214 -> 30935 sun8i-h3-bananapi-m2-plus.dtb
23915 -> 30664 sun8i-h3-nanopi-m1-plus.dtb
22969 -> 29537 sun8i-h3-nanopi-m1.dtb
24157 -> 30836 sun8i-h3-nanopi-duo2.dtb
24110 -> 30845 sun8i-h3-orangepi-plus2e.dtb
23472 -> 30037 sun8i-h3-orangepi-one.dtb
24600 -> 31410 sun8i-h3-orangepi-plus.dtb
23618 -> 30230 sun8i-h3-orangepi-2.dtb
22170 -> 28548 sun8i-h3-orangepi-zero-plus2.dtb
23258 -> 29795 sun8i-h3-nanopi-neo-air.dtb
23113 -> 29699 sun8i-h3-zeropi.dtb
22803 -> 29270 sun8i-h3-nanopi-neo.dtb
24674 -> 31318 sun8i-h3-nanopi-r1.dtb
23477 -> 30038 sun8i-h3-orangepi-pc.dtb
24622 -> 31380 sun8i-h3-bananapi-m2-plus-v1.2.dtb
23750 -> 30366 sun8i-h3-orangepi-pc-plus.dtb
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230627133703.355893-1-felix.moessbauer@siemens.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The OrangePi Zero 3 is a development board based on the Allwinner H618 SoC,
which seems to be just an H616 with more L2 cache. The board itself is a
slightly updated version of the Orange Pi Zero 2. It features:
- Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
- 1/1.5/2/4 GiB LPDDR4 DRAM SKUs (only up to 1GB on the Zero2)
- AXP313a PMIC (more capable AXP305 on the Zero2)
- Raspberry-Pi-1 compatible GPIO header
- extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports
- 1 USB 2.0 host port
- 1 USB 2.0 type C port (power supply + OTG)
- MicroSD slot
- on-board 16MiB bootable SPI NOR flash (only 2MB on the Zero2)
- 1Gbps Ethernet port (via Motorcomm YT8531 PHY) (RTL8211 on the Zero2)
- micro-HDMI port
- (yet) unsupported Allwinner WiFi/BT chip
Add the devicetree file describing the currently supported features,
namely LEDs, SD card, PMIC, SPI flash, USB. Ethernet seems unstable at
the moment, though the basic functionality works.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230804170856.1237202-4-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The Orange Pi Zero 3 board is an updated version of the Zero 2 board.
It uses a SoC called H618, which just seems to be an H616 with more L2
cache.
Add the board/SoC compatible string pair to the list of known boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230804170856.1237202-3-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The Orange Pi Zero 2 got a successor (Zero 3), which shares quite some
DT nodes with the Zero 2, but comes with a different PMIC.
Move the common parts (except the PMIC) into a new shared file, and
include that from the existing board .dts file.
No functional change, the generated DTB is the same, except for some
phandle numbering differences.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230804170856.1237202-2-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Remove duplicated DTC_FLAGS_<board> := -@ entries which intends to enable
the building of device tree overlays.
Commit 724ba67515 ("ARM: dts: Move .dts files to vendor sub-directories")
added those entries at the beginning of file w/o removing the already
available entries spread though file.
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20230721053918.33944-1-claudiu.beznea@tuxon.dev
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
The recommended name for enable GPIOs property in regulator-gpio is
enable-gpios. This is also required by bindings:
meson-g12b-bananapi-cm4-cm4io.dtb: regulator-vddio-c: Unevaluated properties are not allowed ('enable-gpio' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230725142703.157547-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Add the board AN400 tree bindings based Amloigc T7 SoC.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230706091954.3301224-2-xianwei.zhao@amlogic.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Use space after '=' sign to match DTS coding style.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230702185327.44625-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Add bindings for the Khadas Vim4 board, using A311D2 Soc from Amlogic T7
family chip.
Signed-off-by: Lucas Tanure <tanure@linux.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230629073419.207886-2-tanure@linux.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Convert omap.txt to yaml.
CC: linux-omap@vger.kernel.org
Signed-off-by: Andrew Davis <afd@ti.com>
[reduced to only OMAP3/4/5 and AM3, adding Epson Moverio BT-200]
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Message-ID: <20230515074512.66226-2-andreas@kemnade.info>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Without this change the KSZ9477 Evaluation board's Linux (v6.5-rc1) shows
following device warning:
'ksz-switch spi1.0: Port 5 interpreting RGMII delay settings based on "phy-mode" property, please update device tree to specify "rx-internal-delay-ps" and "tx-internal-delay-ps"'
This is not critical, as KSZ driver by itself assigns default value of
tx delay to 2000 ps (as 'rgmii-txid' is set as PHY mode).
However, to avoid extra warnings in logs - the missing 'tx-internal-delay-ps'
has been specified with the default value of 2000 ps.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Link: https://lore.kernel.org/r/20230727080656.3828397-1-lukma@denx.de
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Without this change the KSZ9477-EVB board hangs just after passing
execution flow from u-boot to Linux kernel.
This code has been copied from at91-sama5d3_xplained.dts.
Test setup: Linux 6.5-rc1
Config: arch/arm/configs/sama5_defconfig
Toolchain: gcc-linaro-7.3.1-2018.05-x86_64_arm-linux-gnueabi
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Link: https://lore.kernel.org/r/20230712152111.3756211-1-lukma@denx.de
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
The defined value for "status" is "disabled", not "disable".
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20230626221010.3946263-1-robh@kernel.org
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
This patch adds declaration of the general purpose ADC for D1
and T113s SoCs.
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230619154252.3951913-5-bigunclemax@gmail.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The DTS code coding style expects exactly one space before and after '='
sign.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230702185108.43959-1-krzysztof.kozlowski@linaro.org
[claudiu.beznea: added link]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
The DTS code coding style expects exactly one space before and after '='
sign.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230702185108.43959-1-krzysztof.kozlowski@linaro.org
[claudiu.beznea: added link]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
panel-lvds alone is not a valid compatible string and we always need a
specific compatible string as well. Nexus 7 can come with one of (at
least) two panels, so pick one of them as the specific compatible
string.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The LVDS bindings require a specific compatible string in addition to
the generic "panel-lvds". Add the HannStar HSD101PWW2 which is used on
a similar device (ASUS TF201) and seems to work fine with slightly
modified timings in DT.
Suggested-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Instead of duplicating the I2C3 node and adding NVEC specific
properties, reuse the I2C3 node, extend it with NVEC specific properties
and drop properties that are not needed by NVEC. This results in a DTB
that is a bit cleaner and avoids accidentally using I2C3 and NVEC which
would have them fight over the same hardware resources.
Signed-off-by: Thierry Reding <treding@nvidia.com>
According to the device tree bindings, the powergate definition nodes
don't contain clock-names and reset-names properties, so remove them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
There is no "maxim,disable-etr" property (but there is
maxim,enable-etr), neither in the bindings nor in the Linux driver:
tegra210-smaug.dtb: regulator@1c: Unevaluated properties are not allowed ('maxim,disable-etr' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Create the device tree nodes for the SPI1, SPI2 and SPI3 controllers
found on Tegra234.
Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Activate UARTA and UARTE functionalities for Orin Nano.
- UARTA is accessible via the 40-pin header with pin 8 and 10 (TX/RX)
- UARTE utilizes the M2.E connector
Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
