mirror of
https://github.com/torvalds/linux.git
synced 2026-09-19 00:58:02 +02:00
185a4caeec
1037 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Linus Torvalds
|
09fb6892f3 |
Devicetree updates for v7.2:
DT core:
- Add support for handling multiple cells in "iommu-map" entries.
- Support only 1 entry in /reserved-memory "reg" entries. Support for
more than 1 entry has been broken.
- Fix a UAF on alloc_reserved_mem_array() failure
- Make "ibm,phandle" handling logic specific to PPC
- Use memcpy() instead of strcpy() for known length strings
- Ensure __of_find_n_match_cpu_property() handles malformed "reg"
entries
- Add various checks that expected strings are strings before accessing
them
- Drop redundant memset() when unflattening DT
DT bindings:
- Add a DTS style checker. Currently hooked up to dt_binding_check to
check examples.
- Convert st,nomadik platform, ti,omap-dmm, and ti,irq-crossbar
bindings to DT schema
- Add Apple System Management Controller hwmon, Qualcomm Hamoa Embedded
Controller, Qualcomm IPQ6018 PWM controller, fsl,mc1323, Samsung
SOFEF01-M DDIC panel, Freescale i.MX53 Television Encoder, Samsung S2M
series PMIC extcon, and MT6365 PMIC AuxADC schemas
- Extend bindings for QCom Maili and Nord PDC, QCom Hali fastrpc,
qcom,eliza-imem, qcom,oryon-1-5 CPU, and MT6365 Keys
- Consolidate "sram" property definitions
- Fix constraints on "nvmem" properties which only contain phandles and
no arg cells
- Another pass of fixing "phandle-array" constraints
- Add Gira vendor prefix
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAmoxvkAACgkQ+vtdtY28
YcMvzhAArPeBiRXPbA10csf2S9wtNuW5SX3rtPS4v87YMNstWpEW20ZGqwpFmns5
jzAvCjqlhMxpxH43eBM3GqaieU41GxCNGsveIyOnJeIK274hLk4p3kyJ2q6xOQYr
t2eC1NOiKFnIOM0ASXmIi5orzVnxHPLvcD9bdvcOWI/LMMK3loiY/CK5Cnps/ZaM
EbCWjxTD3JM+C9P2voaa2vEnpCW0w7Xc3ZXj8S1yxSyuILPcdKJikzP3l/LuEIrL
iy36q/9+JULMS8ooCN6VO0mZPYmB3DAraepHyJxO/hIJLVkO7O1SMIIcmukaRAbC
wf6RtdP498WagPxOOmocmh0k1pkAX4KFfqt9N13vKeUmLElWoaSbpp4v/YODlAr3
w6rSS3Z9Goh6m4ZwnyakENLJjqJdOcJcU9pJHA3EJmTSemChcpQ5GKMf5Sm2fI7O
nEtsuts+WfD+V2FR9qpHYEO6hNllsneJEk4RpSsHbfZorrQTLkDrJesahWsqKl76
wMM8ZWrZIs7vPouOim8LzFANL7myRH1wiJHHZIBCKC77sVNE78d0Bs5+Z118zEq1
eMGybSkbPfLiIYmDWnfnmrRL2+38R45mCzMGdCjhjBMtf0cF88e/TDgXwXiVhpIE
CcHr0COf0mOM+HZHUt23QPEhJZV93pxiXn4913LZfqh+FIAINyk=
=0d13
-----END PGP SIGNATURE-----
Merge tag 'devicetree-for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DT core:
- Add support for handling multiple cells in "iommu-map" entries
- Support only 1 entry in /reserved-memory "reg" entries. Support for
more than 1 entry has been broken
- Fix a UAF on alloc_reserved_mem_array() failure
- Make "ibm,phandle" handling logic specific to PPC
- Use memcpy() instead of strcpy() for known length strings
- Ensure __of_find_n_match_cpu_property() handles malformed "reg"
entries
- Add various checks that expected strings are strings before
accessing them
- Drop redundant memset() when unflattening DT
DT bindings:
- Add a DTS style checker. Currently hooked up to dt_binding_check to
check examples
- Convert st,nomadik platform, ti,omap-dmm, and ti,irq-crossbar
bindings to DT schema
- Add Apple System Management Controller hwmon, Qualcomm Hamoa
Embedded Controller, Qualcomm IPQ6018 PWM controller, fsl,mc1323,
Samsung SOFEF01-M DDIC panel, Freescale i.MX53 Television Encoder,
Samsung S2M series PMIC extcon, and MT6365 PMIC AuxADC schemas
- Extend bindings for QCom Maili and Nord PDC, QCom Hali fastrpc,
qcom,eliza-imem, qcom,oryon-1-5 CPU, and MT6365 Keys
- Consolidate "sram" property definitions
- Fix constraints on "nvmem" properties which only contain phandles
and no arg cells
- Another pass of fixing "phandle-array" constraints
- Add Gira vendor prefix"
* tag 'devicetree-for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (50 commits)
dt-bindings: interrupt-controller: qcom,pdc: Add Maili compatible string
dt-bindings: interrupt-controller: ti,irq-crossbar: Convert to DT schema
dt-bindings: vendor-prefixes: add Gira
dt-bindings: embedded-controller: Add Qualcomm reference device EC description
dt-bindings: pwm: add IPQ6018 binding
dt-bindings: hwmon: Add Apple System Management Controller hwmon schema
docs: dt: writing-schema: Clarify what is required in a schema
of: Respect #{iommu,msi}-cells in maps
of: Factor arguments passed to of_map_id() into a struct
of: Add convenience wrappers for of_map_id()
of: reserved_mem: zero total_reserved_mem_cnt if no valid /reserved-memory entry
of: reserved_mem: handle NULL name in of_reserved_mem_lookup()
dt-bindings: cache: l2c2x0: Add missing power-domains
dt-bindings: interrupt-controller: renesas,r9a09g077-icu: Fix reg size in example
dt-bindings: nvmem: consumer: Make 'nvmem' an array of one-item entries
drivers/of/overlay: Use memcpy() to copy known length strings
dt-bindings: add self-test fixtures for style checker
dt-bindings: wire style checker into dt_binding_check
scripts/jobserver-exec: propagate child exit status
dt-bindings: add DTS style checker
...
|
||
|
Linus Torvalds
|
70cb95c736 |
soc: drivers for 7.2
There are a few added drivers, but mostly the normal maintenance to drivers
for firmware, memory controller and other soc specific hadware:
- The NXP QuickEngine gets modern MSI support, which allows some cleanups to
the GICv3 irqchip chip driver
- A new SoC specific driver for the Renesas R-Car MFIS unit is added,
encapsulating support for the on-chip mailbox and hwspinlock
implementations that are not easily separated into individual
drivers
- The Qualcomm SoC drivers add support for additional SoC implementations,
and flexiblity around power managedment for the serial-engine driver
as well as probing the LLCC driver using custom hardware descriptions
inside of the device itself.
- Added support for the Samsung thermal management unit
- A cleanup to the Tegra 'PMC' driver interfaces to remove legacy
APIs and allow multiple PMC instances everywhere.
- Updates to the TI SCI and KNAS drivers to improve suspend/resume
support.
- Minor driver changes for mediatek, xilinx, allwinner, aspeed, tegra,
broadcom, amd, microchip and starfive specific drivers
- Memory controller updates for Tegra and Renesas for additional SoC
types and other improvements.
- Firmware driver updates for Arm FF-A, SMCCC and SCMI interfaces,
to update driver probing, object lifetimes and address minor bugs.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmow8HMACgkQmmx57+YA
GNmV4A//WYorQo+qes020w70BAc67/CCVsYpDLDz0mWD5G/uQoQkmyqJTA/b2VnM
iBzrxJ5lGRP7xkhfDVCfb3wsMNsJV9X4QRLGB13XkXA/vRMZxBd3xKV0K/CWUJYo
0YJV/BeFDonhbIjTyeZ0ddUvkdOtqn7tua+YiVpRLL4lqV0JzwzQ1mrqKuJ1EFk0
LWw/oLf+xhcY9X6lae0kranLcR6wauGVu9FLXu2nMtGnn1ErkUfywmd8C1mZ8yLk
QCEjSNdvjXQKSAFhNhAcNPxEDFqvNqKQEXfa62i3m8rM8mX1/ZJUd49NCEQaOnXm
ZbeZVHLATf8ut6WKvAwOdtcmvY2HAvBy9xyU7mdiYw3+3hDHQWU068bqYcEbfY6O
04vhYjnvYnYCZNifH3MvsdMteILN5Eja+dNq7Li2LbnMqbSUHr4gJm0nQcbvsbs0
x42GsuqtmPy1PL4/9hlwN/eDj+Bce4O2x1ZXl8VoChGRUD1JJXzr4NGDumBv03hA
eqja4VdMWb9Z/w7y6nlXkx48DibpBJJCgotbYl6DSfJjfGX+jnYrHHcZg5BCIvUc
X1Fy6236sWBQsj1crNcm2QZ2JWJE28HRYcDq3JGDDGvWkcrkB4c1H0N/rIkO4H5F
nTW5LgJDTd/KEzq3WOKN+gcHoLjXWl0wKJpb4WQ7sdvcYUTdHx8=
=27+M
-----END PGP SIGNATURE-----
Merge tag 'soc-drivers-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"There are a few added drivers, but mostly the normal maintenance to
drivers for firmware, memory controller and other soc specific
hardware:
- The NXP QuickEngine gets modern MSI support, which allows some
cleanups to the GICv3 irqchip chip driver
- A new SoC specific driver for the Renesas R-Car MFIS unit is added,
encapsulating support for the on-chip mailbox and hwspinlock
implementations that are not easily separated into individual
drivers
- The Qualcomm SoC drivers add support for additional SoC
implementations, and flexibility around power management for the
serial-engine driver as well as probing the LLCC driver using
custom hardware descriptions inside of the device itself.
- Added support for the Samsung thermal management unit
- A cleanup to the Tegra 'PMC' driver interfaces to remove legacy
APIs and allow multiple PMC instances everywhere.
- Updates to the TI SCI and KNAS drivers to improve suspend/resume
support.
- Minor driver changes for mediatek, xilinx, allwinner, aspeed,
tegra, broadcom, amd, microchip and starfive specific drivers
- Memory controller updates for Tegra and Renesas for additional SoC
types and other improvements.
- Firmware driver updates for Arm FF-A, SMCCC and SCMI interfaces, to
update driver probing, object lifetimes and address minor bugs"
* tag 'soc-drivers-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (189 commits)
Revert "firmware: zynqmp: Add dynamic CSU register discovery and sysfs interface"
Revert "Documentation: ABI: add sysfs interface for ZynqMP CSU registers"
memory: tegra234: drop dead NULL check in tegra234_mc_icc_aggregate()
memory: tegra264: drop redundant tegra264_mc_icc_aggregate()
memory: tegra186-emc: stop borrowing MC aggregate hook for EMC
soc: aspeed: cleanup dead default for ASPEED_SOCINFO
firmware: tegra: bpmp: Add support for multi-socket platforms
firmware: tegra: bpmp: Propagate debugfs errors
soc/tegra: pmc: Add Tegra238 support
soc/tegra: pmc: Restrict power-off handler to Nexus 7
soc/tegra: pmc: Populate powergate debugfs only when needed
soc/tegra: pmc: Move legacy code behind CONFIG_ARM guard
soc/tegra: pmc: Remove unused legacy functions
soc/tegra: pmc: Create PMC context dynamically
firmware: samsung: acpm: remove compile-testing stubs
firmware: samsung: acpm: Add devm_acpm_get_by_phandle helper
firmware: samsung: acpm: Add TMU protocol support
firmware: samsung: acpm: Make acpm_ops const and access via pointer
firmware: samsung: acpm: Drop redundant _ops suffix in acpm_ops members
firmware: samsung: acpm: Annotate rx_data->cmd with __counted_by_ptr
...
|
||
|
Arnd Bergmann
|
3659b13199 |
Microchip RISC-V soc drivers for v7.2
A single dt-binding compatible addition for the irqmux on pic64gx. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCaiakQAAKCRB4tDGHoIJi 0spXAQDsU+p0Dr7OhDDn5pP8I4/q2ucr+lqpAUY6i9hq14VuoQD/RqhGh16LFFou EssSKsXGD2uxxrFiv4V7dOp7Rg+lSAs= =4WhE -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIyBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmooKucACgkQmmx57+YA GNmWGA/4irxaH4mTli1QFDNPfDsQlY/Fr5AzOUtl7bNQN7F3xQmhZTUKo4gJW0K8 AnDS8iffdvTLPxlASQslSBQhd3FreWMCOD/iBUXaGkgg1dshg0h1rUyb4vvrqucH tjBZvZeFOd27SySJhDe8fsj8uNERIP3kaz00VIi/IR3IzPucJKFoH5kGUEYUu64x geXIA8tiS7s0y6rvWpuLt9n00uw5I0nbRIdTGTkyZPMQrwBwORjiu2JX/yXJPxkS fp/S3oaqOgXJk9hehqiJRf26vvQLWKVPbfWNoX1WZ5odltv9Pl68YNxgK6Q3rv2q AY4zQ2nbXLC8Re8/4ngRic3rFvodMGX7AjP9rxsA9YBKE39Q4Vdq50Gibmf4WBst spJIWX1tBt8UCx5pUIXUnNwhH/0QxqbUQrTMMX5FxWIZ6kdHz0t8ikNFXZxvsmLZ Jat6t87O+OIPwxg0K+muwKjWpBYolUunPZevp0SBjVrs5ULuKFCdHvjUHZol1tb+ d4MjMveHMxjqeKkyX9chtKf7nzujZIwU1kLcV7s288SBsz3gCTVcnyhJq0j68bVb Pphr1JN1JwuJyJCyQnOGI/XBENE9Tg+dRIhNErjLE2nn73VHb13VpNuKATOw4T2M CVzq6kQsyxKZK/Xm9bNtq8QOubjeC7aGbc6+3y8PCIoLDtj1Ow== =ZrlJ -----END PGP SIGNATURE----- Merge tag 'riscv-soc-drivers-for-v7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers Microchip RISC-V soc drivers for v7.2 A single dt-binding compatible addition for the irqmux on pic64gx. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-soc-drivers-for-v7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: dt-bindings: soc: microchip: document irqmux on pic64gx Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Krzysztof Kozlowski
|
9cf333de20 |
RISC-V Devicetrees for v7.2
Sophgo: For CV18xx serials: - Add bindings for Milk-V "Duo S" board. For SG2042: - The CPU unit address incorrectly used decimal numbers, especially for those nodes which value >= 10. Now corrected to use hexadecimal. - The MSI controller actually only supports 16 interrupts; corrected to match the actual situation. - PCIe RCs are cache-coherent with the CPU. Marked it out for RC nodes. For SG2044: - The same as SG2042, use hex for CPU unit address. In additional, update Chen Wang's email address for Sopgho SoC maintainer. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTYPcWJ6By3aFu8IuKHG95Quc97dgUCah/FnAAKCRCHG95Quc97 dhWzAQDU0rJDliEvffHvt4MBpMe5MuK5vgwxEun3YPCjCTzkpQEA6HT6IgHjlibB SLUn4X8cbJpupgI3czvkxogPNWeZYgE= =kAeE -----END PGP SIGNATURE----- Merge tag 'riscv-sophgo-dt-for-v7.2' of https://github.com/sophgo/linux into soc/dt RISC-V Devicetrees for v7.2 Sophgo: For CV18xx serials: - Add bindings for Milk-V "Duo S" board. For SG2042: - The CPU unit address incorrectly used decimal numbers, especially for those nodes which value >= 10. Now corrected to use hexadecimal. - The MSI controller actually only supports 16 interrupts; corrected to match the actual situation. - PCIe RCs are cache-coherent with the CPU. Marked it out for RC nodes. For SG2044: - The same as SG2042, use hex for CPU unit address. In additional, update Chen Wang's email address for Sopgho SoC maintainer. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * tag 'riscv-sophgo-dt-for-v7.2' of https://github.com/sophgo/linux: riscv: dts: sophgo: reduce SG2042 MSI count to 16 riscv: dts: sophgo: sg2042: use hex for CPU unit address riscv: dts: sophgo: sg2044: use hex for CPU unit address riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers dt-bindings: soc: sophgo: add sg2000 plic and clint documentation dt-bindings: soc: sophgo: add Milk-V Duo S board compatibles MAINTAINERS: update Chen Wang's email address Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> |
||
|
Krzysztof Kozlowski
|
a451dd4b43 |
Renesas driver updates for v7.2 (take two)
- Identify the R-Car M3Le SoC, - Add Multifunctional Interface (MFIS) support for R-Car V4H and V4M. -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCah1FOwAKCRCKwlD9ZEnx cAwKAQCHcFEsNEOFt1Tx6EnK1sACrdjqMlb0hR/rNuwIGz2sZQD/X2tqhSP4cpYA QPfA/+mo0RcJStl34No1weBgWJOB2QM= =zOyF -----END PGP SIGNATURE----- Merge tag 'renesas-drivers-for-v7.2-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/drivers Renesas driver updates for v7.2 (take two) - Identify the R-Car M3Le SoC, - Add Multifunctional Interface (MFIS) support for R-Car V4H and V4M. * tag 'renesas-drivers-for-v7.2-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: rcar-mfis: Add R-Car V4H/V4M support dt-bindings: soc: renesas: mfis: Add R-Car V4H/V4M support soc: renesas: Identify R-Car R8A779MD M3Le SoC Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> |
||
|
Bhargav Joshi
|
ffda432eb1 |
dt-bindings: soc: ti,omap-dmm: Convert to DT schema
Convert the TI OMAP Dynamic Memory Manager (DMM) dt binding from text format to DT schema. During conversion following changes were made: - Move file from /bindings/arm/omap to /bindings/soc/ti/ - Make the 'ti,hwmods' property optional and mark it deprecated as it is no longer used, it is kept to support legacy dtbs. - Add the missing required property 'interrupts' to example node. Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com> Link: https://patch.msgid.link/20260605-ti-omap-dmm-v2-1-1b460742ec83@gmail.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
||
|
Joshua Milas
|
efe66eed43 |
dt-bindings: soc: sophgo: add Milk-V Duo S board compatibles
Document the compatible strings for the Milk-V Duo S board [1] which uses the SOPHGO SG2000 SoC. Link: https://milkv.io/duo-s [1] Signed-off-by: Joshua Milas <josh.milas@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260530173347.33533-2-josh.milas@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> |
||
|
Geert Uytterhoeven
|
556304bddb |
Renesas R-Car X5H MFIS DT Binding Definitions
DT bindings and binding definitions for the Renesas R-Car X5H (R8A78000) Multifunctional Interface (MFIS), shared by driver and DT source files. -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCafhrNgAKCRCKwlD9ZEnx cEYxAQD75qANLTBGvyEIvcSjM099aebREw0CoFgrbhSZ8S/cMwD9H3DjKC1nEcdt Ai6vhFqT6Ps8BILUCPB84VDHj++zOw0= =iPDZ -----END PGP SIGNATURE----- Merge tag 'renesas-r8a78000-dt-binding-defs-tag1' into renesas-dts-for-v7.2 Renesas R-Car X5H MFIS DT Binding Definitions DT bindings and binding definitions for the Renesas R-Car X5H (R8A78000) Multifunctional Interface (MFIS), shared by driver and DT source files. |
||
|
Marek Vasut
|
2cba284c0c |
dt-bindings: soc: renesas: Document R-Car R8A779MD Geist
Document the compatible value for the Renesas R-Car M3Le (R8A779MD) SoC and the Renesas Geist development board. The Renesas M3Le SoC is a register-compatible variant of the R8A77965 (M3-N) with reduced set of peripherals. The Geist board is derived from Renesas Salvator-X/XS boards, with adjustment for the R8A779MD SoC. Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/20260504144534.43745-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
||
|
Arnd Bergmann
|
b6a6fae6c5 |
Qualcomm driver updates for v7.2
Enable QSEECOM and with that access to UEFI variables on the Surface Pro 12in laptop. Refactor the Geni Serial-Engine helper code to allow the serial engine drivers (such as I2C) to operate on targets where power and performance is controlled through an SCMI server instead of individual resources in Linux. Extend the LLCC driver to support reading its data from a System Cache Table (SCT) in memory instead of being hard coded per platform in the driver. Also add support for the Eliza platform. Add support for the Hawi platform to pd-mapper. Switch the SMEM driver to track partitions using xarray to handle the ever growing number of hosts better. Extend the socinfo driver with knowledge about the Nord, SM7750, IPQ9650, and Shikra SoCs, as well as PMAU0102, PMC1020H, PMIV0102, and PMIV0104 PMICs. Define UBWC 3.1 and add a couple of convenient helpers in the UBWC library for MDSS and Adreno. Fix a memory leak in the WCNSS firmware download mechanism. -----BEGIN PGP SIGNATURE----- iQJCBAABCgAsFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmoVuSUOHGJqb3JuQGty eW8uc2UACgkQCx85Pw2ZrcUJoBAAxf+8fFvYZif2gk1wzA01IINQgB5/2gYu9oSW Ex4YrHF2wV3BlzRjDnoQ9yC9mYyQeAwqy0pHPIEhJrh5pTc7sJLH5P+iXwe0JU2e GD6WtxRlSswIhDcmoJokSWNkyQxGu540Mh140/Bd0Pb0tMelh76wmzcpY31tzDOa APmtPCXWOdMGYAJSA5DMUMlKEENBNuD7yg0sYtoNz4+XVv4nsjMviEspyNN/fWHg UvL7IJPFwiKynsYrohTgFS5spXOR79aR1xPVsujoUVhzV/W0NFXiDgGLZa41QBAJ lfqmxQiNCZ6I3n2R4X1OULXy9vLZalLiXQzMOJhvPbjXjW1R6jy40f5+W9SZnNSH Q33nbkpJWG81gN5GeqwdPi1+gDDIMyw4A3+RaqRPJBYkYzG1NU2YD5ZNFpMrfRta BT0Nzs8wdmMQgHDGXhjuzMC1hrm9b8QOT12GUnm2hcL7DIJsJC2mtLmlrvnQSm8y 3iPDrEhok2GzSXOKs1EkRfennjLG2MM54Bv7WosNJjrQi2FWkwU2OeNavDxkHo4G JTWwOPFoRysHqmqLr9aIvQGV9lQ2W+57CqnjrbVeMNclJNUm0usZX/i3zX9jCG7R SGwdslqlE/PqJWjUN8S/+LECI54axJXlp3KE6+m+nkEsOQcYIxwU/PfZiG1vyJu1 0Y22gro= =mOpO -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmoaDQQACgkQmmx57+YA GNm/KxAAumqFwdnLIK37ui8u3FG1he/Pal9RwXR0dJkLTAYmCK5vd/e/GEjTL0BG W2Zv+Gt1kvm0BZ10b7AaQNKx5jnE7AsglOTHXXW8pVmZW7w1Fz8CP96SiZz2iKb0 Fqpuq8utUg7fxYzYZuPGMWNQVSf0dliZrygp8iTHop/2iaJzL/dOQHBtXSXvuJVW FhCYtaDIBXpLzbFpe8z+QMM5bYmgiIF8zqdmOSe92LYVVWv1WNzflu8+fGDCxv9z EhsLdkM62xCR2a5YE0Tx0/44hw6sGh7ffnfkkIrEJvIBtkjxoERc0TRGXcvTeUnp bX4H1d/kanzvUu+0KrP+fxiCQL1DmiUi8SOEFx0YUSrBSp0HtIdgVyLxM6Q0UYdc JP95xqb/SfvVGRf3FFrP8NlIwM7n8NGpV8PqUnQ0K+NVUnsQWPJPZ+lkyCjX6G3b pXR/eSe4OBu3xjUAB2x7r0YQbEjlB1FeVQEA5lRdlW5QSzty/kLgUm/z+4rLQSq1 Zmw9rL28SnlOsoESF0/EAgNUTFfG+cA1wERwa9BdQbb3CzWxKU6QsAInL6ZEp1xI eTtGI+ia9yUv4pzMOiuv00seQQ2A45Qww6xkgsM2n0wbP1Bza9Rrkc1w9exK36ho JZkQ773gwyEYyRfHoobYyFRYtMve4JOWCjGjL5F3Gtw3YddABXU= =ryJr -----END PGP SIGNATURE----- Merge tag 'qcom-drivers-for-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers Qualcomm driver updates for v7.2 Enable QSEECOM and with that access to UEFI variables on the Surface Pro 12in laptop. Refactor the Geni Serial-Engine helper code to allow the serial engine drivers (such as I2C) to operate on targets where power and performance is controlled through an SCMI server instead of individual resources in Linux. Extend the LLCC driver to support reading its data from a System Cache Table (SCT) in memory instead of being hard coded per platform in the driver. Also add support for the Eliza platform. Add support for the Hawi platform to pd-mapper. Switch the SMEM driver to track partitions using xarray to handle the ever growing number of hosts better. Extend the socinfo driver with knowledge about the Nord, SM7750, IPQ9650, and Shikra SoCs, as well as PMAU0102, PMC1020H, PMIV0102, and PMIV0104 PMICs. Define UBWC 3.1 and add a couple of convenient helpers in the UBWC library for MDSS and Adreno. Fix a memory leak in the WCNSS firmware download mechanism. * tag 'qcom-drivers-for-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (40 commits) soc: qcom: geni-se: Introduce helper APIs for performance control soc: qcom: geni-se: Introduce helper API for attaching power domains soc: qcom: geni-se: Add resources activation/deactivation helpers soc: qcom: geni-se: Handle core clk in geni_se_clks_off() and geni_se_clks_on() soc: qcom: geni-se: Introduce helper API for resource initialization soc: qcom: geni-se: Add geni_icc_set_bw_ab() function soc: qcom: geni-se: Refactor geni_icc_get() and make qup-memory ICC path optional soc: qcom: llcc-qcom: Fix NULL vs IS_ERR() bug in qcom_llcc_get_fw_config() soc: qcom: llcc-qcom: Add support for Eliza dt-bindings: cache: qcom,llcc: Document Eliza LLCC block soc: qcom: ubwc: add helper controlling AMSBC enablement soc: qcom: ubwc: define helper for MDSS and Adreno drivers soc: qcom: ubwc: define UBWC 3.1 soc: qcom: socinfo: Add SoC ID for Nord SA8797P dt-bindings: arm: qcom,ids: Add SoC ID for Nord SA8797P soc: qcom: socinfo: Add SoC ID for SM7750 dt-bindings: arm: qcom,ids: Add SoC ID for SM7750 soc: qcom: socinfo: Add PMIC PMAU0102 soc: qcom: socinfo: Add PMIV0102 & PMIV0104 PMICs firmware: qcom: scm: Allow QSEECOM on Surface Pro 12in ... Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Wolfram Sang
|
2e9b940f07 |
dt-bindings: soc: renesas: mfis: Add R-Car V4H/V4M support
The above SoCs have only 12 mailboxes and do not have an extra register space for mailboxes. Everything is contained in the common register set. In addition to adding these SoCs, the other entries get updated to enforce 2 register spaces and their specific number of interrupts. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260519075620.4128-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
||
|
Conor Dooley
|
17d9064987 |
dt-bindings: soc: microchip: document irqmux on pic64gx
Being practically identical to PolarFire SoC, pic64gx has a irqmux that's entirely compatible with that on mpfs. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
Mukesh Ojha
|
c5f5156ed4 |
dt-bindings: soc: qcom,aoss-qmp: Document the Hawi AOSS side channel
Document the Always-on Subsystem side channel on Qualcomm Hawi SoC. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260427181609.3648384-1-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Fenglin Wu
|
676f67060a |
dt-bindings: soc: qcom: qcom,pmic-glink: Add Hawi compatible string
Hawi is a mobile platform that is compatible with Kaanapali platform with respect to pmic-glink support. Add the Hawi compatible string with Kaanapali as a fallback. Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260419-hawi-pmic-glink-v1-1-a26908c468fc@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Deepti Jaggi
|
35466ef5db |
dt-bindings: qcom: geni-se-qup: Add compatible for SA8797P SoC
Document GENI Serial Engine QUP Wrapper Controller on Nord SA8797P SoC which is compatible with SA8255P one. Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260427005901.230237-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Abel Vesa
|
7754a6b6a1 |
dt-bindings: soc: qcom,aoss-qmp: Document the Eliza Always-On Subsystem side channel
Document the Always-On Subsystem (AOSS) side channel found on the Qualcomm Eliza SoC. It is used for communication with other clients, like remoteprocs. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260504-eliza-bindings-aoss-v2-1-c3628ca79a25@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Abel Vesa
|
a390203b7e |
dt-bindings: soc: qcom: qcom,pmic-glink: Document Eliza compatible
Document the compatible for the PMIC GLINK interface found on the Qualcomm Eliza SoC. It is fully compatible with the one found on SM8550, so use that as fallback. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260504-eliza-bindings-pmic-glink-v2-1-d6b5397b7899@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Wolfram Sang
|
0f63ba15dd |
dt-bindings: soc: renesas: Document MFIS IP core
Document the Renesas Multifunctional Interface (MFIS) as found on the Renesas R-Car X5H (r8a78000) SoC. MFIS includes features like Mailbox/HW Spinlock/Product Register/Error Injection/Error Detection and the likes. Family-compatible values are not introduced here because MFIS is usually very different per SoC. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260402112709.13002-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
||
|
Linus Torvalds
|
d730905bc3 |
Support for Mobileye EyeQ6Lplus
Cleanups and fixes -----BEGIN PGP SIGNATURE----- iQJOBAABCAA4FiEEbt46xwy6kEcDOXoUeZbBVTGwZHAFAmniNBwaHHRzYm9nZW5k QGFscGhhLmZyYW5rZW4uZGUACgkQeZbBVTGwZHB2QA//U53JZYmmOxKxwbYwLvK9 Z8MuVgkvA/v7WktwL2PoMO0AlhQsteM5VtupddHhuhUiIr7gPy6Z7pEE9sDqM3gj p1d6vrg5XiWlh1fURdSqvzufKsm/etpElbvc2JjkcqD0sMGJUwlkP3ncZk/DCus6 zhcvya7jVxyvzbCBgJSM8QHvOoj/g3EV4hsx8Ymru8XSdLVEegodZtvUHVx4Q29U fmHCf1u/v+rJVbe2T3nuqsqzQhmaWkC+WyeVJIDUNecjclPoGNOeg8duICNfOu9q dtkzOua7v6rRsUA9GDbMcR44PWzL4LqGTOffzwF7uvYakOAp6nQWsymAUIfkQbE6 +I8heGaYPEQLjSHgCPI2WdJ4urbPdgsd5W2pC8s6WaHPdRlSMapH16I0DxmmNZlV CzW7o2ore5b8H4Mu5mboMjFzMY+A/0zC5S7twOpX+mvgPz+MTf1g0vD3hCSL+N7c LSW7rSZyd2smcgaHJBDpHceRHNZbVqloeO007DiJtrx+IWTBhvhFt2q/aqGG51xM 2P/lRZrA8vAMaTR1hZKLmxUPZpSekezoWC8GbWNeIg5NUUTOJoTAtQvT5vU40GZA 22o3s1a6rgz5KngV9rMWYERSV2yflvloYVo0ASVqgy1ijzzlsin/fbO976GdGD2I 7vrch6tajmTSBYeG0SuKiFY= =jKsJ -----END PGP SIGNATURE----- Merge tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS updates from Thomas Bogendoerfer: - Support for Mobileye EyeQ6Lplus - Cleanups and fixes * tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits) MIPS/mtd: Handle READY GPIO in generic NAND platform data MIPS/input: Move RB532 button to GPIO descriptors MIPS: validate DT bootargs before appending them MIPS: Alchemy: Remove unused forward declaration MAINTAINERS: Mobileye: Add EyeQ6Lplus files MIPS: config: add eyeq6lplus_defconfig MIPS: Add Mobileye EyeQ6Lplus evaluation board dts MIPS: Add Mobileye EyeQ6Lplus SoC dtsi clk: eyeq: Add Mobileye EyeQ6Lplus OLB clk: eyeq: Adjust PLL accuracy computation clk: eyeq: Skip post-divisor when computing PLL frequency pinctrl: eyeq5: Add Mobileye EyeQ6Lplus OLB pinctrl: eyeq5: Use match data reset: eyeq: Add Mobileye EyeQ6Lplus OLB MIPS: Add Mobileye EyeQ6Lplus support dt-bindings: soc: mobileye: Add EyeQ6Lplus OLB dt-bindings: mips: Add Mobileye EyeQ6Lplus SoC MIPS: dts: loongson64g-package: Switch to Loongson UART driver mips: pci-mt7620: rework initialization procedure mips: pci-mt7620: add more register init values ... |
||
|
Linus Torvalds
|
31b43c079f |
soc: drivers for 7.1
The driver updates again are all over the place with many minor fixes
going into platform specific code. The most notable changes are:
- Support for Microchip pic64gx system controllers
- Work on cleaning up devicetree bindings for SoC drivers, and
converting them into the new format
- Lots of smaller changes for Qualcomm SoC drivers, including support
for a number of newly supported chips
- reset controller API cleanups and a new driver for Cix Sky1
- Reworks of the Tegra PMC and CBB drivers, along with a change
to how individual Tegra SoCs get selected in Kconfig and
BPMP firmware driver updates including a refresh of the ABI
header to match the version used by firmware
- STM32 updates to the firewall bus driver and support for
the debug bus through OP-TEE
- SCMI firmware driver improvements for reliability, in particular
for dealing with broken firmware interrupts
- Memory driver updates for Tegra, and a patch to remove the
unused Baikal T1 driver
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmnhCSYACgkQmmx57+YA
GNl2ow/+Pti7qbBE34WNyIuWOgZEzjo1OeLe/Y4LqkQmHcM9FJV3/rCadA/FkmD9
nH85WiRuUjIjzUiAl24SP2nkEcIU/yv8ECvROX46uAjhTByVHkaCedwl3ECW9RPA
IAYiTJPrQBNCmWZuGO4bZ3go6hHn4q4RSd2V8vrCw/J3b+wBSAPTPzsaWnWg4MiL
QYz7sBTwcNJaJuwJ7ZnHN/VgEOs9OgY6ejGJImiaVzBbsH7rNp7Cbs6t88X5rCXS
mbgMvVlYKbsOWj3kNyv98YFAGgzo59uEL+m+846U32w9o0nIgkmIS60RQ5k73JV4
QlhV1uT7PPtu7y7VbxfJ8KISxaRoex/+AZShmAWCul4YK75hEWT3mWGhM8cqeMUQ
U0ogpbekRjKdn2Bgfl6kHf38smusjJ1fOBr8QIZcdDJpEtxYtRmNpLUNNSc5vO+T
HvA79C8I8ydWGyqr1wRP1gDRBNc1BDYKxJO4ohvjnAPIeC01zArXCOyf0F3VtPzH
XSycnyW7eRUVi+4C3/cF8qzhW2y7Wx03ui5mCDIEcOzyVoGNqTrPNsbCvkNkyrdc
jqvWagZ4Ci8jaRxLAawnqHI/stvsHx9V+NPp6p07BsOxJMsuOqO4sInRhh5P6YvM
5wZCFUK37xPEqYvr+BFS9B/4jgw3Mg2Kj+gjxShwsLS5JtVDfZw=
=UB4F
-----END PGP SIGNATURE-----
Merge tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"The driver updates again are all over the place with many minor fixes
going into platform specific code. The most notable changes are:
- Support for Microchip pic64gx system controllers
- Work on cleaning up devicetree bindings for SoC drivers, and
converting them into the new format
- Lots of smaller changes for Qualcomm SoC drivers, including support
for a number of newly supported chips
- reset controller API cleanups and a new driver for Cix Sky1
- Reworks of the Tegra PMC and CBB drivers, along with a change to
how individual Tegra SoCs get selected in Kconfig and BPMP firmware
driver updates including a refresh of the ABI header to match the
version used by firmware
- STM32 updates to the firewall bus driver and support for the debug
bus through OP-TEE
- SCMI firmware driver improvements for reliability, in particular
for dealing with broken firmware interrupts
- Memory driver updates for Tegra, and a patch to remove the unused
Baikal T1 driver"
* tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (193 commits)
firmware: arm_ffa: Use the correct buffer size during RXTX_MAP
firmware: qcom: scm: Allow QSEECOM on Lenovo IdeaCentre Mini X
clk: spear: fix resource leak in clk_register_vco_pll()
reset: rzv2h-usb2phy: Add support for VBUS mux controller registration
reset: rzv2h-usb2phy: Convert to regmap API
dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/G3E USB2PHY reset
dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property
soc: microchip: add mpfs gpio interrupt mux driver
dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux
gpio: mpfs: Add interrupt support
soc: qcom: ubwc: add helpers to get programmable values
soc: qcom: ubwc: add helper to get min_acc length
firmware: qcom: scm: Register gunyah watchdog device
soc: qcom: socinfo: Add SoC ID for SA8650P
dt-bindings: arm: qcom,ids: Add SoC ID for SA8650P
firmware: qcom: scm: Allow QSEECOM on Mahua CRD
soc: qcom: wcnss: simplify allocation of req
soc: qcom: pd-mapper: Add support for Eliza
soc: qcom: aoss: compare against normalized cooling state
soc: qcom: llcc: fix v1 SB syndrome register offset
...
|
||
|
Benoît Monin
|
4434c3896f |
dt-bindings: soc: mobileye: Add EyeQ6Lplus OLB
The "Other Logic Block" found in the EyeQ6Lplus from Mobileye provides various functions for the controllers present in the SoC. The OLB produces 22 clocks derived from its input, which is connected to the main oscillator of the SoC. It provides reset signals via two reset domains. It also controls 32 pins to be either a GPIO or an alternate function. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Reviewed-by: Linus Walleij <linusw@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> |
||
|
Krzysztof Kozlowski
|
ecaf3a92fb |
RISC-V soc drivers for v7.1
Microchip: Add coverage for the pic64gx in the system controller and syscons. Add a interrupt mux driver (akin to the one that Renesas recently added) that fixes a problem where the platform never properly modelled gpio interrupts. There's a gpio driver change here that Bartosz has acked that adds the interrupt support to the GPIO driver itself. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCadOMGgAKCRB4tDGHoIJi 0gXaAP9j6X7ZAL+EOJqiUjQUVslWZUv+hZrKOCv1InnSHDkC5gEAovr3nk6yHjt0 a+4XnUj8AGPbT4bcFEdzeArmH//QtgA= =+V3B -----END PGP SIGNATURE----- Merge tag 'riscv-soc-drivers-for-v7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers RISC-V soc drivers for v7.1 Microchip: Add coverage for the pic64gx in the system controller and syscons. Add a interrupt mux driver (akin to the one that Renesas recently added) that fixes a problem where the platform never properly modelled gpio interrupts. There's a gpio driver change here that Bartosz has acked that adds the interrupt support to the GPIO driver itself. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-soc-drivers-for-v7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/conor/linux: soc: microchip: add mpfs gpio interrupt mux driver dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux gpio: mpfs: Add interrupt support soc: microchip: mpfs-sys-controller: add support for pic64gx dt-bindings: soc: microchip: mpfs-sys-controller: Add pic64gx compatibility dt-bindings: soc: microchip: add compatible for the mss-top-sysreg on pic64gx Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> |
||
|
Théo Lebrun
|
7d1b6b7092 |
dt-bindings: soc: mobileye: OLB is an Ethernet PHY provider on EyeQ5
OLB on EyeQ5 ("mobileye,eyeq5-olb" compatible) is now declared as a
generic PHY provider. Under the hood, it provides Ethernet RGMII/SGMII
PHY support for both MAC instances.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
|
||
|
Arnd Bergmann
|
a66cc657ef |
Qualcomm driver updates for v7.1
Add ECS LIVA QC710, Glymur CRD, Mahua CRD, Purwa IoT EVK, and Asus Vivobook to the QSEECOM allow-list, to enable UEFI variable access through uefisecapp. Register the Gunyah watchdog device if the SCM driver finds itself running under Gunyah. Clean up some locking using guards. Handle possible cases where AOSS cooling state is given a non-boolean state. Replace LLCC per-slice activation bitmap with reference counting. Also add SDM670 support. Improve probe deferral handling in the OCMEM driver. Add Milos, QCS615, Eliza, Glymur, and Mahua support to the pd-mapper. Add support for SoCCP-based pmic-glink, as found in Glymur and Kaanapali. Add common QMI service ids to the main qmi headerfile, to avoid spreading these constants in various drivers. Add support for version 2 of SMP2P and implement the irqchip state reading support. Add CQ7790, SA8650P, SM7450, SM7450P, and IPQ5210 SoC and the PM7550BA PMIC identifiers to the socinfo driver. Add Eliza and Mahua support to the UBWC driver, introduce helpers for drivers to read out min_acc length and other programmable values, and disable bank swizzling for Glymur. Simplify the logic related to allocation of NV download request in the WCNSS control driver. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmnMQNQACgkQCx85Pw2Z rcWpmA//QDo8m9t4GgAdqJLSyH40Hcw0Uotv4DhzquUe1hYXTQb4NwNoJ+JZVPvO 70BDuJTOQcnQCKeagW1Zq5ycJtA11khRL9ZWwzJB3fq3UTHI+n0EfHDmshAxz37Y h8x71dWKcI3NnEHWBFglRyYbv/eKFxcc2CFP0HrAB3UOxPClqsOVB5iNNM/JA3Jp eppYK6473VAF89q+q7+F3kEhz2p4sgyI9G2Sm/vFqXV3CLY0WV98FjQAHi1nXuNV pCz4oPkccBAcu7FQffMIydbtoIBPZDoI7pueJ4GlgewkkunuiJew/Rq0GEKnyzsN SqzfnBnbfsbQPOtZTBNY6tDgnSMQV2fMtgyBqkmgnSCs6A1AU6XVPFq4wWDpr6t/ +y9QpA/Jfb1txeHp7xY/9bOAl2/vorZDLp9O8CR828z6Ptg/CGO8Gws/X0g4QWvZ 6+UjRHTB5BnJENjzJGoxhrO59gyASUExoM02b6pQmz4ayw9q1PHGMVdSAPCygrDH r9+yMcTO8kfUAYtliJrygDTDlhwxMDfd2z82BOZGpSbAbR8zfFKKJmIaSQGNHCjl u3G9Kb5L7QlAVBGVcRYaArp1MQWD6oP+IU1W9YMra5cySwt/nXtSsQZRdhoP5Qp6 YO8YMdldkf37DNar/+wrN012yaYSWj/k9x/f0phAn106oq1o8+0= =1zur -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmnO3XkACgkQmmx57+YA GNlXDRAAkXYODhxU+T1AyT5OgDBzKgfVBte2vne+NOuirAX6+4U6v+0lCVx+fs4z kTfeveRoXtWlSSF3Vyv+rw1fZvpUOwZ9Y+u405fgveAxtDUkjzJGsnlrfMGIWD4a Q99WFz9L+kTcaf03uNLhrg9UAx0SpkfQQm2riY+ueHVY/0dOTsNzjv71A9sJrmvq oSEH3xquCOgd8diR3evE+2KhD4yQkzMmVeBuujDhWwIJmY8aSpZFIJIXYL5sRo+V l1bd5EwPH2Ku0bXaKh5mLDS/MvdKk7EPKru7ST0+IVfBXBnZf6KefAqljCvVuR66 RRNDN2kcWU+aoih2vuVI+y3w1XGMX9AbFlviaGZWCY1mL2FTFvWfrQ4vLTz2bRlB 8gFPmxMtVZQxu5hBOxAprnYrValRddYamh8cPQcpu9BGIG/ZIqx8cSOXZsQTiARk 9DPRBQsQmaGXXl1YxbcYibQn1TL3ozmqQn0dhZ2Ojkxv0cyD3ymvdv68QKXPf7dm j2LU6BgNiK5IGZ2VUk5mk3hp5Kc+6qpmMqg7l/HIf1zUULCCFWu6l/IobuaX7ynj b5EU0feXMCJ9B17G1lgdFsZ0oI3RhkROjCi2huklNh1fA/xThwTsZsZQ9NmEKQHw TDCcavPXh64fSVtv4qePd9HV+KcHeBeA18m+6njdqByT36qMeC0= =nCjL -----END PGP SIGNATURE----- Merge tag 'qcom-drivers-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers Qualcomm driver updates for v7.1 Add ECS LIVA QC710, Glymur CRD, Mahua CRD, Purwa IoT EVK, and Asus Vivobook to the QSEECOM allow-list, to enable UEFI variable access through uefisecapp. Register the Gunyah watchdog device if the SCM driver finds itself running under Gunyah. Clean up some locking using guards. Handle possible cases where AOSS cooling state is given a non-boolean state. Replace LLCC per-slice activation bitmap with reference counting. Also add SDM670 support. Improve probe deferral handling in the OCMEM driver. Add Milos, QCS615, Eliza, Glymur, and Mahua support to the pd-mapper. Add support for SoCCP-based pmic-glink, as found in Glymur and Kaanapali. Add common QMI service ids to the main qmi headerfile, to avoid spreading these constants in various drivers. Add support for version 2 of SMP2P and implement the irqchip state reading support. Add CQ7790, SA8650P, SM7450, SM7450P, and IPQ5210 SoC and the PM7550BA PMIC identifiers to the socinfo driver. Add Eliza and Mahua support to the UBWC driver, introduce helpers for drivers to read out min_acc length and other programmable values, and disable bank swizzling for Glymur. Simplify the logic related to allocation of NV download request in the WCNSS control driver. * tag 'qcom-drivers-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (51 commits) soc: qcom: ubwc: add helpers to get programmable values soc: qcom: ubwc: add helper to get min_acc length firmware: qcom: scm: Register gunyah watchdog device soc: qcom: socinfo: Add SoC ID for SA8650P dt-bindings: arm: qcom,ids: Add SoC ID for SA8650P firmware: qcom: scm: Allow QSEECOM on Mahua CRD soc: qcom: wcnss: simplify allocation of req soc: qcom: pd-mapper: Add support for Eliza soc: qcom: aoss: compare against normalized cooling state soc: qcom: llcc: fix v1 SB syndrome register offset dt-bindings: firmware: qcom,scm: Document ipq9650 SCM soc: qcom: ubwc: Add support for Mahua soc: qcom: pd-mapper: Add support for Glymur and Mahua soc: qcom: ubwc: Add configuration Eliza SoC soc: qcom: ubwc: Remove redundant x1e80100_data dt-bindings: firmware: qcom,scm: document Eliza SCM Firmware Interface soc: qcom: ocmem: return -EPROBE_DEFER is ocmem is not available soc: qcom: ocmem: register reasons for probe deferrals soc: qcom: ocmem: make the core clock optional soc: qcom: ubwc: disable bank swizzling for Glymur platform ... Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Arnd Bergmann
|
fbf57f25f0 |
Reset controller updates for v7.1
* Rework the reset core to support firmware nodes, add more fine grained locking, and use guard() helpers. * Change the reset-gpio driver to use firmware nodes. * Add support for the Cix Sky1 SoC reset controller. * Add support for the RZ/G3E SoC to the reset-rzv2h-usb2phy driver and convert it to regmap. Prepare registering a VBUS mux controller. * Replace use of the deprecated register_restart_handler() function in the ath79, intel-gw, lpc18xx, ma35d1, npcm, and sunplus reset drivers. * Combine two allocations into one in the sti/reset-syscfg driver. * Fix the reset-rzg2l-usbphy-ctrl MODULE_AUTHOR email. * Fix the reset_control_rearm() kerneldoc comment. The last commit is a merge of reset-fixes-for-v7.0-2 into reset/next, to solve a merge conflict between commits |
||
|
Arnd Bergmann
|
62513d2213 |
i.MX dt-bindings update for 7.1:
- New board support: Verdin iMX95, MBa93xxLA-MINI, TQMa95xxLA, S32N79 SoC/RDB, i.MX8MP audio board (version 2), SolidRun i.MX8M, TQMa8x, GOcontroll Moduline IV/Mini, FRDM-IMX91S, Variscite DART-MX91, i.MX93 Wireless EVK, Variscite DART-MX95. - fsl,irqsteer add nxp,s32n79-irqsteer support. - fsl,imx93-media-blk-ctrl add dbi-bridge. -----BEGIN PGP SIGNATURE----- iQHFBAABCgAvFiEEJS45w2QNr0ezLVaoNF3oRQ23YkwFAmnFXEURHGZyYW5rLmxp QG54cC5jb20ACgkQNF3oRQ23Ykwingv/b0JC877LuSiwreC39fP67SBWGPvaos1b q70gQ+nx9EY34ITpMmuwBVCCFUYtqgDQdpwLHzw6WOF5YcGfr7h7gjQZ4+Rt+5J3 KLP6SBlQubNSArzBC2umXUlvxoyqkOqLEwA0LukxIjkPU1D6hdYg3rHm0P3jSNpY GG8omjXXL8VBQZXR/faVSy9RIaNSI0iTvoTavFmmyXgF5aFEOquIaPBdO8Io8JGU x9EHrG3vecR3XSit9c6y6sb2T7bFfp8m1x2+y9Jwmmzl/05gwRBnifVe1KAIRnrb XKBbt8TrvZJa0K/t6/r0JIj/H4wWNw0J0CejwaUbiW4BszVgfhXi8n+T7Ld53xf9 BktA2oCFHqqpsJ+A4RZ/BmnD6bb+nd/1SZxDVnO+eXM1/XC+cDtXQsZ9RopwVmRU bf/6X7bnbITinT6MlO5QHoAgqqh6cS+roRw63mV5g1AcKTMZkj54qheNFxOCRb29 LugZSq6NInLuOn2ftx45SZjP+OPhC/ur =tZ7p -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmnO3CcACgkQmmx57+YA GNkIkBAAkYWfBOZ5wlSWOPxY0Bx79JCBVB9dC45C+Lcw2Sl8oHHH89wRSSR0BQr+ 83X4W+mNum5RWHQgDEyWkvllFZHZ0RFgstk31P7wCaYsSEq7VIHpb76NEGQDfGOB XSvIK7QgQoS38rE9JPXnJZNPjnYmn624Eev99Ykpx1o0uPBppMBDws36OX3m/WaI ObOuS7IQTIZ0wE+1dx3pwHZLt7qiYzX3rpoLZBI2wXc1Sr+RIGcbTXx6gFErk42U 9ID6ovSDrxTOxAVZtFBCuHWKklB5H9fVPbcCJvCOdDEw4q4itxc4EJXWMvvRqsK7 Sddc+zoL+g/zzgCICgWZLuK54wWDR8r39a3gGXNZgh/3FH7SkbA7+ujGImz2GGQM todKDj19HcRdcRDGYq3O6KjgbZ1vL4FvUgMv/Z3yakoMQ4BMI2X3ZsJFVm4YtEHz M3P2VKQiwSR+x0ZLml4PXQepwEkbWErUEzspeSOM98e8a23SkHdt91wbWWaii/RL cMS0BlQAauisEWpNhFNIwuTsQJPc9EnGqfQQMW3MJOImjjGjALWwvWsVDHEJRyja AqJBKYnHhFzGzAAj6xY667UfL9bjICdqg1GUBSqkt47RJZiwZ9a5kYKT4fWqQYuk MfJgEBpQH6NqjnRzwVgcmT5clEx1LYJJRn1aly28EfJb3RccYCw= =xuzA -----END PGP SIGNATURE----- Merge tag 'imx-bindings-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux into soc/drivers i.MX dt-bindings update for 7.1: - New board support: Verdin iMX95, MBa93xxLA-MINI, TQMa95xxLA, S32N79 SoC/RDB, i.MX8MP audio board (version 2), SolidRun i.MX8M, TQMa8x, GOcontroll Moduline IV/Mini, FRDM-IMX91S, Variscite DART-MX91, i.MX93 Wireless EVK, Variscite DART-MX95. - fsl,irqsteer add nxp,s32n79-irqsteer support. - fsl,imx93-media-blk-ctrl add dbi-bridge. * tag 'imx-bindings-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux: dt-bindings: arm: fsl: add Verdin iMX95 dt-bindings: arm: fsl: add MBa93xxLA-MINI dt-bindings: arm: add bindings for TQMa95xxLA dt-bindings: arm: lpc: add missed lpc43xx board dt-bindings: arm: fsl: Add NXP S32N79 SoC and RDB board dt-bindings: interrupt-controller: fsl,irqsteer: add S32N79 support dt-bindings: arm: fsl: Add compatible for i.MX8MP audio board (version 2) dt-bindings: arm: fsl: Add various solidrun i.MX8M boards dt-bindings: arm: fsl: add bindings for TQMa8x dt-bindings: fsl: imx7ulp-smc1: Add #clock-cells property dt-bindings: arm: fsl: Add GOcontroll Moduline IV/Mini dt-bindings: arm: fsl: Add FRDM-IMX91S board dt-bindings: arm: fsl: add Variscite DART-MX91 Boards dt-bindings: arm: fsl: Add i.MX93 Wireless EVK board dt-bindings: arm: fsl: add Variscite DART-MX95 Boards dt-bindings: soc: imx93-media-blk-ctrl: Add PDFC subnode to schema and example Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Conor Dooley
|
5f3575cc73 |
dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux
On PolarFire SoC there are more GPIO interrupts than there are interrupt lines available on the PLIC, and a runtime configurable mux is used to decide which interrupts are assigned direct connections to the PLIC & which are relegated to sharing a line. Reviewed-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
Fabio Estevam
|
25c2721f18 |
dt-bindings: soc: rockchip: grf: Add RV1103B compatibles
Add the PMU GRF and IOC compatible strings for the RV1103B SoC. Signed-off-by: Fabio Estevam <festevam@nabladev.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260313131058.708361-1-festevam@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> |
||
|
Gary Yang
|
c76350e7ad |
dt-bindings: soc: cix: document the syscon on Sky1 SoC
There are two system control on Cix sky1 Soc. One is located in S0 domain, and the other is located in S5 domain. The system control contains resets, usb typeC and more. At this point, only the reset controller is embedded as usb typeC uses it by phandle. Signed-off-by: Gary Yang <gary.yang@cixtech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Biju Das
|
3ac4e6b92f |
dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/G3L SoC
Document RZ/G3L (R9A08G046) SYSC bindings. The SYSC block found on the RZ/G3L SoC is similar to the one found on RZ/G3S. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260203103031.247435-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
||
|
Biju Das
|
56c828dff9 |
dt-bindings: soc: renesas: Document RZ/G3L SoC variants, SMARC SoM and Carrier-II EVK
Document Renesas RZ/G3L (R9A08G046) SoC variants and the Renesas RZ/G3L SMARC Carrier-II EVK board which is based on the Renesas RZ/G3L SMARC SoM. The RZ/G3L SMARC Carrier-II EVK consists of an RZ/G3L SoM module and a SMARC Carrier-II carrier board. The SoM module sits on top of the carrier board. Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260203103031.247435-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
||
|
Pierre-Henry Moussay
|
ecc09da7ba |
dt-bindings: soc: microchip: mpfs-sys-controller: Add pic64gx compatibility
pic64gx is not compatible with mpfs because due to the lack of FPGA functionality some features are disabled. Notably, anything to do with FPGA fabric contents is not supported. Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
Conor Dooley
|
7a58baed88 |
dt-bindings: soc: microchip: add compatible for the mss-top-sysreg on pic64gx
pic64gx has an identical sysreg syscon to mpfs, add it using a fallback. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
Liu Ying
|
3feaa43426 |
dt-bindings: soc: imx93-media-blk-ctrl: Add PDFC subnode to schema and example
i.MX93 SoC mediamix blk-ctrl contains one DISPLAY_MUX register which configures parallel display format by using the "PARALLEL_DISP_FORMAT" field. Document the Parallel Display Format Configuration(PDFC) subnode and add the subnode to example. [m.felsch@pengutronix.de: add bus-width] Signed-off-by: Liu Ying <victor.liu@nxp.com> [m.felsch@pengutronix.de: port to v6.18-rc1] Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> |
||
|
Anjelique Melendez
|
aed7440146 |
dt-bindings: soc: qcom: qcom,pmic-glink: Add Glymur and Kaanapali compatibles
Glymur (a recent compute platform) and Kaanapali (a recent mobile platform) have the charger FW running on a new subsystem SOCCP (SOC Control Processor) instead of on ADSP like in previous platforms. Because of this, pmic_glink interface on Glymur and Kaanapali platforms are not compatible with previous platforms. Hence, add new compatible strings for Glymur and Kaanapali. Signed-off-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260209204915.1983997-2-anjelique.melendez@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Linus Torvalds
|
46a1daac56 |
Pin control changes for the v7.0 kernel cycle:
Core changes:
- Drop the unused devm_pinctrl_unregister() function.
- Move pretended generic pin control functionality out of the
core and into the Amlogic AM4 driver. We have something better
coming (hopefully).
New hardware support:
- Spacemit K3 (RISC-V) pin control support.
- Atmel AT91 PIO4 (ARM32) SAMA7D65 pin control support.
- Exynos9610 (ARM64) pin control support.
- Qualcomm Mahua TLMM (ARM64) pin control support.
- Microchip Polarfire MSSIO (RISC-V) pin control support.
- Ocelot LAN9645XF (multiplatform) pin control support.
Improvements:
- Using a few more guards for locking.
- Various nonurgent fixes and tweaks.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmmS7tgACgkQQRCzN7AZ
XXMnww/+ON7+DH8YA5+yI3fPdejv+6LK4es22B3r8bPVW4HtnfGxNqC7HZ8v9SWQ
H7BkSiEv0XLNVjKIV00WESeaK2V5MN9e52V2HfsSEDEheVdG7uA+9UVM7K2WkDnX
zhfucJdYHa1OEwcnrWMZl+6gAMw7cjuaG3ckNzay+okNme9kiyrnjFzT7NWoCut8
WBbzmpbMCtWdHMk7HSkPDF2LhyB7jVBbbH7qvjjrfxy1L+ybAf8tZJ6urwn+7uCZ
dEe5YYghre2SXi4j9v+WJ+8024RaXG//7JsZvUEGs7Kb9CZAcqAdHwUiRK/rLckj
anHoDEpall0yyH3gZA5ETn8Gw7vChAhm1CTfhUYcV9kc7/9MiShOE1UbBNvjXvCW
e+0zixRrBp0LzJEkJD7b2NhjMLHyXS3D/uN1l5+d04uFwskttVhtQ26Icz3P/3T/
aELNcIemwLQeAIy4btAWYu5dKE0IR80Z/nYozR7W+at9rzt9/8FleALScMXgPRMf
HfcdKj9/cDzFNYOVtPf20gVXqSm/Yv+ZPYTpq45jKDH8U393Ly3XmNXAYOhflf+i
Zt0KBSFf86/+u3Uo0EsQo+4JBK8FpEJT3qz6On7hXevbFiVZsXvfH0MU9up6s11d
zfW56C4mHe0anB8y5Kc0ZKuOt4MzMJm0OOuuiZqnpnK2xFLBmlU=
=lmwJ
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v7.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Core changes:
- Drop the unused devm_pinctrl_unregister() function
- Move pretended generic pin control functionality out of the core
and into the Amlogic AM4 driver. We have something better coming
(hopefully)
New hardware support:
- Spacemit K3 (RISC-V) pin control support
- Atmel AT91 PIO4 (ARM32) SAMA7D65 pin control support
- Exynos9610 (ARM64) pin control support
- Qualcomm Mahua TLMM (ARM64) pin control support
- Microchip Polarfire MSSIO (RISC-V) pin control support
- Ocelot LAN9645XF (multiplatform) pin control support
Improvements:
- Using a few more guards for locking
- Various nonurgent fixes and tweaks"
* tag 'pinctrl-v7.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (73 commits)
pinctrl: generic: move function to amlogic-am4 driver
pinctrl: intel: Align Copyright note with corporate guidelines
pinctrl: mediatek: remove unused drv_offset field
pinctrl: canaan: k230: Fix NULL pointer dereference when parsing devicetree
pinctrl: single: fix refcount leak in pcs_add_gpio_func()
pinctrl: meson: amlogic-a4: Fix device node reference leak in bank helpers
pinctrl: qcom: sm8250-lpass-lpi: Fix i2s2_data_groups definition
pinctrl: core: Remove duplicate error messages
pinctrl: core: Simplify devm_pinctrl_*()
pinctrl: core: Remove unused devm_pinctrl_unregister()
dt-bindings: pinctrl: spacemit: fix drive-strength check warning
pinctrl: fix kismet issues with GENERIC_PINCTRL
pinctrl: tangier: Join tng_pinctrl_probe() into its wrapper
pinctrl: tangier: Remove duplicate error messages
pinctrl: lynxpoint: Remove duplicate error messages
pinctrl: cherryview: Remove duplicate error messages
pinctrl: baytrail: Remove duplicate error messages
pinctrl: intel: Remove duplicate error messages
pinctrl: equilibrium: Fix device node reference leak in pinbank_init()
dt-bindings: pinctrl: pinctrl-microchip-sgpio: add LAN969x
...
|
||
|
Linus Torvalds
|
13c916af3a |
Not much changed in the clk framework this time except the clk.h consumer API
moved the context saving APIs around to fix a build error in certain
configurations. There was a change to the core framework for
CLK_OPS_PARENT_ENABLE behavior during registration, but it wrecked existing
drivers that didn't expect things to be turned off during clk registration so
it got reverted.
This cycle is really a large collection of new clk drivers, primarily for
Qualcomm SoCs but also for Amlogic, SpacemiT, Google, and Aspeed. Another big
change in here is support for automatic hardware clock gating on Samsung SoCs
where the clks turn on and off when needed. Ideally more vendors move to this
method for better power savings. The highlights are in the updates section
below.
Beyond all the new drivers we have a bunch of cleanups like converting drivers
from divider_round_rate() to divider_determine_rate() and using scoped for each
OF child loops. Otherwise it's the usual data fixes and plugging reference
leaks, etc. that's all pretty ordinary but not critical enough to fix until the
next release.
New Drivers:
- Qualcomm Kaanapali global, tcsr, rpmh, display, gpu, camera, and video clk
controllers
- Qualcomm SM8750 camera clk controllers
- Qualcomm MSM8940 and SDM439 global clk controllers
- Google GS101 Display Process Unit (DPU) clk controllers
- SpacemiT K3 clk controllers
- Amlogic t7 clk controllers
- Aspeed AST2700 clk controllers
Updates:
- Convert clock dividers from round_rate() to determine_rate()
- Fix sparse warnings, kernel-doc warnings, and plug leaked OF refs
- Automatic hardware clk gating on Google GS101 SoCs
- Amlogic s4 video clks
- CAN-FD clks and resets on Renesas RZ/T2H, RZ/N2H, RZ/V2H, and RZ/V2N
- Expanded Serial Peripheral Interface (xSPI) clocks and resets on Renesas
RZ/T21H and RZ/N2H
- DMAC, interrupt controller (ICU), SPI, and thermal (TSU) clocks and resets
on Renesas RZ/V2N
- More serial (RSCI) clocks and resets on Renesas RZ/V2H and RZ/V2N
- CPU frequency scaling on T-HEAD TH1520
-----BEGIN PGP SIGNATURE-----
iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmmRJfYUHHN3Ym95ZEBj
aHJvbWl1bS5vcmcACgkQrQKIl8bklSUmIhAAttGxK++IiMe1XTPOezlf6jXP4Hj/
/RAJchCs4y9NeGzOAnwQeGHMSNz70PFcZ3hYAS7w32GHQI+4VHKlmrgT62TqJMCl
79jvQuojGngJcW5uQ531WYB/Iy76b8U+RBiAtFCrfYZa50HAWLtaUPYLXlrDev78
Gx6XZULykcveMp1sC8zQt2zjHaJNs1x8cVD5dVhT8fD/KVw0au0I0f0C/S9qjvXG
NQVn2uSCz4/LkyZ63hxcELJuVEaGojKBD3ne+3EL8ELv/8jz2PT51mgyhWDvlH4A
JSgpdqpkIDnGZgEKt7BPEMLQaFTqD3c3MTQ87bhuTN/S16cG/cS3zTDT14/5nry7
uUGFM5KTtZGRbJaYAQSiNtFLhNt6/j33XmhmjrAqN+tmt+M47URzxt3CMHpIE2hK
+zghb83OU2Rm1fe7xd5K0J/gcA7gKXgAnwqWqATniIrCFmYqSRh9LTr+gtAqrKs0
smT9yav1rl+EVMG8xtCkjEUpGmYe1rvLVwcL7ODvZACW7Q/udjy6qYWV3CLHAVRy
QTnUkj05Ahk0I6qPWOvVPDRfMWCHdbyHiUzkPckuq+3TTSjm4GmqgqQO3XTtxcuF
G+LeeNVb3IwkDNrwmWCs/GGW3fAxQKnDTULqrb0eZhjMmW/OTtXGi99E9BeD0Ucu
o0HecyE5H+oIjtc=
=Zx/F
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Not much changed in the clk framework this time except the clk.h
consumer API moved the context saving APIs around to fix a build error
in certain configurations.
There was a change to the core framework for CLK_OPS_PARENT_ENABLE
behavior during registration, but it wrecked existing drivers that
didn't expect things to be turned off during clk registration so it
got reverted.
This cycle is really a large collection of new clk drivers, primarily
for Qualcomm SoCs but also for Amlogic, SpacemiT, Google, and Aspeed.
Another big change in here is support for automatic hardware clock
gating on Samsung SoCs where the clks turn on and off when needed.
Ideally more vendors move to this method for better power savings. The
highlights are in the updates section below.
Beyond all the new drivers we have a bunch of cleanups like converting
drivers from divider_round_rate() to divider_determine_rate() and
using scoped for each OF child loops. Otherwise it's the usual data
fixes and plugging reference leaks, etc. that's all pretty ordinary
but not critical enough to fix until the next release.
New Drivers:
- Qualcomm Kaanapali global, tcsr, rpmh, display, gpu, camera, and
video clk controllers
- Qualcomm SM8750 camera clk controllers
- Qualcomm MSM8940 and SDM439 global clk controllers
- Google GS101 Display Process Unit (DPU) clk controllers
- SpacemiT K3 clk controllers
- Amlogic t7 clk controllers
- Aspeed AST2700 clk controllers
Updates:
- Convert clock dividers from round_rate() to determine_rate()
- Fix sparse warnings, kernel-doc warnings, and plug leaked OF refs
- Automatic hardware clk gating on Google GS101 SoCs
- Amlogic s4 video clks
- CAN-FD clks and resets on Renesas RZ/T2H, RZ/N2H, RZ/V2H, and
RZ/V2N
- Expanded Serial Peripheral Interface (xSPI) clocks and resets on
Renesas RZ/T21H and RZ/N2H
- DMAC, interrupt controller (ICU), SPI, and thermal (TSU) clocks and
resets on Renesas RZ/V2N
- More serial (RSCI) clocks and resets on Renesas RZ/V2H and RZ/V2N
- CPU frequency scaling on T-HEAD TH1520"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (165 commits)
clk: aspeed: Add reset for HACE/VIDEO
dt-bindings: clock: aspeed: Add VIDEO reset definition
clk: aspeed: add AST2700 clock driver
MAINTAINERS: Add entry for ASPEED clock drivers.
clk: aspeed: Move the existing ASPEED clk drivers into aspeed subdirectory.
Revert "clk: Respect CLK_OPS_PARENT_ENABLE during recalc"
clk: Disable KUNIT_UML_PCI
dt-bindings: clk: rs9: Fix DIF pattern match
clk: rs9: Convert to DEFINE_SIMPLE_DEV_PM_OPS()
clk: rs9: Reserve 8 struct clk_hw slots for for 9FGV0841
clk: qcom: sm8750: Constify 'qcom_cc_desc' in SM8750 camcc
clk: zynqmp: pll: Fix zynqmp_clk_divider_determine_rate kerneldoc
clk: zynqmp: divider: Fix zynqmp_clk_divider_determine_rate kerneldoc
clk: mediatek: Fix error handling in runtime PM setup
clk: mediatek: don't select clk-mt8192 for all ARM64 builds
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pll registration to pass device
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
...
|
||
|
Stephen Boyd
|
b675697d80
|
Merge branches 'clk-amlogic', 'clk-thead', 'clk-mediatek' and 'clk-samsung' into clk-next
* clk-amlogic: clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro clk: meson: g12a: Limit the HDMI PLL OD to /4 clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs clk: amlogic: remove potentially unsafe flags from S4 video clocks clk: amlogic: add video-related clocks for S4 SoC dt-bindings: clock: add video clock indices for Amlogic S4 SoC clk: meson: t7: add t7 clock peripherals controller driver clk: meson: t7: add support for the T7 SoC PLL clock dt-bindings: clock: add Amlogic T7 peripherals clock controller dt-bindings: clock: add Amlogic T7 SCMI clock controller dt-bindings: clock: add Amlogic T7 PLL clock controller * clk-thead: clk: thead: th1520-ap: Support CPU frequency scaling clk: thead: th1520-ap: Add macro to define multiplexers with flags clk: thead: th1520-ap: Support setting PLL rates clk: thead: th1520-ap: Add C910 bus clock clk: thead: th1520-ap: Poll for PLL lock and wait for stability dt-bindings: clock: thead,th1520-clk-ap: Add ID for C910 bus clock * clk-mediatek: Revert "clk: Respect CLK_OPS_PARENT_ENABLE during recalc" clk: mediatek: Fix error handling in runtime PM setup clk: mediatek: don't select clk-mt8192 for all ARM64 builds clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks clk: mediatek: Refactor pllfh registration to pass device clk: mediatek: Pass device to clk_hw_register for PLLs clk: mediatek: Refactor pll registration to pass device clk: Respect CLK_OPS_PARENT_ENABLE during recalc dt-bindings: clock: mediatek,mt7622-pciesys: Remove syscon compatible clk: mediatek: Drop __initconst from gates * clk-samsung: clk: samsung: gs101: add support for Display Process Unit (DPU) clocks dt-bindings: samsung: exynos-sysreg: add gs101 dpu compatible dt-bindings: clock: google,gs101-clock: Add DPU clock management unit dt-bindings: clock: google,gs101-clock: fix alphanumeric ordering clk: samsung: fix sysreg save/restore when PM is enabled for CMU clk: samsung: avoid warning message on legacy Exynos (auto clock gating) clk: samsung: gs101: Enable auto_clock_gate mode for each gs101 CMU clk: samsung: Implement automatic clock gating mode for CMUs dt-bindings: clock: google,gs101-clock: add samsung,sysreg property as required clk: samsung: exynosautov920: add clock support dt-bindings: clock: exynosautov920: add MFD clock definitions |
||
|
Linus Torvalds
|
6589b3d76d |
soc: devicetree updates for 7.0
There are a handful of new SoCs this time, all of these are
more or less related to chips in a wider family:
- SpacemiT Key Stone K3 is an 8-core risc-v chip, and the first
widely available RVA23 implementation. Note that this is
entirely unrelated with the similarly named Texas Instruments
K3 chip family that follwed the TI Keystone2 SoC.
- The Realtek Kent family of SoCs contains three chip models
rtd1501s, rtd1861b and rtd1920s, and is related to their earlier
Set-top-box and NAS products such as rtd1619, but is built
on newer Arm Cortex-A78 cores.
- The Qualcomm Milos family includes the Snapdragon 7s Gen 3
(SM7635) mobile phone SoC built around Armv9 Kryo cores of the Arm
Cortex-A720 generation. This one is used in the Fairphone Gen 6
- Qualcomm Kaanapali is a new SoC based around eight high
performance Oryon CPU cores
- NXP i.MX8QP and i.MX952 are both feature reduced versions of
chips we already support, i.e. the i.MX8QM and i.MX952, with
fewer CPU cores and I/O interfaces.
As part of a cleanup, a number of SoC specific devicetree files got
removed because they did not have a single board using the .dtsi files
and they were never compile tested as a result: Samsung s3c6400,
ST spear320s, ST stm32mp21xc/stm32mp23xc/stm32mp25xc, Renesas
r8a779m0/r8a779m2/r8a779m4/r8a779m6/r8a779m7/r8a779m8/r8a779mb/
r9a07g044c1/r9a07g044l1/r9a07g054l1/r9a09g047e37, and TI am3703/am3715.
All of these could be restored easily if a new board gets merged.
Broadcom/Cavium/Marvell ThunderX2 gets removed along with its only
machine, as all remaining users are assumed to be using ACPI
based firmware.
A relatively small number of 43 boards get added this time, and
almost all of them for arm64. Aside from the reference boards for
the newly added SoCs, this includes:
- Three server boards use 32-bit ASpeed BMCs
- One more reference board for 32-bit Microchip LAN9668
- 64-bit Arm single-board computers based on Amlogic s905y4,
CIX sky1, NXP ls1028a/imx8mn/imx8mp/imx91/imx93/imx95,
Qualcomm qcs6490/qrb2210 and Rockchip rk3568/rk3588s
- Carrier board for SOMs using Intel agilex5, Marvell Armada 7020,
NXP iMX8QP, Mediatek mt8370/mt8390 and rockchip rk3588
- Two mobile phones using Snapdragon 845
- A gaming device and a NAS box, both based on Rockchips rk356x
On top of the newly added boards and SoCs, there is a lot of
background activity going into cleanups, in particular towards
getting a warning-free dtc build, and the usual work on adding
support for more hardware on the previously added machines.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmmLSTIACgkQmmx57+YA
GNk6xw//bn239Nn6XUSrmm3b7SGDf+9AvdrukrUEOsIYBYUM7fkulVSINpVOSzZU
DAxLSCY1qfE9zP4x+hrYv922w9Rt19zPuEwFVCslbbTk9NN8IhmhIOs06o2jrvN3
HS/AcESV2SCUe0EVjDIdBgisKMGdbN2t8bdrFFOmqUkQ+7EJ2GvNL0MoaKrdF+Sr
ilt5Hhkl6ixbGDq2KEB2QQHQhYKa/5GdKS0CLTY4et/dZbjHVg9o6/sfgIhLINCz
wNb9CKnt1Gv5L3RWW2LxQrrNe5qhLmHq1vmPbxSJGrzqnOwY9Tcg4s1Io9EcDtyW
LZlq4PkLJV9oPVHgi0mygZ3ONVhWhCMVhTXg6Osi1aHJeEERuIaYMfeU7WD0jHv8
ZcGboxfyiQmphRJumL0C74uIuuXgdoKrv7gqQvo9dy+HRxdHW/7p8TQi9SSfh7kF
Iysc2ePMmqLd4WJCMxV+7FrT8oZxOL+/KfisCu6n/Qdv65kTWmBlLCK6XZrmWYyk
YKg48F8xpQaSmgevWePwhcH0a/TmgmoT+6xOfTuyo88k65FLXXmrFp14th2Kg5sI
60W9ur6ujPI3s19H9C3IQp7ub5Ermvj+g893zEB1e2CR9blfqRARV9zFSv4OMkq+
hQmqe5cU9/17k7wchFke4Y/FsS8W2oFFJ9o6czOTnh5NhlpVSJw=
=IK23
-----END PGP SIGNATURE-----
Merge tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"There are a handful of new SoCs this time, all of these are more or
less related to chips in a wider family:
- SpacemiT Key Stone K3 is an 8-core risc-v chip, and the first
widely available RVA23 implementation. Note that this is entirely
unrelated with the similarly named Texas Instruments K3 chip family
that follwed the TI Keystone2 SoC.
- The Realtek Kent family of SoCs contains three chip models
rtd1501s, rtd1861b and rtd1920s, and is related to their earlier
Set-top-box and NAS products such as rtd1619, but is built on newer
Arm Cortex-A78 cores.
- The Qualcomm Milos family includes the Snapdragon 7s Gen 3 (SM7635)
mobile phone SoC built around Armv9 Kryo cores of the Arm
Cortex-A720 generation. This one is used in the Fairphone Gen 6
- Qualcomm Kaanapali is a new SoC based around eight high performance
Oryon CPU cores
- NXP i.MX8QP and i.MX952 are both feature reduced versions of chips
we already support, i.e. the i.MX8QM and i.MX952, with fewer CPU
cores and I/O interfaces.
As part of a cleanup, a number of SoC specific devicetree files got
removed because they did not have a single board using the .dtsi files
and they were never compile tested as a result: Samsung s3c6400, ST
spear320s, ST stm32mp21xc/stm32mp23xc/stm32mp25xc, Renesas
r8a779m0/r8a779m2/r8a779m4/r8a779m6/r8a779m7/r8a779m8/r8a779mb/
r9a07g044c1/r9a07g044l1/r9a07g054l1/r9a09g047e37, and TI
am3703/am3715. All of these could be restored easily if a new board
gets merged.
Broadcom/Cavium/Marvell ThunderX2 gets removed along with its only
machine, as all remaining users are assumed to be using ACPI based
firmware.
A relatively small number of 43 boards get added this time, and almost
all of them for arm64. Aside from the reference boards for the newly
added SoCs, this includes:
- Three server boards use 32-bit ASpeed BMCs
- One more reference board for 32-bit Microchip LAN9668
- 64-bit Arm single-board computers based on Amlogic s905y4, CIX
sky1, NXP ls1028a/imx8mn/imx8mp/imx91/imx93/imx95, Qualcomm
qcs6490/qrb2210 and Rockchip rk3568/rk3588s
- Carrier board for SOMs using Intel agilex5, Marvell Armada 7020,
NXP iMX8QP, Mediatek mt8370/mt8390 and rockchip rk3588
- Two mobile phones using Snapdragon 845
- A gaming device and a NAS box, both based on Rockchips rk356x
On top of the newly added boards and SoCs, there is a lot of
background activity going into cleanups, in particular towards getting
a warning-free dtc build, and the usual work on adding support for
more hardware on the previously added machines"
* tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (757 commits)
dt-bindings: intel: Add Agilex eMMC support
arm64: dts: socfpga: agilex: add emmc support
arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node
ARM: dts: socfpga: fix dtbs_check warning for fpga-region
ARM: dts: socfpga: add #address-cells and #size-cells for sram node
dt-bindings: altera: document syscon as fallback for sys-mgr
arm64: dts: altera: Use lowercase hex
dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml
arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes
arm64: dts: socfpga: agilex5: add support for modular board
dt-bindings: intel: Add Agilex5 SoCFPGA modular board
arm64: dts: socfpga: agilex5: Add dma-coherent property
arm64: dts: realtek: Add Kent SoC and EVB device trees
dt-bindings: arm: realtek: Add Kent Soc family compatibles
ARM: dts: samsung: Drop s3c6400.dtsi
ARM: dts: nuvoton: Minor whitespace cleanup
MAINTAINERS: Add Falcon DB
arm64: dts: a7k: add COM Express boards
ARM: dts: microchip: Drop usb_a9g20-dab-mmx.dtsi
arm64: dts: rockchip: Fix rk3588 PCIe range mappings
...
|
||
|
Arnd Bergmann
|
f51d34065d |
SoCFPGA DTS updates for v6.20, version 3
- dt-bindings updates: - Add intel,socfpga-agilex5-socdk-modular for the Agilex5 mod board - Add intel,socfpga-agilex-emmc for the Agilex eMMC daughter board - Move entries in intel,socfpga.yaml into altera.yaml - Add syscon as a fallback for sys-mgr - Add dma-cohrerent property for Agilex5 NAND and DMA - Add support for the Agilex5 modular board - Add IOMMUS property for ethernet nodes for Agilex5 - Use lowercase hex for dts files - Add #address-cells and #size-cells for sram - Fix dtbs_check warning for fpga-region - Move dma controller node for Agilex5 under simple-bus - Add support for the Agilex eMMC daughter board -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEoHhMeiyk5VmwVMwNGZQEC4GjKPQFAmmBaFYACgkQGZQEC4Gj KPQLjxAAovoapeOuk0Ps+O31v9NCzuRfIwvGC1YryL4+REqU6PIJxEV7rJKL9bxy HePefbDgOtuukwqcy/IF/rN8av3ETqbRif4c0Gdt6vzOJ5TRCwdbVctLJQlchG/h CCv86QiDNt5VmCXJ8aONNcuUl1RmKRgScv5teeL4bPFhOwXfPYsjR6n7AexwDfCm qFw3b8xR1Qo4kQrn8NQwa5aJ/YrC9zeMgJMN8Yd8Zqe07MzLRCPlKioPi04zG9Gz Sd4NFLzBNW3PNwZxjQjGaZ99f5MDRMMrIFDUFN6qyyKpF0u+z8jboZ0KfuE8AWSH SpRp2MD5wdCv2jfynfvaHYZJCbf2yO9KUwI0BTNbfZK2PB/Kjbh1NtfuyTzU1CyS 26RumUjItmEW0DHiHxHWEIqUQH18LPX95+aiX3HDEg4DC8AcYDqER6udzIEVvb0f z1XftA5uwy59tzgFLear/UV+u0kq8H3ndBHvsrSsCuXiekXEz3N9JddRmZrDve6Y 5PorxK0CA9SiMIknTwPgR+C1WEhdw0CBJsjz1jWijqw8ZIHB70MpU7Tk4j1qJlbL 7GpOQySIy5qcg2m9SS7yvCWtBt8xdtbj9cR8UnEEuJKzTnahxHcfYnontuUbYyJd zSQ0JKndpwb4QCmOAYswsp4WVOGfnVCPia4Eu4L94BRN16hv+to= =ux17 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmmC954ACgkQmmx57+YA GNl1Hw/+KMtxRTV2Gy8jUIJmWl3G1OXJ2n9HDyo+fSH9c9IqyU3RcLxWqQlENaz7 MCxRIozKbjSvwNOgx7wkbmxY5oyEnZ0hqr0ylsn/wctBTCghaqID6IZd+5fdigS9 1VqFeVB+i5GvihJ1mJDEHaUAjfahc9JA30da+oAqBkAsT89MkAn6Iaaze44tIlu1 7i2EFzaMB7Gb5WXZ340x1rDM/u6cjR9iEYSXqSjmj+upy5xYuINzWDRN/1ZFtkTh 44xoOoZ+rH7wnLYzx0gWoEcH+RA7yDbicaqJ4l+u1lbUNAsz46WfXbdys/kGKE8F Us6gXbLlZ+ZDGxB3dEqsOvxfI3u2u1Ehz69b+nZxNf2Fh5NDBSjkzcu30BywMgpj NPY/XqK9DA6G7M405rYaIJQMSiDqevZnBS35/jtq3t5pYmkuKUvwG6/8XexrOq00 FXGX7JS8nEm8U3DFjwT6Z+Hg4Psm/nZxsv6KiarvJWDuhUeJRJM0qY2IF1dAYi1g LONh1Lt/WNHqDyF8bWkP6cT7zCGZ5Tlozj+3V/oyPNi6VndA6sNzIi9L/oR3oHOD vBGnEr95QaxZ/FaqNvMJo54DNBR3NEscDe3rAi+B4WaAH04EtSKMOwaY3pN9edwj H0hnbWU0bYsCfWDTbS698+lxTD/zCsBTEoWSFo0iL8mus0ArIgw= =XO7t -----END PGP SIGNATURE----- Merge tag 'socfpga_dts_updates_for_v6.20_v3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt SoCFPGA DTS updates for v6.20, version 3 - dt-bindings updates: - Add intel,socfpga-agilex5-socdk-modular for the Agilex5 mod board - Add intel,socfpga-agilex-emmc for the Agilex eMMC daughter board - Move entries in intel,socfpga.yaml into altera.yaml - Add syscon as a fallback for sys-mgr - Add dma-cohrerent property for Agilex5 NAND and DMA - Add support for the Agilex5 modular board - Add IOMMUS property for ethernet nodes for Agilex5 - Use lowercase hex for dts files - Add #address-cells and #size-cells for sram - Fix dtbs_check warning for fpga-region - Move dma controller node for Agilex5 under simple-bus - Add support for the Agilex eMMC daughter board * tag 'socfpga_dts_updates_for_v6.20_v3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: dt-bindings: intel: Add Agilex eMMC support arm64: dts: socfpga: agilex: add emmc support arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node ARM: dts: socfpga: fix dtbs_check warning for fpga-region ARM: dts: socfpga: add #address-cells and #size-cells for sram node dt-bindings: altera: document syscon as fallback for sys-mgr arm64: dts: altera: Use lowercase hex dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes arm64: dts: socfpga: agilex5: add support for modular board dt-bindings: intel: Add Agilex5 SoCFPGA modular board arm64: dts: socfpga: agilex5: Add dma-coherent property Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Dinh Nguyen
|
42918d28cb |
dt-bindings: altera: document syscon as fallback for sys-mgr
For 32-bit Altera SoCFPGA parts, the sys-mgr uses the syscon as a fallback. This change addresses this warning from dtbs_check: sysmgr@ffd08000 (altr,sys-mgr): compatible: 'oneOf' conditional failed, one must be fixed: ['altr,sys-mgr', 'syscon'] is too long 'altr,sys-mgr-s10' was expected 'altr,sys-mgr' was expected from schema $id: http://devicetree.org/schemas/soc/altera/altr,sys-mgr.yaml Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> |
||
|
Arnd Bergmann
|
a393bda150 |
Reset controller updates for v6.20
* Add a compatible to the reset-gpio driver, suppress the sysfs bind attributes, and propagate GPIO API errors. * Add support for the i.MX8ULP SIM LPAV reset controller. * Add RZ/G3S USBPHY suspend/resume support. * Enable reset-k230 by default on ARCH_CANAAN * Add support for the SpacemiT K3 SoC reset controller. * Merge the 'spacemit-clkrst-v6.20-3' tag, shared with the clk tree, as a dependency for the SpacemiT changes. -----BEGIN PGP SIGNATURE----- iI0EABYKADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCaXiRShcccC56YWJlbEBw ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwDWkAP0foLlNQzqjNj7uT6ysYoHwbixE +F9iaLCqJ9SAS5ajcwEAvJdJOJJCHGLR/4ImjH4AdCC1RqENUPYTqivvjZ3ozAU= =Z0D4 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml7J0sACgkQmmx57+YA GNnDxhAAn5icxeT8YFUJjKnYCnNx3gOVP9sdSQRc+MOdTwSNen6LdVqaXhYJij2y yqTk138Ulr3NUG84k3p75Rajz6TbMsVY1usuqa+vJqr9ruuPmAIx1xTEI/Hb6HVM 4k2NeSk2osYSx/o0xgOC3qPA8fGAw/sdduFkU69wrWPAfoxg5uK+OQyJ8VJRnhFQ 45WnIZ+Z8AtINhJiq88cowilf762PTEi2t6PRjsI/E5JJplQXYyi2Kpx48nYHmrp Kfl0bmNIM7a7fVOAXd/fdQ7QYex/qhUZzZy1GZh7uo3VSVyjLJuN2ZHkxvmfjIjG x2SyAhfuryvCWiN7GDJcreiPNJOOkBtzjvisCvBQE9OFYSsZd2YRhb2cluK7YUZt mlSPxqqD0Z+Y4/03pXAdLmAiUYqq2ZZeLiO4u6ExwYrHu7lcJlhmSMXdcokiMVwo 1QRRaJiXc5qcr/s/xkKT91Kmy1ncwiulb0Py2WkUaGTPKjPCqvPgHQ2PDZ6za9Eo ilsn6yyuBfn3Dlcat2o59frXDp5/GggHx0gcxq6CrEWUUwchUbvHy0IMfqUNdzo4 dTT2HKwse+GPDfK9Rm8O1UiRGaWMBSW68db2X4KNGeKj3PvakDyAz7CxdCa86E3g HfFQDzTK8bzlSnXCvjH9/q99aqxwAxs171NkveE3nx+NPqxptXc= =P4vq -----END PGP SIGNATURE----- Merge tag 'reset-for-v6.20' of https://git.pengutronix.de/git/pza/linux into soc/drivers Reset controller updates for v6.20 * Add a compatible to the reset-gpio driver, suppress the sysfs bind attributes, and propagate GPIO API errors. * Add support for the i.MX8ULP SIM LPAV reset controller. * Add RZ/G3S USBPHY suspend/resume support. * Enable reset-k230 by default on ARCH_CANAAN * Add support for the SpacemiT K3 SoC reset controller. * Merge the 'spacemit-clkrst-v6.20-3' tag, shared with the clk tree, as a dependency for the SpacemiT changes. * tag 'reset-for-v6.20' of https://git.pengutronix.de/git/pza/linux: reset: spacemit: Add SpacemiT K3 reset driver reset: spacemit: Extract common K1 reset code reset: Create subdirectory for SpacemiT drivers dt-bindings: soc: spacemit: Add K3 reset support and IDs reset: canaan: k230: drop OF dependency and enable by default reset: rzg2l-usbphy-ctrl: Add suspend/resume support reset: rzg2l-usbphy-ctrl: Propagate the return value of regmap_field_update_bits() reset: gpio: check the return value of gpiod_set_value_cansleep() reset: imx8mp-audiomix: Support i.MX8ULP SIM LPAV reset: imx8mp-audiomix: Extend the driver usage reset: imx8mp-audiomix: Switch to using regmap API reset: imx8mp-audiomix: Drop unneeded macros reset: gpio: suppress bind attributes in sysfs clk: spacemit: k3: extract common header reset: spacemit: fix auxiliary device id clk: spacemit: prepare common ccu header reset: gpio: add the "compatible" property Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Arnd Bergmann
|
35a53670ea |
MediaTek soc driver updates
This adds:
- A socinfo entry for the MT8371 Genio 520 SoC
- Support for the Dynamic Voltage and Frequency Scaling
Resource Controller (DVFSRC) version 4, found in the
new MediaTek Kompanio Ultra (MT8196) SoC
- Initial support for the CMDQ mailbox found in the MT8196.
- A memory leak fix in the MediaTek SVS driver's debug ops.
-----BEGIN PGP SIGNATURE-----
iLoEABYKAGIWIQQn3Xxr56ypAcSHzXSaNgTPrZeEeAUCaXNXhhsUgAAAAAAEAA5t
YW51MiwyLjUrMS4xMSwyLDIoHGFuZ2Vsb2dpb2FjY2hpbm8uZGVscmVnbm9AY29s
bGFib3JhLmNvbQAKCRCaNgTPrZeEeF2oAQDcnPsR1I6J92rmK75Dufy4ayA79Ko0
j2cYEOzAoO+mzgD/SDq0VGMpPhyatUv5Lj8md69gARhNlylJVDIpC0jBQAQ=
=v4Rp
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml7I8IACgkQmmx57+YA
GNmr5g//fM9YAmf/oA9AT6Ta4bQWzzzp9dSIZ18I8v7G4RSpCK9uVK0mVhH4JceU
QXt63dTL+wAZOHjCIXgpQzcZ6tXdCaD4XZux87Ab+EfrxVPBQbOkwMAA4rkj8Vbd
LLJ36G2qOyBvpw8+whCmsQCcUn9UqWuDWkgnIRRt04tn/QOCi5XQcKIdvyzQdglB
TlbGQKxW4XQXzKr1pDrgSF9mie3jtw9Z7povlTiUIhnfqCIkoS5X2upcyWAtGpjr
ON2t5lIH3TvlrhanqREfHltRBB1GF4AvAadaj0q9dA9DoZLwTlr7SfoiSHiR8kf+
QongU9Y4ObeLriAsyDT5/SNZ11lSIL+f2jpJMBTzdQ9+NpalE9mgWHA7O76iR4vf
E3SdwDRSykSXiNg+wzi6GeccHYE1yrpRu05g/MSCuO3N7AMqIYHmvfbWg2sM0ruS
8J0OYdEbr+JmVScYQ7GPHOdcwgdv4mAn5ENjhwmNjWTYMdjPNi1PnQwrXUzo3jYV
s7s8+P8yg4aABdPuDH+vDDaVj5T/fHy+OedMkRtGBfHbInu2WG/g4x6kDutiCR1L
b7Zu72psQEDAtfRrRnQP0/P+8/M7HLV0lbMVWf0H78lM3dQKOHTi6uuyT55IWCTv
WIwITw4Lo9BzapGjBU7QU2YcEW+t6mJ126wo1UbcM7V4JPcID40=
=i7PU
-----END PGP SIGNATURE-----
Merge tag 'mtk-soc-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/drivers
MediaTek soc driver updates
This adds:
- A socinfo entry for the MT8371 Genio 520 SoC
- Support for the Dynamic Voltage and Frequency Scaling
Resource Controller (DVFSRC) version 4, found in the
new MediaTek Kompanio Ultra (MT8196) SoC
- Initial support for the CMDQ mailbox found in the MT8196.
- A memory leak fix in the MediaTek SVS driver's debug ops.
* tag 'mtk-soc-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
soc: mediatek: mtk-cmdq: Add mminfra_offset adjustment for DRAM addresses
soc: mediatek: mtk-cmdq: Extend cmdq_pkt_write API for SoCs without subsys ID
soc: mediatek: mtk-cmdq: Add pa_base parsing for hardware without subsys ID support
soc: mediatek: mtk-cmdq: Add cmdq_get_mbox_priv() in cmdq_pkt_create()
mailbox: mtk-cmdq: Add driver data to support for MT8196
mailbox: mtk-cmdq: Add mminfra_offset configuration for DRAM transaction
mailbox: mtk-cmdq: Add GCE hardware virtualization configuration
mailbox: mtk-cmdq: Add cmdq private data to cmdq_pkt for generating instruction
soc: mediatek: mtk-dvfsrc: Rework bandwidth calculations
soc: mediatek: mtk-dvfsrc: Get and Enable DVFSRC clock
soc: mediatek: mtk-dvfsrc: Add support for DVFSRCv4 and MT8196
soc: mediatek: mtk-dvfsrc: Write bandwidth to EMI DDR if present
soc: mediatek: mtk-dvfsrc: Add a new callback for calc_dram_bw
soc: mediatek: mtk-dvfsrc: Add and propagate DVFSRC bandwidth type
soc: mediatek: mtk-dvfsrc: Change error check for DVFSRCv4 START cmd
dt-bindings: soc: mediatek: dvfsrc: Document clock
soc: mediatek: mtk-socinfo: Add entry for MT8371AV/AZA Genio 520
soc: mediatek: svs: Fix memory leak in svs_enable_debug_write()
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
||
|
Arnd Bergmann
|
896cc203af |
Samsung DTS ARM64 changes for v6.20
1. ExynosAutov920:
- Add MFD clock controller node.
2. Google GS101:
- Add True Random Number Generator (TRNG) and OTP nvmem nodes.
- Correct the PMU (Power Management Unit) compatibles by dropping
fallback to syscon. The PMU on Samsung devices serves the role of
syscon, however on GS101 it cannot be used via standard Linux syscon
interface, because register accesses require custom regmap. It was
simply never correctly working with "syscon" compatible fallback.
- Add phandles to System Registers SYSREG blocks in clock controllers,
necessary for enabling automatic clock control later.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmlrzm8QHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD13BJD/4s3Q75bedb7izJ3kvBYTE4Rj1WnfDokx0u
E8STJ5p6FrEB2AKxLSRJTW4/Ih0Bp52G+sBUMetKzUlEznXaJ9c8TdJ9hPRDUYh7
at9R2wpyyWWFOXLIAuNp0nohxUuCiNrJssZZZTsJzV1yFodCG3aPYn38/oNrKVTx
Uhl9zBxTtdGclpPi/npue34oEQRv824AXlu1DSjBbEJfuDYxX5uijcs8T97l2Dtj
rb6Mm2cjTvvU1pTR9sCzGrBxtHP92kl/72w8iSgfvi6OsXqvcHLDdNdhJYvAjdnl
eQNFe0XSFUZDT7pLv+gW/5PEGrO3J6sTKCk5xkic4yQczVr/pqdnxajSGvodOmQu
AQB5EcDwExFGhttiXUEAyG85MVOsLJv+i6sU+2VLQVDOc7+DCMidP0DMgfPh/B/S
dRb0dCTBKWGSnUL1iAnWLVUjxkmnbecA1EcE8/AxG++vn2bXo9t+w1J9LYcwkebU
lrZHj9DjJLvzg6ejBUbwMotzK+c1hYH9WqYGZOcdsw7jPd7ULEaJs1ycO0Oreny4
t8oae9wF85eD4aCZ9KLRnp3l9v2w/cIWzvOLwcqaIsANiVvTy2i3pxLyfkvwgQ2g
+gjms9FTH2IoJ36Y0+RmBklYABOodZiYF+e8eEoioo7xOS6FhMaYQRCcyfMgb9n2
gACUifUGAQ==
=xVlA
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml3fXEACgkQmmx57+YA
GNlNdRAAvxo6wZ1vv1UsVUbGhZ3TmSlYEkYYBo73GMVzkaXRm7HyPA5zo5I+yJRJ
QtH5SPYqgdzfeZGMjnMFGG/IIO4ZB4g7SEWHMFROdz1IIzjTzv5ZBt1rK2tvj7Ok
9gQKWwOnjDPxIcXRHDFcMwAF1WXPvOqTlGbTWBz5PoYcsU6II47ifbLqvautAn24
S74tBfjGukn5kodrtytJOyZt/Vc7NjR6oAXSQ+M7c+Yff4UbHWxRSSHwfGPVFBVB
vdkfg0rY3tzdLs1PUWWgC8T9O/xhILeCnxhnlbgo7u0a+3CnAdQcbfWhmSPPNYzT
+xX/bo6f+FzBPTVeK08QGAvVPH+dHWxk0aktABjS3Hpk6/fOwpCum1oJUECF2SiM
43huYrJZCGLHW12CmEEAKg52rghkqPJkevn+lBXnF5l862/VSeQ/LZUuHIXKK6a1
2xqJqnbzvlHqdjdTrCFC/v9xyQvwJXZt3BH6I8l1oN1ppunZb7jCAlESMGDYjhVZ
NBYsU21eeYCG07+QtvDZ4TSipmtq6RQsvW7fDuvQKSSiNMOOTs6iP5VH0RC48al1
rLUKwiPmYvFSlFBEwt2AIVECtHA73W4MQJgp4s6gwpS2XDYsHTi8NiUx9LbTha7s
kuqrCuwRcY0IQs7dwdDYAggkeQBsYsTWhZi+SGfeHyNlb2y3ur0=
=pNN2
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.20
1. ExynosAutov920:
- Add MFD clock controller node.
2. Google GS101:
- Add True Random Number Generator (TRNG) and OTP nvmem nodes.
- Correct the PMU (Power Management Unit) compatibles by dropping
fallback to syscon. The PMU on Samsung devices serves the role of
syscon, however on GS101 it cannot be used via standard Linux syscon
interface, because register accesses require custom regmap. It was
simply never correctly working with "syscon" compatible fallback.
- Add phandles to System Registers SYSREG blocks in clock controllers,
necessary for enabling automatic clock control later.
* tag 'samsung-dt64-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: gs101: add OTP node
arm64: dts: exynos: gs101: add samsung,sysreg property to CMU nodes
arm64: dts: exynosautov920: add CMU_MFD clock DT nodes
arm64: dts: exynos: gs101: remove syscon compatible from pmu node
dt-bindings: soc: samsung: exynos-pmu: remove syscon for google,gs101-pmu
arm64: dts: exynos: gs101: add TRNG node
dt-bindings: rng: add google,gs101-trng compatible
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
||
|
Guodong Xu
|
216e0a5e98 |
dt-bindings: soc: spacemit: Add K3 reset support and IDs
Update the spacemit,k1-syscon.yaml binding to document K3 SoC reset support. K3 reset devices are registered at runtime as auxiliary devices by the K3 CCU driver. Since K3 reuses the K1 syscon binding, there is no separate YAML binding file for K3 resets. Update #reset-cells description to document where reset IDs are defined. Acked-by: Alex Elder <elder@riscstar.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Guodong Xu <guodong@riscstar.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Conor Dooley
|
6b324d1994 |
dt-bindings: pinctrl: document polarfire soc mssio pin controller
On Polarfire SoC, the Bank 2 and Bank 4 IOs connected to the Multiprocessor Subsystem (MSS) are controlled by IOMUX_CRs 1 through 6, which determine what function in routed to them, and MSSIO_BANK#_IO_CFG_CRs, which determine the configuration of each pin. Document it, including several custom configuration options that stem from MSS Configurator options (the MSS Configurator is part of the FPGA tooling for this device). "ibufmd" unfortunately is not a 1:1 mapping with an MSS Configurator option, unlike clamp-diode or lockdown, and I do not know the effect of any bits in the field. I have no been able to find an explanation for these bits in documentation. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org> |
||
|
Peter Griffin
|
1d8fae6617 |
dt-bindings: samsung: exynos-sysreg: add gs101 dpu compatible
Add dedicated compatibles for gs101 dpu sysreg controllers to the documentation. Reviewed-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260113-dpu-clocks-v3-3-cb85424f2c72@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> |
||
|
Herve Codina (Schneider Electric)
|
f3b795d298 |
dt-bindings: soc: renesas: Document RZ/N1 GPIO Interrupt Multiplexer
On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines. The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines. Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260114093938.1089936-7-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
||
|
Yixun Lan
|
efe897b557
|
dt-bindings: soc: spacemit: k3: add clock support
Add compatible strings for clock drivers to support Spacemit K3 SoC, also includes all the defined clock IDs. The SpacemiT K3 SoC clock IP is scattered over several different blocks, which are APBC, APBS, APMU, DCIU, MPMU, all of them are capable of generating clock and reset signals. APMU and MPMU have additional Power Domain management functionality. Following is a brief list that shows devices managed in each block: APBC: UART, GPIO, PWM, SPI, TIMER, I2S, IR, DR, TSEN, IPC, CAN APBS: various PPL clocks control APMU: CCI, CPU, CSI, ISP, LCD, USB, QSPI, DMA, VPU, GPU, DSI, PCIe, EMAC.. DCID: SRAM, DMA, TCM MPMU: various PLL1 derived clocks, UART, WATCHDOG, I2S Link: https://lore.kernel.org/r/20260108-k3-clk-v5-1-42a11b74ad58@gentoo.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Yixun Lan <dlan@gentoo.org> |
||
|
Nicolas Frattaroli
|
831ee17036
|
dt-bindings: soc: mediatek: dvfsrc: Document clock
The DVFSRC hardware has a clock on all platforms. Instead or proliferating the culture of omitting clock descriptions in the clock controller drivers or marking them critical instead of declaring these types of relationships, add this one to the binding. Any device that wishes to use this binding should figure out their incomplete or incorrect clock situation first before piling more features on top. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |