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SoCFPGA DTS updates for v6.20, version 3

Browse Source 
- dt-bindings updates:
 	- Add intel,socfpga-agilex5-socdk-modular for the Agilex5 mod board
 	- Add intel,socfpga-agilex-emmc for the Agilex eMMC daughter board
 	- Move entries in intel,socfpga.yaml into altera.yaml
 	- Add syscon as a fallback for sys-mgr
 
 - Add dma-cohrerent property for Agilex5 NAND and DMA
 - Add support for the Agilex5 modular board
 - Add IOMMUS property for ethernet nodes for Agilex5
 - Use lowercase hex for dts files
 - Add #address-cells and #size-cells for sram
 - Fix dtbs_check warning for fpga-region
 - Move dma controller node for Agilex5 under simple-bus
 - Add support for the Agilex eMMC daughter board
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Merge tag 'socfpga_dts_updates_for_v6.20_v3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt

SoCFPGA DTS updates for v6.20, version 3
- dt-bindings updates:
	- Add intel,socfpga-agilex5-socdk-modular for the Agilex5 mod board
	- Add intel,socfpga-agilex-emmc for the Agilex eMMC daughter board
	- Move entries in intel,socfpga.yaml into altera.yaml
	- Add syscon as a fallback for sys-mgr

- Add dma-cohrerent property for Agilex5 NAND and DMA
- Add support for the Agilex5 modular board
- Add IOMMUS property for ethernet nodes for Agilex5
- Use lowercase hex for dts files
- Add #address-cells and #size-cells for sram
- Fix dtbs_check warning for fpga-region
- Move dma controller node for Agilex5 under simple-bus
- Add support for the Agilex eMMC daughter board

* tag 'socfpga_dts_updates_for_v6.20_v3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  dt-bindings: intel: Add Agilex eMMC support
  arm64: dts: socfpga: agilex: add emmc support
  arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node
  ARM: dts: socfpga: fix dtbs_check warning for fpga-region
  ARM: dts: socfpga: add #address-cells and #size-cells for sram node
  dt-bindings: altera: document syscon as fallback for sys-mgr
  arm64: dts: altera: Use lowercase hex
  dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml
  arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes
  arm64: dts: socfpga: agilex5: add support for modular board
  dt-bindings: intel: Add Agilex5 SoCFPGA modular board
  arm64: dts: socfpga: agilex5: Add dma-coherent property

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2026-02-04 08:39:08 +01:00
commit f51d34065d
14 changed files with 335 additions and 108 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
Documentation/devicetree/bindings/arm/altera.yaml
View File

@ -9,6 +9,9 @@ title: Altera's SoCFPGA platform
maintainers:
- Dinh Nguyen <dinguyen@kernel.org>
description:
Altera/Intel boards with ARM 32/64 bits cores
properties:
$nodename:
const: "/"
@ -81,6 +84,30 @@ properties:
- altr,socfpga-stratix10-swvp
- const: altr,socfpga-stratix10
- description: AgileX boards
items:
- enum:
- intel,n5x-socdk
- intel,socfpga-agilex-n6000
- intel,socfpga-agilex-socdk
- intel,socfpga-agilex-socdk-emmc
- const: intel,socfpga-agilex
- description: Agilex3 boards
items:
- enum:
- intel,socfpga-agilex3-socdk
- const: intel,socfpga-agilex3
- const: intel,socfpga-agilex5
- description: Agilex5 boards
items:
- enum:
- intel,socfpga-agilex5-socdk
- intel,socfpga-agilex5-socdk-013b
- intel,socfpga-agilex5-socdk-nand
- const: intel,socfpga-agilex5
- description: SoCFPGA VT
items:
- const: altr,socfpga-vt

40
Documentation/devicetree/bindings/arm/intel,socfpga.yaml
View File

@ -1,40 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/intel,socfpga.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel SoCFPGA platform
maintainers:
- Dinh Nguyen <dinguyen@kernel.org>
properties:
$nodename:
const: "/"
compatible:
oneOf:
- description: AgileX boards
items:
- enum:
- intel,n5x-socdk
- intel,socfpga-agilex-n6000
- intel,socfpga-agilex-socdk
- const: intel,socfpga-agilex
- description: Agilex3 boards
items:
- enum:
- intel,socfpga-agilex3-socdk
- const: intel,socfpga-agilex3
- const: intel,socfpga-agilex5
- description: Agilex5 boards
items:
- enum:
- intel,socfpga-agilex5-socdk
- intel,socfpga-agilex5-socdk-013b
- intel,socfpga-agilex5-socdk-nand
- const: intel,socfpga-agilex5
additionalProperties: true
...

6
Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml
View File

@ -13,7 +13,9 @@ properties:
compatible:
oneOf:
- description: Cyclone5/Arria5/Arria10
const: altr,sys-mgr
items:
- const: altr,sys-mgr
- const: syscon
- description: Stratix10 SoC
items:
- const: altr,sys-mgr-s10
@ -45,7 +47,7 @@ additionalProperties: false
examples:
- |
sysmgr@ffd08000 {
compatible = "altr,sys-mgr";
compatible = "altr,sys-mgr", "syscon";
reg = <0xffd08000 0x1000>;
cpu1-start-addr = <0xffd080c4>;
};

6
arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
View File

@ -87,12 +87,13 @@ pdma: pdma@ffe01000 {
};
};
base_fpga_region {
base_fpga_region: fpga-region {
compatible = "fpga-region";
fpga-mgr = <&fpgamgr0>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
can0: can@ffc00000 {
@ -785,6 +786,9 @@ nand0: nand-controller@ff900000 {
ocram: sram@ffff0000 {
compatible = "mmio-sram";
reg = <0xffff0000 0x10000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
qspi: spi@ff705000 {

6
arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi
View File

@ -80,12 +80,13 @@ pdma: pdma@ffda1000 {
};
};
base_fpga_region {
base_fpga_region: fpga-region {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "fpga-region";
fpga-mgr = <&fpga_mgr>;
ranges;
};
clkmgr@ffd04000 {
@ -686,6 +687,9 @@ nand: nand-controller@ffb90000 {
ocram: sram@ffe00000 {
compatible = "mmio-sram";
reg = <0xffe00000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
eccmgr: eccmgr {

2
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
View File

@ -382,7 +382,7 @@ pdma: dma-controller@ffda0000 {
pinctrl0: pinctrl@ffd13000 {
compatible = "pinctrl-single";
reg = <0xffd13000 0xA0>;
reg = <0xffd13000 0xa0>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;

2
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
View File

@ -192,7 +192,7 @@ qspi_boot: partition@0 {
root: partition@4200000 {
label = "Root Filesystem - UBIFS";
reg = <0x04200000 0x0BE00000>;
reg = <0x04200000 0x0be00000>;
};
};
};

4
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
View File

@ -174,12 +174,12 @@ partitions {
qspi_boot: partition@0 {
label = "Boot and fpga data";
reg = <0x0 0x03FE0000>;
reg = <0x0 0x03fe0000>;
};
qspi_rootfs: partition@3fe0000 {
label = "Root Filesystem - JFFS2";
reg = <0x03FE0000 0x0C020000>;
reg = <0x03fe0000 0x0c020000>;
};
};
};

2
arch/arm64/boot/dts/intel/Makefile
View File

@ -1,10 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
socfpga_agilex_socdk.dtb \
socfpga_agilex_socdk_emmc.dtb \
socfpga_agilex_socdk_nand.dtb \
socfpga_agilex3_socdk.dtb \
socfpga_agilex5_socdk.dtb \
socfpga_agilex5_socdk_013b.dtb \
socfpga_agilex5_socdk_modular.dtb \
socfpga_agilex5_socdk_nand.dtb \
socfpga_n5x_socdk.dtb
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb

128
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
View File

@ -312,6 +312,7 @@ nand: nand-controller@10b80000 {
clock-names = "nf_clk";
cdns,board-delay-ps = <4830>;
iommus = <&smmu 4>;
dma-coherent;
status = "disabled";
};
@ -323,40 +324,50 @@ ocram: sram@0 {
#size-cells = <1>;
};
dmac0: dma-controller@10db0000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x10db0000 0x500>;
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
<&clkmgr AGILEX5_L4_MP_CLK>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
dma-channels = <4>;
snps,dma-masters = <1>;
snps,data-width = <2>;
snps,block-size = <32767 32767 32767 32767>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <8>;
iommus = <&smmu 8>;
};
dma: dma-bus@10db0000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <2>;
ranges = <0x00 0x10db0000 0x00 0x20000>;
dma-ranges = <0x00 0x00 0x100 0x00>;
dmac1: dma-controller@10dc0000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x10dc0000 0x500>;
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
<&clkmgr AGILEX5_L4_MP_CLK>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
dma-channels = <4>;
snps,dma-masters = <1>;
snps,data-width = <2>;
snps,block-size = <32767 32767 32767 32767>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <8>;
iommus = <&smmu 9>;
dmac0: dma-controller@0 {
compatible = "altr,agilex5-axi-dma",
"snps,axi-dma-1.01a";
reg = <0x0 0x0 0x500>;
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
<&clkmgr AGILEX5_L4_MP_CLK>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
dma-channels = <4>;
snps,dma-masters = <1>;
snps,data-width = <2>;
snps,block-size = <32767 32767 32767 32767>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <8>;
iommus = <&smmu 8>;
};
dmac1: dma-controller@10000 {
compatible = "altr,agilex5-axi-dma",
"snps,axi-dma-1.01a";
reg = <0x10000 0x0 0x500>;
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
<&clkmgr AGILEX5_L4_MP_CLK>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
dma-channels = <4>;
snps,dma-masters = <1>;
snps,data-width = <2>;
snps,block-size = <32767 32767 32767 32767>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <8>;
iommus = <&smmu 9>;
};
};
rst: rstmgr@10d11000 {
@ -565,6 +576,7 @@ gmac0: ethernet@10810000 {
snps,tso;
altr,sysmgr-syscon = <&sysmgr 0x44 0>;
snps,clk-csr = <0>;
iommus = <&smmu 1>;
status = "disabled";
stmmac_axi_emac0_setup: stmmac-axi-config {
@ -618,31 +630,31 @@ queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,weight = <0x0A>;
snps,weight = <0x0a>;
snps,dcb-algorithm;
};
queue2 {
snps,weight = <0x0B>;
snps,weight = <0x0b>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue3 {
snps,weight = <0x0C>;
snps,weight = <0x0c>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue4 {
snps,weight = <0x0D>;
snps,weight = <0x0d>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue5 {
snps,weight = <0x0E>;
snps,weight = <0x0e>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue6 {
snps,weight = <0x0F>;
snps,weight = <0x0f>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
@ -677,6 +689,7 @@ gmac1: ethernet@10820000 {
snps,tso;
altr,sysmgr-syscon = <&sysmgr 0x48 0>;
snps,clk-csr = <0>;
iommus = <&smmu 2>;
status = "disabled";
stmmac_axi_emac1_setup: stmmac-axi-config {
@ -730,31 +743,31 @@ queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,weight = <0x0A>;
snps,weight = <0x0a>;
snps,dcb-algorithm;
};
queue2 {
snps,weight = <0x0B>;
snps,weight = <0x0b>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue3 {
snps,weight = <0x0C>;
snps,weight = <0x0c>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue4 {
snps,weight = <0x0D>;
snps,weight = <0x0d>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue5 {
snps,weight = <0x0E>;
snps,weight = <0x0e>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue6 {
snps,weight = <0x0F>;
snps,weight = <0x0f>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
@ -789,6 +802,7 @@ gmac2: ethernet@10830000 {
snps,tso;
altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
snps,clk-csr = <0>;
iommus = <&smmu 3>;
status = "disabled";
stmmac_axi_emac2_setup: stmmac-axi-config {
@ -842,31 +856,31 @@ queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,weight = <0x0A>;
snps,weight = <0x0a>;
snps,dcb-algorithm;
};
queue2 {
snps,weight = <0x0B>;
snps,weight = <0x0b>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue3 {
snps,weight = <0x0C>;
snps,weight = <0x0c>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue4 {
snps,weight = <0x0D>;
snps,weight = <0x0d>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue5 {
snps,weight = <0x0E>;
snps,weight = <0x0e>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue6 {
snps,weight = <0x0F>;
snps,weight = <0x0f>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
@ -912,24 +926,24 @@ pmu0_tbu2: pmu@16082000 {
pmu0_tbu3: pmu@160a2000 {
compatible = "arm,smmu-v3-pmcg";
reg = <0x160A2000 0x1000>,
<0x160B2000 0x1000>;
reg = <0x160a2000 0x1000>,
<0x160b2000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
};
pmu0_tbu4: pmu@160c2000 {
compatible = "arm,smmu-v3-pmcg";
reg = <0x160C2000 0x1000>,
<0x160D2000 0x1000>;
reg = <0x160c2000 0x1000>,
<0x160d2000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
};
pmu0_tbu5: pmu@160e2000 {
compatible = "arm,smmu-v3-pmcg";
reg = <0x160E2000 0x1000>,
<0x160F2000 0x1000>;
reg = <0x160e2000 0x1000>,
<0x160f2000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
};

109
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts Normal file
View File

@ -0,0 +1,109 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2025, Altera Corporation
*/
#include "socfpga_agilex5.dtsi"
/ {
model = "SoCFPGA Agilex5 SoCDK - Modular development kit";
compatible = "intel,socfpga-agilex5-socdk-modular", "intel,socfpga-agilex5";
aliases {
serial0 = &uart0;
ethernet2 = &gmac2;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led0 {
label = "hps_led0";
gpios = <&porta 0x0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0x0 0x80000000 0x0 0x0>;
};
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gmac2 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&emac2_phy0>;
max-frame-size = <9000>;
mdio0 {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
emac2_phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
&osc1 {
clock-frequency = <25000000>;
};
&qspi {
status = "okay";
flash@0 {
compatible = "micron,mt25qu02g", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,read-delay = <2>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
qspi_boot: partition@0 {
label = "u-boot";
reg = <0x0 0x04200000>;
};
root: partition@4200000 {
label = "root";
reg = <0x04200000 0x0be00000>;
};
};
};
};
&smmu {
status = "okay";
};
&uart0 {
status = "okay";
};
&watchdog0 {
status = "okay";
};

2
arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
View File

@ -131,7 +131,7 @@ qspi_boot: partition@0 {
root: partition@4200000 {
label = "Root Filesystem - UBIFS";
reg = <0x04200000 0x0BE00000>;
reg = <0x04200000 0x0be00000>;
};
};
};

105
arch/arm64/boot/dts/intel/socfpga_agilex_socdk_emmc.dts Normal file
View File

@ -0,0 +1,105 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2026, Altera Corporation
*/
#include "socfpga_agilex.dtsi"
/ {
model = "SoCFPGA Agilex SoCDK eMMC daughter board";
compatible = "intel,socfpga-agilex-socdk-emmc", "intel,socfpga-agilex";
aliases {
serial0 = &uart0;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
ethernet2 = &gmac2;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led0 {
label = "hps_led0";
gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
};
led1 {
label = "hps_led1";
gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
};
led2 {
label = "hps_led2";
gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0x80000000 0 0>;
};
};
&gpio1 {
status = "okay";
};
&gmac2 {
status = "okay";
/* PHY delays is configured via skew properties */
phy-mode = "rgmii";
phy-handle = <&phy0>;
max-frame-size = <9000>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@4 {
reg = <4>;
txd0-skew-ps = <0>; /* -420ps */
txd1-skew-ps = <0>; /* -420ps */
txd2-skew-ps = <0>; /* -420ps */
txd3-skew-ps = <0>; /* -420ps */
rxd0-skew-ps = <420>; /* 0ps */
rxd1-skew-ps = <420>; /* 0ps */
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
txen-skew-ps = <0>; /* -420ps */
txc-skew-ps = <900>; /* 0ps */
rxdv-skew-ps = <420>; /* 0ps */
rxc-skew-ps = <1680>; /* 780ps */
};
};
};
&mmc {
status = "okay";
cap-mmc-highspeed;
broken-cd;
bus-width = <4>;
clk-phase-sd-hs = <0>, <135>;
};
&osc1 {
clock-frequency = <25000000>;
};
&uart0 {
status = "okay";
};
&usb0 {
status = "okay";
disable-over-current;
};
&watchdog0 {
status = "okay";
};

4
arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
View File

@ -103,12 +103,12 @@ partitions {
qspi_boot: partition@0 {
label = "Boot and fpga data";
reg = <0x0 0x03FE0000>;
reg = <0x0 0x03fe0000>;
};
qspi_rootfs: partition@3fe0000 {
label = "Root Filesystem - JFFS2";
reg = <0x03FE0000 0x0C020000>;
reg = <0x03fe0000 0x0c020000>;
};
};
};