Commit Graph

1122469 Commits

Author SHA1 Message Date
Arnd Bergmann
07d0db46b3 i.MX device tree change for 6.1
- A series from Alexander Stein to add missing properties for i.MX6 SRAM.
 - Drop 'interrupts' property when 'interrupts-extended' is present. This
   fixes a dtbs_check warning with i.MX6 DT.
 - Update device trees to use generic name 'dma-controller' for SDMA.
 - A set of changes from Krzysztof Kozlowski to align SPI, LED and
   gpio-keys node name with dtschema.
 - A series of indentation and white-space cleanups from Marcel Ziswiler
   to address various checkpatch warnings.
 - Add DDR pinmux defines to VF610 DT header.
 - A couple of changes from Peng Fan to update clock-names and add IPG
   clock for i.MX7ULP LPI2C devices.
 - Improve device tree structure for Kontron i.MX6UL/ULL based boards.
 - A series of changes from Tim Harvey to add CAN regulator for Gateworks
   i.MX6QDL boards.
 - Various small and random board specific updates.
 -----BEGIN PGP SIGNATURE-----
 
 iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmMmkqkUHHNoYXduZ3Vv
 QGtlcm5lbC5vcmcACgkQUFdYWoewfM5jrAf+K3D9RtMWlGY1zrqv6QLWgBbeNaBt
 wtICvLyaaypcPqZ/WzgfgMgJf9tUwDzkrzewyRqG4aHBQvY0xOlwvUFH/OA2C4mA
 K0/FYR6GK4rIlZpOW1Rkj3K0U0GrtxUsF9uXLFhQShJWWVn+gpjZmcZ3hEVwRyIR
 eNEKsMmwV0UZhT1JZYZ/U+sQD8yfaNPLLVM+doLwcavQavNGQyDRLdpAZ6AuMANz
 SckcGC4tI3mkPsTBweshemSDe14XILrnDgei1429AfLd+vb48l9FPUF5/oOKJRt7
 Zb1uQmXfCwyUJx7pU3tJZBUHAAGqsupniYtpxYxH8PL46lSulmSDpnMLyA==
 =wloQ
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMtum4ACgkQmmx57+YA
 GNnNQg/+OF8MWe9D2KCAacvr+5hw2L2qAl0UTXsMEWOrAsv8kBpt9MRcqRPFF+Ag
 4MzMrOL7m30R58aJBks0guKyk6dRMX+Qr6Z/H8JIKIjg43nANeysqK/mXbXWtXkN
 uwUsZCDV3vcyaw6xrxOXG1UX3Y7wedD/x77XDzJG8pPYU4Bg85h1ZfsXjhqgx/QN
 7vKDH4QwRxNzKQBwF04aaDjyQHZS7mXGpieLt3GtY+OdjXM+BFDou5hgITSWfnd4
 u+LzCy0u1j3AMImV5cCiZdCpix68/ExJdSPATL/He6p/cqFXxYpqk+zLIV3p9whn
 jgWBst3XKVBFbGU0Omb4sU3YvxE8oRuUNsKcGqS7/ycF8nZwjvSQHoiRBx9P4qkC
 X9uKe4sy6GzrR8altz6MlfhmVIeGg6ureirUWI/jJer3+DYDoXXruBFlkWDUuetV
 FmQ6E2MNwRBg0OvB6+/0ak6ApPiAtp+zj4dqtmYgcYxaR7tNZcY0AGjTGd+5BMA8
 6lSDAfRxAsKYWNu+3xA8Cdjo4+N+tEweHQNX6RDkWMii0yeR4T2zQYSa/gl/xhaa
 OSUzGzod8C6KJY/Yb2vZMo+Lsum/dgA9G53v2N1S0WTIK4FNcibgBXoYA9i5RRJW
 kSDfudU4RpBjDwDHj6uxWn/WwuHqkzOAtUWvx3cX8c+I8cLl6/M=
 =7v6C
 -----END PGP SIGNATURE-----

Merge tag 'imx-dt-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX device tree change for 6.1

- A series from Alexander Stein to add missing properties for i.MX6 SRAM.
- Drop 'interrupts' property when 'interrupts-extended' is present. This
  fixes a dtbs_check warning with i.MX6 DT.
- Update device trees to use generic name 'dma-controller' for SDMA.
- A set of changes from Krzysztof Kozlowski to align SPI, LED and
  gpio-keys node name with dtschema.
- A series of indentation and white-space cleanups from Marcel Ziswiler
  to address various checkpatch warnings.
- Add DDR pinmux defines to VF610 DT header.
- A couple of changes from Peng Fan to update clock-names and add IPG
  clock for i.MX7ULP LPI2C devices.
- Improve device tree structure for Kontron i.MX6UL/ULL based boards.
- A series of changes from Tim Harvey to add CAN regulator for Gateworks
  i.MX6QDL boards.
- Various small and random board specific updates.

* tag 'imx-dt-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (40 commits)
  ARM: dts: imx6qdl-gw54xx: add CAN regulator
  ARM: dts: imx6qdl-gw53xx: add CAN regulator
  ARM: dts: imx6qdl-gw52xx: add CAN regulator
  ARM: dts: imx: update sdma node name format
  ARM: dts: imx6: skov: migrate to resistive-adc-touch
  ARM: dts: imx6sx-udoo-neo: don't use multiple blank lines
  ARM: dts: imx6sl: use tabs for code indent
  ARM: dts: imx6sx: add missing properties for sram
  ARM: dts: imx6sll: add missing properties for sram
  ARM: dts: imx6sl: add missing properties for sram
  ARM: dts: imx6qp: add missing properties for sram
  ARM: dts: imx6dl: add missing properties for sram
  ARM: dts: imx6q: add missing properties for sram
  ARM: dts: imx7ulp: Add IPG clock for lpi2c
  ARM: dts: imx7ulp: update the LPI2C clock-names
  ARM: dts: vf610: ddr pinmux
  ARM: dts: imx6qdl-dhcom: Move IPU iomux node from PDK2 to SoM file
  ARM: dts: imx6ul-kontron: Add imx6ull-kontron-bl to Makefile
  ARM: dts: imx6ul-kontron: Simplify devicetree structure
  ARM: dts: vf610: align SPI node name with dtschema
  ...

Link: https://lore.kernel.org/r/20220918092806.2152700-3-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-23 15:53:50 +02:00
Arnd Bergmann
2b14d7da65 i.MX DT bindings for 6.1:
- Add compatible for new boards: Kontron BL i.MX8MM OSM-S, MSC
   SM2S-IMX8PLUS SoM and SM2-MB-EP1 Carrier, i.MX8M Mini Gateworks
   GW7904 board, i.MX8DXL EVK Board.
 - Add add interconnect property for i.MX8MP various blk-ctrl devices.
 - Add i.MX8MP HDMI HDCP and HRV power domain DT IDs.
 - Add bindings for i.MX93 SRC and MEDIAMIX blk-ctrl.
 - A minor style fix on i.MX8MM clock binding header.
 -----BEGIN PGP SIGNATURE-----
 
 iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmMlhS4UHHNoYXduZ3Vv
 QGtlcm5lbC5vcmcACgkQUFdYWoewfM6RGgf9EYZWreK87zuUb3F0ARa6Ac1uYS9R
 mWBz6WaVm5SQV/bIr6oSql7iIyrojAVb7FqusZ/d/YbP3WlhcCT5l7VhjjSE0LNi
 IZsyfl0fWEg+ro8MtwY/VnEcWH01eAgbqo6Hbu3oGKJqU5lwmhKD5gT1ctbtGWOA
 v6BlfB5iT/D+IexTeYz/NS2h6MZgVfLLVki82qjyokrUagVOmoPLjZhAlqJKJrHT
 khD1rfdeq56vGprd6juSvFQcNh5SvoKj8TqMlRSOA4peSPLChRSmRyRAYiNN6v8d
 HhHAeRc3XhDQlVxt9zWar981JxDDXHWooo2NIeNKB0bYiKjBGJtEeJ27qw==
 =7xMQ
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMtubAACgkQmmx57+YA
 GNk4IxAArqCHIy7vCDjx+SiQV8aiJNQzTlPIv6CRnnh/GpbAk0VwOFzd1q2zQPZl
 3RJQF/r9y76V/1Nqvam3Bldly9lHl0BLXCSdJjJN7gDJ2HZLJFjLZr9PPd8lrq/F
 1xCej6mDB1K/FgiQNVBhjjI+uw05PPF7eZgfpdgAYiWYXiSogk7IdR1LgiT5KzbB
 QSl19/BcrXc7G+wve5sFsJzCozQkn2aQo2phsYgbUZ5u1gTwLN3Y2Arq6iUjF0iR
 opnqEuWalBTUYvGZonrvBwg/BW2z9uiTJ1WUEIKSst4W7I2qYMSFG73KLR/KJela
 qflPNJ9y7Qy4TzQ7e3vWouXzIVZVfbp8IiIoWatFd907ii1omhnVkvSe/cVIpPvz
 eKlPVXQB7QKEH1ITmDIUy9dzYlZYbVKyx76E478yrRnzXDFIXvTbooqHZ2eiU2aY
 dSIttucqL/yeJZ28EZ9ZhMxLOYPjKkqwv+0DsmTwWSpEHEJAw0gGyOCPrmCdGdWr
 bK6CSKntPWiXgVMNstdgVdlyRJJr1udxUmYq5h2EBmE+bHBTkTf95ys4isxygXk7
 edK+oc7iUeyVwQm4o7hnVuWEpLP97BCDaFV7Sa9+RkqJ2iKdLaVPD/VARjl/ypgZ
 u/DWpPFNOzabCPj0SD5osT/arXisEfatGTIgwO23swiJfDJlpiU=
 =D4U3
 -----END PGP SIGNATURE-----

Merge tag 'imx-bindings-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX DT bindings for 6.1:

- Add compatible for new boards: Kontron BL i.MX8MM OSM-S, MSC
  SM2S-IMX8PLUS SoM and SM2-MB-EP1 Carrier, i.MX8M Mini Gateworks
  GW7904 board, i.MX8DXL EVK Board.
- Add add interconnect property for i.MX8MP various blk-ctrl devices.
- Add i.MX8MP HDMI HDCP and HRV power domain DT IDs.
- Add bindings for i.MX93 SRC and MEDIAMIX blk-ctrl.
- A minor style fix on i.MX8MM clock binding header.

* tag 'imx-bindings-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  dt-bindings: arm: imx: update fsl.yaml for imx8dxl
  dt-bindings: firmware: add missing resource IDs for imx8dxl
  dt-bindings: arm: Add i.MX8M Mini Gateworks GW7904 board
  dt-bindings: soc: add i.MX93 mediamix blk ctrl
  dt-bindings: soc: add i.MX93 SRC
  dt-bindings: mfd: syscon: Add i.MX93 blk ctrl system registers
  dt-bindings: arm: fsl: Add MSC SM2S-IMX8PLUS SoM and SM2-MB-EP1 Carrier
  dt-bindings: arm: fsl: Add Kontron BL i.MX8MM OSM-S board
  dt-bindings: arm: fsl: Rename compatibles for Kontron i.MX8MM SoM/board
  dt-bindings: soc: imx: add i.MX8MP vpu blk ctrl
  dt-bindings: soc: imx: add interconnect property for i.MX8MM vpu blk ctrl
  dt-bindings: soc: imx: drop minItems for i.MX8MM vpu blk ctrl
  dt-bindings: power: imx8mp-power: add HDMI HDCP/HRV
  dt-bindings: arm: fsl: imx6ul-kontron: Update bindings
  dt-bindings: clk: imx8mm: don't use multiple blank lines
  dt-bindings: soc: imx: add interconnect property for i.MX8MP hsio blk ctrl
  dt-bindings: soc: imx: add interconnect property for i.MX8MP hdmi blk ctrl
  dt-bindings: soc: imx: add interconnect property for i.MX8MP media blk ctrl

Link: https://lore.kernel.org/r/20220918092806.2152700-1-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-23 15:50:40 +02:00
Arnd Bergmann
f58ec42950 arm64: tegra: Device tree changes for v6.1-rc1
These changes enable PCI, Ethernet and HDA support on Jetson AGX Orin.
 DMA support is enabled for I2C on a number of SoC generations and the
 Google Pixel C (a.k.a. Smaug) device receives Bluetooth and Wi-Fi
 support.
 
 Other than that this also contains some minor cleanups and fixes.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmMkS+cTHHRyZWRpbmdA
 bnZpZGlhLmNvbQAKCRDdI6zXfz6zoSVxEACS52ng2EWzrY27C1nZkka1+1bt9BRs
 uKLBrA8BuwGNtyLHirN8TbEaSlg3/dv81lQDVBTYXtxdwudLL9lY2PGdgJaHM1FA
 bRKR2eZz6AQdvnQi348mbXRVEG7yWrZi9UCWCQwQ5Q/b1g0k4GJQU9U80acHtRsa
 XW6Wj9rlaUayxAMRYkbb+2GecoKk4zrHDqtHrhXJjHurGdzhvNdKZcIWzcXzxHal
 jWN81G8FNqf19S1BTkOsV3nwlqwVb9zA02ZAia/HYKIFR9Tsn0s6GlXaDo4F7bB/
 yrM6dfe+22ZUd+ivpjrHLnefAM//grvFEBdmuK/tIdnasYa70U6PnOoRhoob8orH
 yrJkxgzdWslD2BIDmXKiRvzjoLe8/0nTjMK1drNg6SRRYDXBx0b5atDSPcpTsmcu
 nVW+6w7ISHJvQ2FqvTwWXGyw8vjMIsba0vKO5z9E/Xnboy6qFTb7y7032MrHhk7i
 HIAHfHQTMEwPFJQnVXZquC0X7lKrY3hKlyjsGcdtqqU0UGyDwU++dtdugF2HP6Na
 D7EZkBf+ibXWmIwSAAJRjXf/hbYLIVZHEAX7hQlESHZBI9ckLwxMVCKgwDkU8zus
 ZHhUuBQ/dmrEh+hgkYmkIMcGTJSBYtnvMVEB0K/oIB9+nbbuZ4mQ8vu38wrsQa6+
 X92eUMCBRB3N7g==
 =hMuy
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMtuBAACgkQmmx57+YA
 GNmaRxAAhAx+cHVY0rOROQ1bEFhu1C4GYrrcqwkgqsCFLNSU2OMMdSaD700J5RbO
 j1ghhXR9jispWZIc6WyjscmClDHcwq/fMjqHfl2Cru243RXSO+LL3Ut/JiBLIBpd
 Kj0/14XQzZc43PW3Jnz2SLMSU3recRt8ZMYnl3OxHzJPrXWedYKI2J6uSsPb32fG
 n6svKejHaqiFFtsHQhjlqox370wSocArhqh238iUqncOTj23lycO3VZ1Rwk/h8G0
 YdAGeeih0NGM2eah1ntYcdclpbILI9Nsme/xD4yCyxByVB5WqwLOkSqyppdRd2UY
 KG1Z95UsaNGBZTc/1F7FUGNCUiv/zHys8KysnibhXQniAvoG/sz4E8bFpGSpa76o
 hISOFb82q1PPDxUXIWq8deyrGtCZyUkgSEh0tNsuNafec2iOl0/ERvZyTD+6PKlT
 xbmtZoT1Wf69s6hh08pzS5cO5FztHXudA754jIRZUFbRquDNoBNDZHa8APKpGxSI
 e0+SS1kRgBHgrMXNOJH0UDQtkt1fdbDJWCHvXx1ki/1BjedyQZdkU75D5epEyTLn
 F1XTcGbtF5WlgC0vQCL8SEhIA6nqotkZHRSfs0E0+9JadRsH9f9xWgLG+CqGsPzM
 /FWS4UnijuiIj5r1lcm0xuLO524tGdGuDdAIBkymehZkpDF1Bjc=
 =fOSZ
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-6.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

arm64: tegra: Device tree changes for v6.1-rc1

These changes enable PCI, Ethernet and HDA support on Jetson AGX Orin.
DMA support is enabled for I2C on a number of SoC generations and the
Google Pixel C (a.k.a. Smaug) device receives Bluetooth and Wi-Fi
support.

Other than that this also contains some minor cleanups and fixes.

* tag 'tegra-for-6.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Add GPCDMA support for Tegra I2C
  arm64: tegra: Add iommus for HDA on Tegra234
  arm64: tegra: Enable HDA node for Jetson AGX Orin
  arm64: tegra: Add context isolation domains on Tegra234
  arm64: tegra: Fixup iommu-map property formatting
  arm64: dts: tegra: smaug: Add Wi-Fi node
  arm64: dts: tegra: smaug: Add Bluetooth node
  arm64: tegra: Enable MGBE on Jetson AGX Orin Developer Kit
  arm64: tegra: Add MGBE nodes on Tegra234
  arm64: tegra: Fix up compatible for Tegra234 GPCDMA
  arm64: tegra: Enable PCIe slots in P3737-0000 board
  arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT
  arm64: tegra: Add regulators required for PCIe

Link: https://lore.kernel.org/r/20220916101957.1635854-5-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-23 15:43:44 +02:00
Arnd Bergmann
195571f342 dt-bindings: Changes for v6.1-rc1
Adds device tree bindings for the MGBE found on Tegra234 SoCs, as well
 as stream IDs for the shared host1x context devices.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmMkSw8THHRyZWRpbmdA
 bnZpZGlhLmNvbQAKCRDdI6zXfz6zocJTEACYpoTDx2T2lLMv8iGCL0wWDJrOU2/Y
 N0plnJi+kJKXwwGAjC95A5Lbm+7PQeAgeH/Ai1NxBu4LCL83QHN0Zzc25g9MdMFa
 HH4g030V14TEM8Yj0WCXAVtO+y6OsAX4ycwRA9OJEz+c+lKPIbAiXe6vibVFQz/f
 yTeumGT0iOI8efqzYpP0x7gSHUsrY0i+4+Td4aqSapE1/93FCEzvUAz/vj/2OGGe
 fXOXVnVVk9IWuhTw61Sum9dborq3g4SHAAldygffC6Ivx1/3AkrF5fvFYYopZrSf
 h2orSrDg4S3kqhF6mwPksBFLoWChoWQB/t620kuXuUYEVFV0mTqdgnMbv/w3CYPC
 JsiNfKrtWND53LMh2UOrJjRLnTtxZCOLXalyovJkkoccaKi2BxiRAHryj/sogoxW
 GRinz48bxnF58MQ1v4BBbUrntzf2SSF7d11zkQg1MQ1qljEZJV0piZDPDyLLyWME
 xOggT8DSfwJWG+nlA51+UCjr4Qvv4u6gkOXo7lbv3uOiVHHq/aMqeJKCkOpySqbk
 J0kxURvRmNRXvMf+jsDsyk3L6EhSElfwF9UKB4vdjI9O+wj/rs2C2C024lOWHI14
 ew09v6UnBzGfOoq7YmBl0RP6B6HcCWFfKaZSEJ+bS9pzPPT54iZq+e853ZANG9GO
 oaCO0XVSFYnzXQ==
 =fXO9
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMtt9QACgkQmmx57+YA
 GNmUUg//U5Bdddza9xHN3uOoJJRTIuciMK1KC8EGlW7RUGkJV3lK+8Qmb/GzbZ8e
 xSwhNSgP9cyJ5c2khU+IT+dNQtvBpnAsezLWccdEbhx48OOV3D+4OxQDJKtX/z27
 FMXaryY7TLKfLR1utlCcZ8+l5fV/8fiO/Py18hM2TUv86v8IHSbpsyGiDcsywi3N
 Fa8Vlz+Vbr2N4kfe3FOUQZUw1lTEjh9negDKXMQJYE0I5IyHkEqIBNjJbP6mtWfg
 i9G0sEvC2LjVF1KnoflNmpFjXzLWoiEasY6GEv9FsVhYfTgvLwfnsHH3/l2Dv+da
 v5gGrqQGmtr7jZeKU2Zz4oKvg91e098JCaUUJjLirpA0uS16kbt5v9Uof27MXY8b
 /htgFQgjMPx+Jn1K9tYxBk+WnmtMI40O5MSj+QG2uL1x6Q/QYFSL346YmLDDJvL0
 6c3J1rlh/VlMI3EzycFl2CAFEBpYzBP6ERFw/2BtkEfhGUEhBaX4wG6uKevNDOo8
 HJsOcIJKNCgQk88nGB+ItqDbxfwaa2UQnXufWPdV8Rty1ysfvlU60CWR7SK8NAeX
 gcPdqH9Z1B8doYGmrtj9HKCdtpo0qyYI3Ruz/0pBQgFiVoO0FltN/d6fItf8aJKf
 yHUigmWiQ4FKM3sjl4H5rpWqDv3Q+oGPQmfMoE5jVQgp6tL0b+o=
 =PY4Y
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-6.1-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

dt-bindings: Changes for v6.1-rc1

Adds device tree bindings for the MGBE found on Tegra234 SoCs, as well
as stream IDs for the shared host1x context devices.

* tag 'tegra-for-6.1-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: Add Host1x context stream IDs on Tegra234
  dt-bindings: net: Add Tegra234 MGBE

Link: https://lore.kernel.org/r/20220916101957.1635854-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-23 15:42:44 +02:00
Arnd Bergmann
2fef9856dc AT91 DT for v6.1 #2
It contains:
 - new SAMA5D3 based board, namely SAMA5D3-EDS
 - adjustments to pass the DT binding validations
 - disable AES on some LAN966 based boards as they are reserverd by
   secure OS
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYIAB0WIQTsZ8eserC1pmhwqDmejrg/N2X7/QUCYyQybAAKCRCejrg/N2X7
 /R+wAQCDcL8RVW4opVAOjDkMOCnVxq8M+pjx+jVOnIPIRsGnNwEAxZ9sX5gP8HM3
 ygUF/qoc3bUxXAN/YH6HfWIpYszV8wY=
 =9Ge/
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMmC7gACgkQmmx57+YA
 GNm/8hAAhp9bs85oOISO8dZCx3rQklj4FIKxUQD/cjdqeynjRZ7kjONlC8BGHE4U
 QKCzLwEHAdUAdrDv3KWu7vW+Fub+yrfJH58SV7Z46NOyu2jy0i6cZFDTQXXH6WCr
 ipkj0wRT0M519HOBGr1n8a9JX/WHAcmHcA54ADZ6aQz02mH9GZ73T0MCe8ySAPpe
 SWrv1a3QowY9UvabpNOPtLabLqJLeRJTIcKRc3Nl/3DObTT0wph78mNp0+YlarmE
 gw218a7tgRxa5j0KgHfStUzg+xHiWnwLPKwoQ9pMogByzErJICpO++t/e00zFAB/
 IAsHyKwGXh+oWXA+K47CI7NgXtlLLN9PpR1CcJtYmXFbSxSZEAyI6JqYXMf6m3l5
 4Ig1LhxIBUjxylbCjha0dBE/zdENKwEp980O1lIZpLH+XdPKUSYmQIUCGloP0tOt
 EAdxwR+z1fw8RY687SYHCyLWOQBeUl7yfTkAhA/YrRXyTQvbhs8zQszZCkA8jFTm
 AJGH8f3dJYBRl0RoVJQxP2YEZ15y7h118piuP1U/Q3bwNLGx8AacQNg+cBg7qowT
 YM/iybDQ+RZPMxUVHNtjU0ZDhB7iqAgbK7dNJW35c4Tj/BM5/qmf1s7G9ZDmJm6D
 IkNCtPNbKJ8J9P/xG0pi1XKyqOAmTXhiJm2F5g7J4CQ747975S8=
 =49Pi
 -----END PGP SIGNATURE-----

Merge tag 'at91-dt-6.1-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt

AT91 DT for v6.1 #2

It contains:
- new SAMA5D3 based board, namely SAMA5D3-EDS
- adjustments to pass the DT binding validations
- disable AES on some LAN966 based boards as they are reserverd by
  secure OS

* tag 'at91-dt-6.1-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  spi: dt-bindings: atmel,at91rm9200-spi: Add DMA related properties
  ARM: dts: at91: Add `atmel,usart-mode` required property to serial nodes
  ARM: dts: at91: sam9x60ek: Add DBGU compatibles to uart1
  ARM: dts: at91: sama7g5: Swap rx and tx for spi11
  dts: arm: at91: Add SAMA5D3-EDS Board
  dt-bindings: arm: at91: Add info on SAMA5D3-EDS
  ARM: dts: lan966x: disable aes

Link: https://lore.kernel.org/r/20220916105407.1287452-1-claudiu.beznea@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-17 20:02:31 +02:00
Shenwei Wang
64e61a940d dt-bindings: arm: imx: update fsl.yaml for imx8dxl
i.MX8DXL is a device targeting the automotive and industrial market
segments. The chip is designed to achieve both high performance and
low power consumption. It has a dual (2x) Cortex-A35 processor.

Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17 16:25:50 +08:00
Shenwei Wang
c09cc6e528 dt-bindings: firmware: add missing resource IDs for imx8dxl
Add the missing resource IDs for imx8dxl.

Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17 16:25:50 +08:00
Tim Harvey
6128972adb dt-bindings: arm: Add i.MX8M Mini Gateworks GW7904 board
Add DT compatible string for i.MX8M Mini based Gateworks GW7904 board.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17 16:25:50 +08:00
Peng Fan
121494030c dt-bindings: soc: add i.MX93 mediamix blk ctrl
Add DT bindings for i.MX93 MEDIAMIX BLK CTRL.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17 16:25:50 +08:00
Peng Fan
4fed4d20c5 dt-bindings: soc: add i.MX93 SRC
Add bindings for i.MX93 System Reset Controller(SRC). SRC supports
resets and power gating for mixes.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17 16:25:49 +08:00
Peng Fan
7a8a447163 dt-bindings: mfd: syscon: Add i.MX93 blk ctrl system registers
Document i.MX93 BLK CTRL system registers.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17 16:25:49 +08:00
Martyn Welch
b08047d63c dt-bindings: arm: fsl: Add MSC SM2S-IMX8PLUS SoM and SM2-MB-EP1 Carrier
Add DT compatible strings for a combination of the 14N0600E variant of
the Avnet (MSC branded) SM2S-IMX8PLUS SoM on it's own and in combination
with the SM2-MB-EP1 carrier board.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17 16:25:49 +08:00
Frieder Schrempf
25b1896467 dt-bindings: arm: fsl: Add Kontron BL i.MX8MM OSM-S board
Add bindings for the Kontron BL i.MX8MM OSM-S board.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17 16:25:49 +08:00
Frieder Schrempf
9d820e6581 dt-bindings: arm: fsl: Rename compatibles for Kontron i.MX8MM SoM/board
This updates the bindings in order to use names for the boards that
follow the latest convention used by Kontron marketing.

By updating we make sure, that we can maintain this more easily in
future and make sure that the proper devicetree can be selected for
the hardware.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17 16:25:49 +08:00
Peng Fan
c7ebd54158 dt-bindings: soc: imx: add i.MX8MP vpu blk ctrl
i.MX8MP VPU blk ctrl module has similar design as i.MX8MM, so reuse
the i.MX8MM VPU blk ctrl yaml file. And add description for the items.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17 16:25:49 +08:00
Peng Fan
2345fc8dc2 dt-bindings: soc: imx: add interconnect property for i.MX8MM vpu blk ctrl
i.MX8MM VPU support NoC QoS setting, so add interconnect property
for i.MX8MM VPU blk ctrl

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17 16:25:49 +08:00
Peng Fan
c1d9381ce4 dt-bindings: soc: imx: drop minItems for i.MX8MM vpu blk ctrl
minItems and maxItems are set as the same value. In such case minItems is
not necessary. So drop it.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17 16:25:49 +08:00
Peng Fan
69e43d9e83 dt-bindings: power: imx8mp-power: add HDMI HDCP/HRV
Add i.MX8MP HDMI HDCP and HRV entries.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17 16:25:48 +08:00
Frieder Schrempf
3627a8139d dt-bindings: arm: fsl: imx6ul-kontron: Update bindings
This updates the bindings in order to simplify the devicetree
structure and to add names for the boards that follow the latest
convention used by Kontron marketing.

It also gets rid of the N6xxx notation in the compatibles and
file names, as they are not really used anymore and often result
in confusion.

This is a breaking change, but the impact shouldn't be too big
and it makes usage and maintenance easier in the future.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17 16:25:48 +08:00
Marcel Ziswiler
402de4bfb3 dt-bindings: clk: imx8mm: don't use multiple blank lines
Avoid the following checkpatch warning:

include/dt-bindings/clock/imx8mm-clock.h:284: check: Please don't use
 multiple blank lines

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17 16:25:05 +08:00
Tim Harvey
b7fd68ac27 ARM: dts: imx6qdl-gw54xx: add CAN regulator
The GW54xx has a transceiver with a STBY pin connected to an IMX6 GPIO.
Configure this as a regulator to drive it low when CAN is in use.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17 12:21:38 +08:00
Tim Harvey
ad928a743d ARM: dts: imx6qdl-gw53xx: add CAN regulator
The GW53xx has a transceiver with a STBY pin connected to an IMX6 GPIO.
Configure this as a regulator to drive it low when CAN is in use.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17 12:21:30 +08:00
Tim Harvey
2069c5265b ARM: dts: imx6qdl-gw52xx: add CAN regulator
The GW52xx has a transceiver with a STBY pin connected to an IMX6 GPIO.
Configure this as a regulator to drive it low when CAN is in use.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17 12:21:21 +08:00
Sergiu Moga
0b2eafe116 spi: dt-bindings: atmel,at91rm9200-spi: Add DMA related properties
The DT nodes of the SPI IP's may contain DMA related properties so
make sure that the binding is able to properly validate those as
well by making it aware of these optional properties.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220913142205.162399-5-sergiu.moga@microchip.com
2022-09-16 10:52:24 +03:00
Sergiu Moga
f9e1d0767f ARM: dts: at91: Add atmel,usart-mode required property to serial nodes
Add the missing required DT property `atmel,usart-mode` to the serial
nodes of Atmel/Microchip DT files.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220913142205.162399-4-sergiu.moga@microchip.com
2022-09-16 10:41:36 +03:00
Sergiu Moga
7fca501460 ARM: dts: at91: sam9x60ek: Add DBGU compatibles to uart1
Maintain consistency among the compatibles of the serial nodes of
sam9x60ek and highlight the incremental characteristic of its serial
IP's by making sure that all serial nodes contain both the sam9x60
and sam9260 usart/dbgu compatibles.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220913142205.162399-3-sergiu.moga@microchip.com
2022-09-16 10:41:36 +03:00
Sergiu Moga
944ec7d1a3 ARM: dts: at91: sama7g5: Swap rx and tx for spi11
Swap the rx and tx of the DMA related DT properties of the spi11 node
in order to maintain consistency across Microchip/Atmel SoC files.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220913142205.162399-2-sergiu.moga@microchip.com
2022-09-16 10:41:36 +03:00
Arnd Bergmann
32c3d47fd7 This pull request contains Broadcom ARM64-based SoC changes for 6.1,
please pull the following:
 
 - Rafal adds the BCM4908 LED controller node and describes all 32 LED
 pins, he also adds support for the Asus GC-AC5300 LEDs
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmMfeXkACgkQh9CWnEQH
 BwS3XRAA1UyWHE6AqYSsLWcllNBxvbgJ9Fm5PqyY2+ZvMcHL3Pt5R0drY9tkQRfx
 ohiZmNoMxRgoVi79DGunVp9MWHtYzAyjoN8TOvS2er3zfEGBqoLTxPzNMDqcuX7y
 rtnFcrRAcr501gqqQ/ueaFxNDiIUY9aa48aPs7m7Tvqk9waKGtSDJ/y07+Bc/MYX
 RlsjKBkElfU8E/kcUQlGxGwEfaZ3V2nZtagf1En/BYtZ3X16T/zHJozu9TcI9YxQ
 yRxs7erW1GMOnrkVrlQFCH2TojhO6Ec5NtgSb2Ix9Bk80bU1l2hda6mm/lRFi81A
 AaJE1beJzspuQwHgS8zhKNwQNSzTptROkmzL5Ema7TKab72E9Oyp5cmTF5GaMskH
 BGunAghmi5SDU4Xz1sr5NnPSvnYwi/MdJvlPTSbzMGTuMk2Eze4vH5lAzsgePBr+
 Uw9B+nI/j6JIzQCrzzNZrr/M5i0PItuXvNO/ia8YbFnmQo4BvYwK4tE7G0i7kTmn
 YP428RYM7UontSBdEcJi/2P6JHoJvyxisbaMPgdBw8GP+qUgb8hiH/w9qJvIhcFX
 WfYZlILSKLbtnDob4o9HjN46W5IH5AbwcVy+Ax7qGA1l1yxxXjPB2CHJFtDCSpzK
 MfVoiUBqzdn/gZ68WQZbXuDchIBZG/FxFmr8zRyIiiQfWkHnHYY=
 =+IBl
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMjhSAACgkQmmx57+YA
 GNn7zw//ezQSo9ofE2JAQWzCs3d+3S3QAFqCz/PoBCmFS71Yoi59BoVD3ghVUdyB
 KZMEhWPgHa+MHJWHOqNM4TBbEF8J6MZNXIB/nrxG2L8h4QYmN995jlyQSsHX8yGd
 NEg9bwcTZ4lf5a2VZgzVgseNS3K4tOr0dGyIY68N1fmg4HaADbycYbOJjICxUDyL
 RNpghhJm3IIc/iwSS+kiY8Zny1MZnGj35xmvbzKOLek6DE6WeCZshP01MZD9BPJ2
 VAOQjHQ2z8XUjoHWEmkcl7HOnC6IILgdJwaRmrS8dHR1nIdN8n3J9ldpjdtCDXtD
 A+wjfhXsSg1O9yRfXfNnEXhPYma3lJMHllT266fas8344tXrrp2xmvIOI96UP+Um
 VhWsjkrTAXKBe26L5tkq5XEmgdmzclFPmn7gUzoGu7Ho5G2HvSZXTqng3OkGKlj/
 k6sIH+W56Ew0HfBkwwoZGiixp8YBepQG59jTDeOsosI4783k8Iwk8dZByxnlUH5o
 eHlSbmbbz5LpySMfanwbGSwoNUBmlG9n0OoNufzsQDNwsWPnl+iMH6JlyF/9qeDs
 yPDXZ3WAON7Mua6cFgeBDNyUOlw5uHZvfy1Lhx5MDwjsC05p+bd6At2dpjYHWTja
 t019ijZ1iD4eZqhF1Hd+tkFcI+xmOfIKeupQEG/vV5PEBktgEWk=
 =ybyG
 -----END PGP SIGNATURE-----

Merge tag 'arm-soc/for-6.1/devicetree-arm64' of https://github.com/Broadcom/stblinux into arm/dt

This pull request contains Broadcom ARM64-based SoC changes for 6.1,
please pull the following:

- Rafal adds the BCM4908 LED controller node and describes all 32 LED
pins, he also adds support for the Asus GC-AC5300 LEDs

* tag 'arm-soc/for-6.1/devicetree-arm64' of https://github.com/Broadcom/stblinux:
  arm64: dts: broadcom: bcm4908: add Asus GT-AC5300 LEDs
  arm64: dts: broadcom: bcm4908: add LEDs controller block
  arm64: dts: broadcom: bcm4908: add remaining LED pins

Link: https://lore.kernel.org/r/20220915023044.2350782-3-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-15 22:03:43 +02:00
Arnd Bergmann
e33060879c This pull request contains Broadcom ARM-based SoC Device Tree updates
for 6.1, please pull the following:
 
 - Rafal improves the BCM5301X PCIe DT nodes schema validation by
 flagging the PCIe controller with a missing "device_type" property
 
 - William merges BCM4908 within BCMBCA since this chip is part of the
 Broadcom Broadband Carrier Access group and follows the architecture of
 those chips
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmMfeSQACgkQh9CWnEQH
 BwSu8A//bscpH0DKVVkZyji+UQN0c0WmBhPJTbedQRrMEABAmrF0kfJdGbNEe01r
 Qzb2GjhLpWDX5pL+SmDmjX0l9OQZiv83ruPCDK97HDqy1V1LbGBiT1I37R9eNW1v
 mWtL67RSEiuDKZdSfDEq/rkoPbYhowuYsSvIz53qr9EvFEjZXAXbRRpzKUJ/wDL1
 Nk/y+j6Vlc5ZzScsIZucRuIp9AJ4tH+Kaj+ZNcRs7cG01Ot4PtBa2gxCr7pmyiY4
 q9PFFWUZPQpKkMo/jLWvT4ajsHm7Fv4CLZK8h9GZOAuxYvmhqqLoPigDvBS3sug1
 Je2V2gdeuqiFgh9i6XHVM/XM2Hr+z8RHsFISjyHZQYUwSiWxo+E2p8pql/tMmh6Q
 swSX971xbbgBOVPC1JWuFTEtm8vWwGtlZXE5iptxWxTn5cq1pHNkg3wCNIMXjUei
 Bj78PM4ZyNPbJ5lq4RJP0ryT5N1UCYaX6sOh+nOD6GH1YXq+5XO4nx6/yeUEGKSM
 sGogAy40a0qP6UlHVdfayDgXFIfgSjY15Pfq5unSIEywQHhBR1GKDgrrAXSWQrux
 8F2kY0v2FDnAZeoYwWrJvrN24NmKm3TMeKjyoz7tu2KHYADWWQ1UrujFuXBAoIZC
 QeuFjfg/Ymar6A1BGwcQsrxDgMWruOLB9/029g8vLfoIuUYjNqA=
 =JcYR
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMjhE0ACgkQmmx57+YA
 GNmF5RAAoV7YjTJbbUqvuyJtqui491JY+ppMJtMYvq97PIIPhoNhQC2Yh3pfq/RG
 gL3a1+aXxMw5/YXOz2BJ5EIfHcfnkZF4DbIdGFviueMchh8sxTLivPHLcFRc7y6k
 RN9ydIpgq/XxrALGIq3N4zSl3D823HEbQ0UcN4RkxbPPqXDgTGxkwcvWrMaDJolb
 iLJpTaeael7VVaLNuPmDb0igEAAHbGNxQcu8MpRlaTwLZnJZHuOjxs8/h3ZhH+3g
 ZjDXw0qqO1kEdyqkJgUofJT8l0Hn54zoZDXZIJnhEiTsjcGR/X4jl2B+13vt8jW9
 MWcMh6DMK3U1zgRfAJnt4Ufas8iUc181yx3CRPBc/gIjh8t4arxD1wlepNcvPUBt
 AAM0Zi3j+CKzvLuU3IugOAWNLGUIcie6L/CWrEA2EYzd8IVtINd0mcWdPlP5L4/j
 4LwTJjQGNr+wedtWL1u90Oe3Qciax1IFwBRQBNR0y+4SRUhmzoVDKtFCiuRF/YpE
 GjmpLamdr+8XWjcGv3YvK50z6XTwSlWaMKyiHyDp3IGX4swmNJDHT3NyDhBL+ubH
 4jzBsBHJ2y/3PuaqruHUgD+r65kK88dVgfaSOZGNukdIdM8q2LobcZeXPB+nRdS2
 A67ekYdLcieeEFtkzaJOIogEpbou0CPgwxyStyDbWPZyk1JJkfA=
 =4L+j
 -----END PGP SIGNATURE-----

Merge tag 'arm-soc/for-6.1/devicetree' of https://github.com/Broadcom/stblinux into arm/dt

This pull request contains Broadcom ARM-based SoC Device Tree updates
for 6.1, please pull the following:

- Rafal improves the BCM5301X PCIe DT nodes schema validation by
flagging the PCIe controller with a missing "device_type" property

- William merges BCM4908 within BCMBCA since this chip is part of the
Broadcom Broadband Carrier Access group and follows the architecture of
those chips

* tag 'arm-soc/for-6.1/devicetree' of https://github.com/Broadcom/stblinux:
  arm64: bcmbca: Merge ARCH_BCM4908 to ARCH_BCMBCA
  arm64: dts: Add BCM4908 generic board dts
  arm64: dts: Move BCM4908 dts to bcmbca folder
  arm64: dts: bcmbca: update BCM4908 board dts files
  dt-bindings: arm64: bcmbca: Update BCM4908 description
  dt-bindings: arm64: bcmbca: Merge BCM4908 into BCMBCA
  ARM: dts: BCM5301X: Add basic PCI controller properties

Link: https://lore.kernel.org/r/20220915023044.2350782-2-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-15 22:00:13 +02:00
Akhil R
8e4428051d arm64: tegra: Add GPCDMA support for Tegra I2C
Add dma properties to support GPCDMA for I2C in Tegra 186 and later
chips

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:38 +02:00
Mohan Kumar
af4c27738c arm64: tegra: Add iommus for HDA on Tegra234
Add the iommus property to the HDA node on Tegra234.

Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:38 +02:00
Mohan Kumar
0a4fa25042 arm64: tegra: Enable HDA node for Jetson AGX Orin
Enable HDA node for the Jetson AGX Orin platform.

Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:38 +02:00
Mikko Perttunen
b35f5b53a8 arm64: tegra: Add context isolation domains on Tegra234
Add Host1x context isolation domains on Tegra234. On Tegra234 we have
two IOMMUs that are connected to Host1x-channel programmed engines,
so we have to include domains for each of them.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:38 +02:00
Thierry Reding
b0c1a994f6 arm64: tegra: Fixup iommu-map property formatting
Make sure that each phandle-array is enclosed in a set of angular
brackets and properly indent each entry.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:37 +02:00
Diogo Ivo
a1e3de6ea5 arm64: dts: tegra: smaug: Add Wi-Fi node
The Google Pixel C contains a BRCM4354 Wi-Fi + BT module.
Add a DT node for its Wi-Fi functionality. Tested on Pixel C.

Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:37 +02:00
Diogo Ivo
a63c0cd837 arm64: dts: tegra: smaug: Add Bluetooth node
The Google Pixel C contains a BRCM4354 Wi-Fi + BT module.
Add a DT node for its BT functionality. Tested on Pixel C.

Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:37 +02:00
Thierry Reding
8aec2c17b9 arm64: tegra: Enable MGBE on Jetson AGX Orin Developer Kit
A Multi-Gigabit Ethernet (MGBE) instance drives the primary Ethernet
port on the Jetson AGX Orin Developer Kit. Enable it.

Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:37 +02:00
Thierry Reding
610cdf3186 arm64: tegra: Add MGBE nodes on Tegra234
Add device tree nodes for the four instances of the Multi-Gigabit
Ethernet (MGBE) IP found on NVIDIA Tegra234 SoCs.

Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:37 +02:00
Thierry Reding
4f41e9d542 arm64: tegra: Fix up compatible for Tegra234 GPCDMA
There is no need to list the Tegra194-specific compatible for Tegra234
because the backwards-compatibility goes back all the way to Tegra186.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:37 +02:00
Vidya Sagar
1d61cbb790 arm64: tegra: Enable PCIe slots in P3737-0000 board
Enable PCIe controller nodes to enable respective PCIe slots on
P3737-0000 board. Following is the ownership of slots by different
PCIe controllers.
Controller-1 : On-board Broadcom WiFi controller
Controller-4 : M.2 Key-M slot
Controller-5 : CEM form-factor x8 slot

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:37 +02:00
Vidya Sagar
ec142c44b0 arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT
Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree.
The Tegra234 SoC contains 10 PCIe controllers and 24 P2U instances
grouped into three different PHY bricks namely High-Speed IO (HSIO-8 P2Us)
NVIDIA High Speed (NVHS-8 P2Us) and Gigabit Ethernet (GBE-8 P2Us)
respectively.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:37 +02:00
Vidya Sagar
cd42b26a52 arm64: tegra: Add regulators required for PCIe
Add regulator supplies required for PCIe functionality. The supplies
include 1.8V, 3.3V and 12V.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 21:30:37 +02:00
Thierry Reding
5b6b207ca5 Merge branch 'for-6.1/dt-bindings' into for-6.1/arm64/dt 2022-09-15 21:30:18 +02:00
Mikko Perttunen
cc99f95d49 dt-bindings: Add Host1x context stream IDs on Tegra234
Add defines for stream IDs used for Host1x context isolation
on Tegra234. The same stream IDs are used for both NISO0 and
NISO1 SMMUs since Host1x's stream ID protection tables don't
make a distinction between the two.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15 14:05:42 +02:00
Jerry Ray
7ea519de71 dts: arm: at91: Add SAMA5D3-EDS Board
The SAMA5D3-EDS board is an Ethernet Development Platform allowing for
evaluating many Microchip ethernet switch and PHY products.  Various
daughter cards can connect via an RGMII connector or an RMII connector.

The EDS board is not intended for stand-alone use and has no ethernet
capabilities when no daughter board is connected.  As such, this device
tree is intended to be used with a DT overlay defining the add-on board.
To better ensure consistency, some items are defined here as a form of
documentation so that all add-on overlays will use the same terms.

Link: https://www.microchip.com/en-us/development-tool/SAMA5D3-ETHERNET-DEVELOPMENT-SYSTEM
Signed-off-by: Jerry Ray <jerry.ray@microchip.com>
[claudiu.beznea: s/gpio-inputs/gpio-keys in at91-sama5d3_eds.dts]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909163022.13022-2-jerry.ray@microchip.com
2022-09-14 10:33:30 +03:00
Jerry Ray
af2a5ea3ff dt-bindings: arm: at91: Add info on SAMA5D3-EDS
Adding the SAMA5D3-EDS board from Microchip into the atmel AT91 board
description yaml file.

Signed-off-by: Jerry Ray <jerry.ray@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909163022.13022-1-jerry.ray@microchip.com
2022-09-14 10:24:02 +03:00
Horatiu Vultur
b716f7981e ARM: dts: lan966x: disable aes
Disable AES node on lan966x pcb8290, pcb891 and pcb8309 because these
boards have lan966x that uses secure OS which reserves the AES block.
Therefore it can't be exposed to non-secure world.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220908070451.3730608-1-horatiu.vultur@microchip.com
2022-09-14 10:23:42 +03:00
Arnd Bergmann
2c12f88cef Samsung DTS ARM64 changes for v6.0
1. Add binding headers for several Exynos850 and ExynosAutov9 clocks.
 2. ExynosAutov9: Add FSYS clock controller nodes.
 3. ExynosAutov9: Document serial compatible (used in DTS).
 4. Exynos850: Add Audio, IS, MFC clock controllers. Add IOMMU nodes.
 -----BEGIN PGP SIGNATURE-----
 
 iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmMbVoEQHGtyemtAa2Vy
 bmVsLm9yZwAKCRDBN2bmhouD1+oyD/wIScAnh7VVTa1OXhHx3PRMxij3bHA8bka8
 B+eTXuHDgomjyjOOysb8APouBAX9nVsi2HFTLOvL9cKLfOZ8mIJutQj70EEfRrg2
 sdVrDgDkJjFkDDNbYyxoLWN/GE1GlambxyTX2BKqJa3GoOg7tcMmXFpy3Lik0XKP
 nxZdIi63aEZc96rqtoLBn4Ni7kWllNNKnGZabrxK4cs3jTHO0Ay+ZGp57exXwEgf
 JdTPaVCw8uB2jjStZESwnldsBZxzJFpwUG+R3cLOejXq8xHuvxpJgD8rvBWS7A8u
 2zOA/qONL1J+B/3pLtlWJAAOXL9MPlxAxWzYOdcaV+vm8XCDhA1aDlJPP+STpcFy
 5zBwm44rqEelgYqPS0CwtCigC0tCmsekMANnRUeCSAmzjRYq18dLF8S36AUPR6UK
 sAtrJwgaGwg6xgsIX4ZqpGKEwNnv6FhViXHGp6Dq3Gw/Czin4Q8sHhRBIhFkUn19
 g4nerk+vzsILke4ZgVT0Hab6Yplrlestc7nxnkAAsPQMwSK9g29HionzNGgxW91m
 7MupJq9KcDGOY3UvSID/L4Bh7XJm/oIqskQX/UGvVACkuprpPs9zlGoO0vwfsQKA
 4HL27Bwvfb1msTFvpOVK4uU00S1sCBd7cnsvS1KoJaxOxSjlLlMwI+ZEUcl+PC5e
 vtkE60ZhfA==
 =bRQO
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMfTh0ACgkQmmx57+YA
 GNkRqxAAlhirqrhRyy2MKuHiI0jJPqXCjbI8CWq1Snb9/aWjkn2Jvg7GChbRnpaS
 bUBMRlwo5ejMJA53zyhx7UMBLzfhrPdAVWZ81sy+EsLMcXRFQ1yXAuocHCMM8Sry
 ttNrof8gi94QOHdkJOqWOF8+/s96bfATms583UlCw5nQR7FX9PeE72zT49YAP5zG
 gUrTmLhZ16fDQDnrAcUJXEbDcSkXO7xsxy1fun0LmykS6bvHK4M5nWsNcYz0JJYm
 L+lQeM/xe3cyIsaqGRkiH+tu1YxCePNSIq2BcfMi+s0dYX0UKnfLAcsxrfVF434/
 pfD/YlXdSnm9QhSowwTe9iDNObuXkxmYuTKJqS0kSmm0Ayc7KrAhZylF7POgYkwG
 KOWis+31f8vinpMKYmLbWKwmo8EgXTdIuANwwX5VyH42GtESpmxnSp6wQO5/i8S3
 TPiG/R4sq5e23qpCez5CBU7ImnDObHCYflW0HLWi1YAUS1oRgVeXXWC+Zt0yzXyS
 IAnz3vwSQqnIbXyzVIQOl9rV+UYLzFixk+3QnXn3RfTEVzJzlKkXp3Jr5ntarW3M
 apqxOwJh7k9QZsawEjNtBNlWgasmD1ThDw7+rp3idbjBJGXppy/mKHBoD3PrzyWw
 AVG3L8SjNrHHxFvKqzDkmVF72tGee+t/vZHzoVLVuPjddkSf4Eo=
 =xnEY
 -----END PGP SIGNATURE-----

Merge tag 'samsung-dt64-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt

Samsung DTS ARM64 changes for v6.0

1. Add binding headers for several Exynos850 and ExynosAutov9 clocks.
2. ExynosAutov9: Add FSYS clock controller nodes.
3. ExynosAutov9: Document serial compatible (used in DTS).
4. Exynos850: Add Audio, IS, MFC clock controllers. Add IOMMU nodes.

* tag 'samsung-dt64-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  dt-bindings: serial: samsung: add exynosautov9-uart compatible
  arm64: dts: exynos: Add SysMMU nodes for Exynos850
  arm64: dts: exynos: Add CMU_AUD, CMU_IS and CMU_MFCMSCL for Exynos850
  arm64: dts: exynosautov9: add fsys0/1 clock DT nodes
  dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCL
  dt-bindings: clock: exynos850: Add Exynos850 CMU_IS
  dt-bindings: clock: exynos850: Add Exynos850 CMU_AUD
  dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
  dt-bindings: clock: exynosautov9: add fsys1 clock definitions
  dt-bindings: clock: exynosautov9: add fys0 clock definitions
  dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1

Link: https://lore.kernel.org/r/20220909150849.820523-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-12 17:19:57 +02:00
Arnd Bergmann
6d243f8981 STM32 DT for v6.1, round 1
Highlights:
 ----------
 
 - MPU:
   - General:
     - Add I2C support (5 instances) on STM32MP13.
     - Add SPI support (5 instabces) on STM32MP13.
     - Add timer interrupts support on STM32MP15.
 
   - ST boards:
     - Enable I2C1 and I2C5 on stm32mp135f-dk board.
     - Add SPI5 on stm32mp135f-dk board but disabled as only available on
       the GPIO expansion connector.
 
   - ARGON:
     - Remove spidev node as not used by the code.
 -----BEGIN PGP SIGNATURE-----
 
 iQJRBAABCgA7FiEEctl9+nxzUSUqdELdf5rJavIecIUFAmMfNDwdHGFsZXhhbmRy
 ZS50b3JndWVAZm9zcy5zdC5jb20ACgkQf5rJavIecIXHHw//f2HN23M75xgKkYZH
 XAoRHGvoxUAmc4Oi41yAShpszb6O4HjnweRGIIrqr+UK6Hg/RwHSM4pqXRhJrnrk
 RtLMTbtd3SAHcnKxGw6NTTz7BjJeD5Ey1XQmUbHPZg+wqXPbpqfR+Mf8jGO+cyG+
 WBKjJbBxQQKWiupve1W3oqcAgp22oPpUxsl8BWJZlQVcdJvTZe/jg3nvqZueVU7R
 NlzF5AjbWnqzGNl65xZYad1s30jMeTOHZdH9wQlkbwM/iJ8/Qx+N4LS24nf4voYu
 /Mz+CzzWGDycZOCiRtmJBrxOCNqXZXebVb2ZwcPcVggrEXO1vJwxCtv+4oQkzXvv
 q0xTpd8+0xibXkt3rckMpSJ0zZlae4cHhHAgMUAJhPCBI0PXeEsThIJS/EzE7IQU
 qGvnZb7CPhbdBIWJ5MD3gjHbv8zUTuelbce3QP8e7DZNrLRnI+SHLgH8Owuoob8t
 RMOPJt4e0GhH69V2+B1GlE9PvHca2Bew+mbYtm8PphwSW0iGFcxbSxECN6YdBFMd
 vJGiQrrvnVW/+GT/eoVM78+OgnJ9qviLJOJc3iWsE/pcXAgAbqrXHOG4RZv1xmp5
 fvQZg4LHz9IEx9z23poQezApqyYdemt8ijmL2B1xzb+SJsbEgYmW2XdoI0+dEggm
 VwVP3B6HV6ERgvVJby5cv0Ft+NU=
 =QRRi
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMfQ8QACgkQmmx57+YA
 GNne/g//blaPR87ylFXix1Zj95pKZIN0HuXZ80/87Wwyn6imylmV+z66PifcftCS
 wl/1HEu9OfHwMDES5yIXlcOAUWolLbbkBv53DF09EwOP9Hs9zy4dvc0qiZ3RVn9b
 28O8P3JmNisTkGYABSf9FVlZAVVYPRKzURRCFYPe+ybznbjzlBmUtAdow3AC3Uwt
 bHv6B5BLqVzLENKj3DaPiRmhQ+sC/oG5VsrvjbmYRS4rVa//34cK44Z7kMfdn7tQ
 Av/BWbCmgZrpa5tvmILgz5uD240GZ4rsLrz73LJVMJ5+rnnc1GXRfK6TKG7tC5Xo
 WlM+vToDqS2f8OS6b9ZzqQCcWqJB26SEoLuhq8pt5l0EO30bvM8/mpVzDD0N8vgY
 0TMPb83KSMuK2V+GxKFHNECJqrmR/fz81qnVrQ1KC1K9JcYholVu4e9WnSKTBBkG
 wOn+4BjPiK8f5ApccNtntl2Vn2ZGqMEtsblqxkGxIkjpoHkPsXl+LE+T7vlpjcbX
 m3nLKQ93BbenhwJuoE78qTOyfNX0aDW7XOykWI7SWSeYSH/U4SmhQ0qLc6erL7YT
 W/lSrpI+Pz5QJba7WxfnOYiT2kTyNmsjy5h2ug87zZ2Uq8wwRVh/Ynddx6asBJdS
 vfAeen5RUV0eWZAsCmaThVpwGFidWkGBYxUmb54Podf4+/MJf0Y=
 =iYz9
 -----END PGP SIGNATURE-----

Merge tag 'stm32-dt-for-v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt

STM32 DT for v6.1, round 1

Highlights:
----------

- MPU:
  - General:
    - Add I2C support (5 instances) on STM32MP13.
    - Add SPI support (5 instabces) on STM32MP13.
    - Add timer interrupts support on STM32MP15.

  - ST boards:
    - Enable I2C1 and I2C5 on stm32mp135f-dk board.
    - Add SPI5 on stm32mp135f-dk board but disabled as only available on
      the GPIO expansion connector.

  - ARGON:
    - Remove spidev node as not used by the code.

* tag 'stm32-dt-for-v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
  ARM: dts: stm32: argon: remove spidev node
  ARM: dts: stm32: Create separate pinmux for qspi cs pin in stm32mp15-pinctrl.dtsi
  ARM: dts: stm32: Fix typo in license text for Engicam boards
  ARM: dts: stm32: Add timer interrupts on stm32mp15
  ARM: dts: stm32: add pinctrl and disabled spi5 node in stm32mp135f-dk
  ARM: dts: stm32: add spi nodes into stm32mp131.dtsi
  ARM: dts: stm32: enable i2c1 and i2c5 on stm32mp135f-dk.dts
  ARM: dts: stm32: add i2c nodes into stm32mp131.dtsi

Link: https://lore.kernel.org/r/d80afc20-2745-24a2-ab70-a5a03439bd50@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-12 16:35:48 +02:00
Arnd Bergmann
b68ec1163c Adapt emac nodes to make them conform to the newly yaml-converted binding.
-----BEGIN PGP SIGNATURE-----
 
 iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmMb410QHGhlaWtvQHNu
 dGVjaC5kZQAKCRDzpnnJnNEdgcXVB/9WBLLMqcuNRWx4/rrr5Wqyvp9VycLX4L17
 iz/VYBAdetbUPmmqOSr+F1lRG/7GSG95vLhPxUUq1h7YlizfEE6hyPOT8j2xEjpv
 tj7qF3zZHaAbqNegq7NXJQ2vMBJVXe73HNHqom89Seiv1H7gWfvOdUhHCEbzyv9M
 Hf9XpdT27QxmDp9iiz1HKG5OAS6lO8XKsO2UnVR/WW8r1UIaamslP3663IHFNzIj
 hP0GTKp22FH7XXDuUZga2VQNhp8cfGMoHxoE+HlyZeuyxQtQvxAuYITykkHeGJOH
 ZjS3btzKU8/WrJrP9I1AjcXuJNJw8ozb4kIt9E/gtkUKGzAYVMho
 =QnDl
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMfPpEACgkQmmx57+YA
 GNl44hAApMqPA21l3oGyX5OglYNkyrS5yxAkJE/WtQuWyCC1vOyyl5NY3w12D2mF
 /AvsGCL8oVWJHB2pzURNhFS10vmS2T/kswjbJUKhJ8T0XLrmPHevkP0sjwZyakSz
 Iha93YsmWf9Ugpca8JDuNELYFYCdEO905lMOZTeD+W9dokkJzwLNmPO/DJelywh1
 H7YhwOhKrV6kL9hTEyLSgdQk+e26cG0xQo1n8kIJsBTH/oODa9ogDcrBLYJLgMcq
 laUlj40CyYF17NrHv1JVp+Bdi8kBg34CvJkv2uDFNcpdDkwh0GFvGUSgdyb/pmBT
 N7UIMzlf4YFZtCjXDkxzudsFEMbaV943uoQp6iczt6L8cjtKD5V8czASaOR43NIe
 0gCIe5et/9FU98A+5PW1iuIhvlQq0LuWGmAWecNEYrWPhFtzYJGs95GqxxcSGHGY
 8az5bkFqxXMtBOu7lyIatxctfXGIzKXXTcDzNTGGwDiLy4vpghi0IzMUd6inDj/v
 TXTdJ/3RCrGOed3rtpontU4CSyn9l70C29gZNYRGRCOzOk5u8AcHOdEeLWq4kalK
 VxGIttYsVvmVRuwE7qQSGI/sX146bqBjB6Q2sxC12jlS+OQYRZaum6n1m3mqw0VA
 tIyqpnwJE8WTyK7vG1fHJaIcJE5LHoI24V6cZyCBLSJV1WdCLmg=
 =AbAT
 -----END PGP SIGNATURE-----

Merge tag 'v6.1-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

Adapt emac nodes to make them conform to the newly yaml-converted binding.

* tag 'v6.1-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: restyle emac nodes
  ARM: dts: rockchip: fix rk3036 emac node compatible string

Link: https://lore.kernel.org/r/4766760.31r3eYUQgx@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-12 16:13:37 +02:00