github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-06-01 11:03:43 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

arm64: tegra: Fixup iommu-map property formatting

Browse Source 
Make sure that each phandle-array is enclosed in a set of angular
brackets and properly indent each entry.

Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding 2022-09-02 17:05:29 +02:00
parent a1e3de6ea5
commit b0c1a994f6
2 changed files with 16 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
arch/arm64/boot/dts/nvidia/tegra186.dtsi
View File

@ -1485,15 +1485,14 @@ host1x@13e00000 {
iommus = <&smmu TEGRA186_SID_HOST1X>;
/* Context isolation domains */
iommu-map = <
0 &smmu TEGRA186_SID_HOST1X_CTX0 1
1 &smmu TEGRA186_SID_HOST1X_CTX1 1
2 &smmu TEGRA186_SID_HOST1X_CTX2 1
3 &smmu TEGRA186_SID_HOST1X_CTX3 1
4 &smmu TEGRA186_SID_HOST1X_CTX4 1
5 &smmu TEGRA186_SID_HOST1X_CTX5 1
6 &smmu TEGRA186_SID_HOST1X_CTX6 1
7 &smmu TEGRA186_SID_HOST1X_CTX7 1>;
iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>,
<1 &smmu TEGRA186_SID_HOST1X_CTX1 1>,
<2 &smmu TEGRA186_SID_HOST1X_CTX2 1>,
<3 &smmu TEGRA186_SID_HOST1X_CTX3 1>,
<4 &smmu TEGRA186_SID_HOST1X_CTX4 1>,
<5 &smmu TEGRA186_SID_HOST1X_CTX5 1>,
<6 &smmu TEGRA186_SID_HOST1X_CTX6 1>,
<7 &smmu TEGRA186_SID_HOST1X_CTX7 1>;
dpaux1: dpaux@15040000 {
compatible = "nvidia,tegra186-dpaux";

17
arch/arm64/boot/dts/nvidia/tegra194.dtsi
View File

@ -1869,15 +1869,14 @@ host1x@13e00000 {
iommus = <&smmu TEGRA194_SID_HOST1X>;
/* Context isolation domains */
iommu-map = <
0 &smmu TEGRA194_SID_HOST1X_CTX0 1
1 &smmu TEGRA194_SID_HOST1X_CTX1 1
2 &smmu TEGRA194_SID_HOST1X_CTX2 1
3 &smmu TEGRA194_SID_HOST1X_CTX3 1
4 &smmu TEGRA194_SID_HOST1X_CTX4 1
5 &smmu TEGRA194_SID_HOST1X_CTX5 1
6 &smmu TEGRA194_SID_HOST1X_CTX6 1
7 &smmu TEGRA194_SID_HOST1X_CTX7 1>;
iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>,
<1 &smmu TEGRA194_SID_HOST1X_CTX1 1>,
<2 &smmu TEGRA194_SID_HOST1X_CTX2 1>,
<3 &smmu TEGRA194_SID_HOST1X_CTX3 1>,
<4 &smmu TEGRA194_SID_HOST1X_CTX4 1>,
<5 &smmu TEGRA194_SID_HOST1X_CTX5 1>,
<6 &smmu TEGRA194_SID_HOST1X_CTX6 1>,
<7 &smmu TEGRA194_SID_HOST1X_CTX7 1>;
nvdec@15140000 {
compatible = "nvidia,tegra194-nvdec";