Commit Graph

14 Commits

Author SHA1 Message Date
Kees Cook
3a2c4d55e3 treewide: refresh kmalloc_obj() conversions
This is another run of the Coccinelle script for converting kmalloc()
family of allocations to kmalloc_obj() via the existing rules in
scripts/coccinelle/api/kmalloc_objs.cocci

This catches both the set of kmalloc() uses added since the first
kmalloc_obj() conversions in v7.0 and adds a large group missed in the
first pass due to Coccinelle not interacting well with the cleanup.h
scoped_...() family of macros[1]. I worked around this with spatch's
"--macro-file" argument to a file with all the scoped_...() macros mapped
to Coccinelle's YACFE_ITERATOR[2] as that was the closest viable control
flow indicator I could find.

Build tested allmodconfig on x86, arm64, arm, loongarch, mips, powerpc,
riscv, and s390 with no new warnings.

Link: https://lore.kernel.org/lkml/202609021314.8A9C0B8@keescook/ [1]
Link: https://github.com/coccinelle/coccinelle/blob/master/standard.h [2]
Signed-off-by: Kees Cook <kees+treewide@kernel.org>
2026-09-04 21:37:00 -07:00
Charlene Liu
5b7e4ad090 drm/amd/display: ensure dtbclk clk_src selected before hdmistream_clk_en
[why]
correct a sequence issue by switching to dcn35's dccg sequence:
to make sure select dtbclk src first before programming hdmistream_clk_en.

Reviewed-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-14 19:12:35 -04:00
Leo Chen
3754bdca43 drm/amd/display: Update ONO PG Workaround for DCN42
[Why & How]
There is an updated workaround for PG Repeater issue in DCN42. This PR is
addressing the dynamic power gating use cases (Driver PG) to align with
the new sequence.

Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01 11:17:42 -04:00
Karen Chen
687bd7c811 drm/amd/display: Disable DPPCLK RCG to fix cursor disappearing
[Why & How]
DPP clock is gated when programming the cursor. This change
disables DPPCLK RCG in dccg42_init before accessing DPP,
ensuring cursor programming latches correctly.

Assisted-by: Cursor
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Karen Chen <Karen.Chen@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01 11:17:19 -04:00
Matthew Stewart
dac8aa629a drm/amd/display: Remove DCCG registers not needed in DCN42
[why]

Some resources that exist in the DCN block are not needed and shouldn't
be used.

[how]

Remove defines from register lists.

Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01 11:16:57 -04:00
Matthew Stewart
46fda8bda6 drm/amd/display: Rewrite dccg42_init
[why]

DCN42 reuses dccg42_init, which causes problems due to undefined masks.

[how]

- Read res_pool to determine the quantities of the respective resources
- Remove the physymclk root_clock_optimization check, as it seems like
  it shouldn't do anything (defaults to disabled already).

Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01 11:16:45 -04:00
Matthew Stewart
64142f9d51 drm/amd/display: Fix DCN42 null registers & register masks
[why]

The register lists used on DCN42 variants are different. Some reused
codepaths are trying to access registers not used.

[how]

Add DISPCLK_FREQ_CHANGECNTL, HUBPREQ_DEBUG, and HDMISTREAMCLK_CNTL to
the register lists.

Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01 11:16:42 -04:00
Ovidiu Bunea
ec9b4b2629 drm/amd/display: Temp disable repeater FGCG as workaround
[why & how]
There is an issue that is seemingly limited to DCN42 where systems with
IOMMU enabled will hang during reboot stress testing. The hang happens shortly
after DCN PG exit happens and HUBP is programmed for the first flip, but before
the first surface address is latched. Testing has shown that disabling
DCCG_GLOBAL_FGCG_REP_DIS, HUBP_FGCG_REP_DIS, and DCFCLK_GATE_DIS can mask this
issue.

Disable FGCG for these three repeater bits to avoid issue while debug is on-going.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 16:08:44 -04:00
Harry Wentland
d36771a034 drm/amd/display: Add DCCG DIO, HPO, OPP, and OPTC support for FRL
This adds support to HW block programming for the core blocks
for HDMI FRL:
- DIO
- HPO
- OPP
- OPTC

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03 13:44:31 -04:00
Roman Li
4aebe73f44 drm/amd/display: Add allow_clock_gating to dcn42 dccg
[Why]
The allow_clock_gating function is present in all other DCN versions
and is required to properly migrate DCCG registers access from hwseq
to the dccg component, resolving register conflicts.

[How]
Add the missing .allow_clock_gating function pointer to the
dccg42_funcs struct.

Signed-off-by: Roman Li <roman.li@amd.com>
Acked-by: Chenyu Chen <chen-yu.chen@amd.com>
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17 15:41:15 -04:00
Gaghik Khachatrian
f82480fafe drm/amd/display: Fixed Silence complier warnings in dc
[Why]
Resolve compiler warnings by marking unused parameters explicitly.

[How]
In .c and .h function definitions, keep parameter names
in signatures and add a line with `(void)param;` in function body

Preserved function signatures and avoids breaking code paths that
may reference the parameter under conditional compilation.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Reviewed-by: Austin Zheng <austin.zheng@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-30 15:12:15 -04:00
Charlene Liu
94cd4c4d71 drm/amd/display: add dccg FGCG mask init
[why]
missing DCCG_GLOBAL_FGCG_REP_DIS mask macro init

Reviewed-by: Swapnil Patel <swapnil.patel@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-23 14:16:09 -04:00
Roman Li
5b880e37a8 drm/amd/display: Enable dcn42 DC clk_mgr
Add support for DCN 4.2 clock manager.

Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-11 13:58:06 -04:00
Roman Li
bd096a56da drm/amd/display: Add dcn42 DC resources
Display Core resources for DCN 4.2:
- CLK_MGR
- DCCG
- DIO
- DPP
- GPIO
- HPO
- HUBBUB
- HUBP
- HWSS
- IRQ
- MMHUBBUB
- MPC
- OPTC
- PG

Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23 14:28:33 -05:00