Correct spaces or mix of tabs+spaces into proper tab-indented lines.
No functional impact (same DTB).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Correct the shunt-resistor-micro-ohms values for the four TI LM5066i
hot-swap controllers on the PDB. This ensures accurate current and
power sensor readings from the hardware monitors.
Signed-off-by: Mike Hsieh <mike.quanta.115@gmail.com>
Link: https://patch.msgid.link/20260618-sanmiguel-dts-config-hsc-lm5066i-v1-1-cccf959c9b78@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
GPIO 14 on the fio_ioexp (pca9555) controller corresponds to the
PWRGD_RMC_N signal, which is active-low.
The pwrgd-rmc-hog node currently specifies output-low for this GPIO
with GPIO_ACTIVE_LOW flags. Under Linux gpiolib, configuring an
active-low GPIO hog with output-low sets the logical value to inactive
(0), causing the subsystem to drive the physical line high.
Correct the hog configuration to output-high, which sets the logical
value to active (1), driving the physical pin low on boot as intended.
[arj: tidy subject line]
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Link: https://patch.msgid.link/20260716-upstream-sanmiguel-fix-pwrgd-rmc-n-v1-1-8287b306e02a@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
The interrupt properties for fio_ioexp (pca9555 on i2c14) were incorrectly
configured to gpio1 with ASPEED_GPIO(B, 6).
Update the interrupt-parent to gpio0 and the interrupt pin to
ASPEED_GPIO(C, 6) according to the hardware specification.
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Remove the TMP421 sensor entry from the DTS, as it is no longer the
primary telemetry source.
Accessing the CX8 NIC via I2C while it is powered off causes voltage
leakage on the bus, leading to EEPROM corruption on shared I2C devices.
Removing this node prevents the BMC from initiating traffic to the NIC
during initialization, protecting the integrity of the shared bus.
Signed-off-by: Mike Hsieh <mike.quanta.115@gmail.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Adds the DT nodes needed for ethernet support for Asus Kommando, with
phy mode set to rgmii-id.
When this DT was originally added, the phy mode was set to rgmii (which
was incorrect). It was suggested to remove networking support from the
DT till the Aspeed networking driver was patched so that the correct phy
mode could be used.
The discussion in [1] mentions that u-boot was inserting clk delays that
weren't needed, which resulted in needing to set the phy mode in linux
to rgmii incorrectly. The solution suggested there was to patch u-boot to
no longer insert these clk delays and use rgmii-id as the phy mode for
any future DTs added to linux.
This DT was tested (on the OpenBMC u-boot fork [2]) with a u-boot DT
modified to insert clk delays of 0 (instead of patching u-boot itself).
[3] adds a u-boot DT for this device (without networking) and describes
how to patch it to add networking support. If this patched DT is used,
then networking works with rgmii-id phy mode in both u-boot and linux.
[1] https://lore.kernel.org/linux-aspeed/ef88bb50-9f2c-458d-a7e5-dc5ecb9c777a@lunn.ch/
[2] https://github.com/openbmc/u-boot/tree/v2019.04-aspeed-openbmc
[3] https://lore.kernel.org/openbmc/20260328-asus-kommando-v2-1-2a656f8cd314@gmail.com/
Signed-off-by: Anirudh Srinivasan <anirudhsriniv@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20260331-asus-kommando-networking-v2-1-f7d72ae5d40d@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Add device tree for the Meta (Facebook) Rainiera6 compute node, based on
AST2600 BMC.
Signed-off-by: Neil Cheng <neilcheng0417@gmail.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Update several Anacapa SGPIO line names to match the existing platform
hardware design and the signal names consumed by userspace monitoring.
The previous names did not match the actual Anacapa SGPIO usage. Some
lines were named as CPU or CPU power-good signals, but they are wired
and used on Anacapa for EDSFF presence, EDSFF power-good, boot EDSFF
presence, and thermal-trip assertion monitoring.
Correct the mappings as follows:
PWRGD_PVDDCR_SOC_P0 -> L_PRSNT_EDSFF0_N
PWRGD_PVDDIO_P0 -> L_PRSNT_EDSFF1_N
PWRGD_PVDDIO_MEM_S3_P0 -> R_PRSNT_EDSFF2_N
PWRGD_CHMP_CPU0_FPGA -> R_PRSNT_EDSFF3_N
PWRGD_CHIL_CPU0_FPGA -> HPM_EDSFF_PG
EAM2_CPU_MOD_PWR_GD_R -> PRSNT_EDSFF_BOOT_N
CPU0_SP7R1 -> L_EDSFF0_PG
CPU0_SP7R2 -> L_EDSFF1_PG
CPU0_SP7R3 -> R_EDSFF2_PG
CPU0_SP7R4 -> R_EDSFF3_PG
HPM_AMC_THERMTRIP_R_L -> AMC_THERMTRIP_ASSERT
FM_CPU0_THERMTRIP_N -> CPU_THERMTRIP_ASSERT
The left-side EDSFF slots are numbered as EDSFF0 and EDSFF1 to match
the platform slot numbering used by userspace. The thermtrip names are
also updated to describe the asserted condition monitored by userspace
instead of the raw active-low signal names.
This is a naming correction for the existing Anacapa hardware design.
There is no new board revision or underlying hardware change involved.
[arj: Tweak capitalisation in commit subject, rewrap paragraph]
Signed-off-by: Rex Fu <Rex.Fu@amd.com>
Link: https://patch.msgid.link/20260518-anacapa-sgpio-edsff-thermtrip-v2-1-e43b1847b2dc@amd.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Add linux device tree entry for Meta (Facebook) SanMiguel compute-tray
BMC using AT2620 SoC.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Introduce a device tree node for the AST2600 PWM/Tach controller.
Describe register range, clock, reset, and cell configuration.
Set status to "disabled" by default.
Prepares for enabling PWM and tachometer support on platforms
utilizing this SoC.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Add an MP5998 power monitor used to monitor the power consumption
of the Paddle_P12V_HSC rail on the Yosemite5 paddle board.
[arj: Remove changelog from commit message]
Signed-off-by: Daniel Hsu <Daniel-Hsu@quantatw.com>
Link: https://patch.msgid.link/20260331120734.39260-1-Daniel-Hsu@quantatw.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Add interrupt-parent and interrupts properties to the PDB PCA9555
nodes in the anacapa DTS.
[arj: Tweak commit subject capitalisation]
Signed-off-by: Rex Fu <Rex.Fu@amd.com>
Link: https://patch.msgid.link/20260417-anacapa-pca9555-irq-v1-1-9a6d28b1b656@amd.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Add &mac0, &mdio3, and the ethphy3 PHY node to enable BMC networking
on the AST2600-based NVIDIA MSX4 board. The PHY is attached to MDIO3
at address 2 and uses RGMII with PHY-internal delays.
These nodes were intentionally omitted in commit f28674fab3 ("ARM:
dts: aspeed: Add NVIDIA MSX4 HPM") at Andrew Lunn's request, pending
clarification of the RGMII delay handling. Following his guidance on
linux-aspeed, the bootloader has been modified to stop enabling MAC
clock delays on the SoC side, so phy-mode = "rgmii-id" correctly
results in the PHY adding the required ~2ns delay without any
double-delay from the MAC controller.
The corresponding U-Boot change has been submitted to openbmc/u-boot.
Link: https://patch.msgid.link/eac09481-0ba1-4ac2-ad8c-d859822ff0d5@lunn.ch
Link: https://patch.msgid.link/20260504044702.2613879-1-andhsieh@nvidia.com
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Marc Olberding <molberding@nvidia.com>
Signed-off-by: Ender Hsieh <andhsieh@nvidia.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Add JTAG_CPLD_TRST_R_N to the sgpiom0 pin name table on Facebook Anacapa
BMC. This exposes the CPLD JTAG TRST signal through SGPIO, allowing
proper JTAG reset control during debug.
[arj: Minor tidying of commit message formatting]
Signed-off-by: Colin Huang <u8813345@gmail.com>
Link: https://patch.msgid.link/20260511-add-jtag-trst-pin-v1-1-b0be2f7b2da5@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Add the i3c controller devices to the ast2600 g6 common dts. We add all
6 busses to the common g6 definition, but leave disabled through the
status property, to be enabled per-platform.
Suggested-by: Jeremy Kerr <jk@codeconstruct.com.au>
Signed-off-by: Dawid Glazik <dawid.glazik@linux.intel.com>
Link: https://patch.msgid.link/7a94a5f4cf84c11c7fba7485e666ecbaddfbe5cf.1777058942.git.dawid.glazik@linux.intel.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
We currently have the apb's mapping of the i2c controller space as a
labelled mostly-empty node:
apb {
i2c: bus@1e78a000 {
ranges = <...>;
};
}
... and then define the contents of the i2c block later:
i2c: {
i2c0: i2c-bus@80 {
reg = <0x80 0x80>;
};
i2c1: i2c-bus@100 {
reg = <0x100 0x80>;
};
}
Krzysztof mentions[1] that isn't convention though, with the top-level
simple-bus being empty and linked via the label. So, drop the label
usage and move the i2c bus definition into the simple-bus node directly
under the apb:
apb {
bus@1e78a000 {
ranges = <...>;
i2c0: i2c-bus@80 {
reg = <0x80 0x80>;
};
i2c1: i2c-bus@100 {
reg = <0x100 0x80>;
};
};
}
This will allow us to be consistent when we add new definitions for the
i3c nodes, which would require the latter format.
Link: https://lore.kernel.org/linux-devicetree/c5331cf8-7295-4e6a-ba39-e0751a2c357e@kernel.org/ [1]
Suggested-by: Jeremy Kerr <jk@codeconstruct.com.au>
Signed-off-by: Dawid Glazik <dawid.glazik@linux.intel.com>
Link: https://patch.msgid.link/7c7010a87bb70b9e2abdadfea76d41cdcb88a82f.1777058942.git.dawid.glazik@linux.intel.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
The Anacapa board features Atmel 24C2048 EEPROMs on i2c0 and i2c1, which
are used to store retimer configurations. Add the corresponding device
tree nodes to support these components.
Signed-off-by: Dirk Chen <dirkchen@amd.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
add NFC NXP NCI device support to NFC tag reading
Signed-off-by: Carl Lee <carl.lee@amd.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Add a 128M layout for the BMC flash chip we didn't boot from. Including
this allows the user to write to each partition on the alternate spi
chip. This dtsi follows the existing standard of using the same layout
as non alt version and prepending `alt` to each partition's name.
[arj: Update subject, elide test demonstration]
Signed-off-by: Marc Olberding <molberding@nvidia.com>
Link: https://patch.msgid.link/20260120-alt-128-v4-1-0e5c491a532c@nvidia.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Add device tree for Asus Kommando IPMI Expansion card, an AST2600 based
PCIe BMC card.
Signed-off-by: Anirudh Srinivasan <anirudhsriniv@gmail.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
The at25,* properties have been deprecated since 2012. These platforms
weren't upstream until 2020 and 2023, so it should be safe to switch
over to the "new" properties and just drop the deprecated ones.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
The ALTRAD8 BMC is an Aspeed AST2500-based BMC for the ASRock Rack
ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q boards.
Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
Tested-by: Tan Siewert <tan.siewert@hetzner.com>
Reviewed-by: Tan Siewert <tan.siewert@hetzner.com>
Link: https://patch.msgid.link/20251218161816.38155-3-rebecca@bsdio.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Remove the "try-power-role = sink" property from all USB-C connectors.
The try mechanism is unnecessary and wastes time during connection.
Since power-role = "dual" is already configured, standard USB PD
negotiation is sufficient and more efficient.
Signed-off-by: Cosmo Chou <chou.cosmo@gmail.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
The Meta Anacapa BMC is the DC-SCM (Data Center Secure Control
Module) controller for the Meta OCP Open Rack Wide (ORW) compute tray.
This platform is a key component of the AMD Helios AI rack reference
design system, designed for next-generation AI workloads.
The BMC utilizes the Aspeed AST2600 SoC to manage the compute tray, which
contains up to 4 AMD Instinct MI450 Series GPUs (connected via a Broadcom
OCP NIC) and host CPUs. Its primary role is to provide essential system
control, power sequencing, and telemetry reporting for the compute complex
via the OpenBMC software stack.
For more detail on the AMD Helios reference design:
https://www.amd.com/en/blogs/2025/amd-helios-ai-rack-built-on-metas-2025-ocp-design.html
Signed-off-by: Peter Shen <sjg168@gmail.com>
Link: https://patch.msgid.link/20251219091632.1598603-3-sjg168@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Replace non-functional 'vref' with 'aspeed,int-vref-microvolt'
using the default 2.5V that the driver was already applying.
Signed-off-by: Cosmo Chou <chou.cosmo@gmail.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Remove 'aspeed,hw-timeout-ms' property which is not supported by
the driver and causes dt-schema warnings.
Signed-off-by: Cosmo Chou <chou.cosmo@gmail.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Use generic node names to fix dt-schema warnings:
- spi1_gpio: rename to generic "spi" node name
- LED nodes: rename to led-N and move names to label properties
- GPIO key nodes: add "-switch" suffix to node names
Signed-off-by: Cosmo Chou <chou.cosmo@gmail.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Changing the compatible changes the properties allowed -
snps,dw-apb-uart doesn't specify no-loopback-test, so remove it.
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
There's neither a binding defined nor a driver that matches on the
compatible, so drop it from the devicetree until someone is motivated to
solve the problems.
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Its presence is not required by the binding, its addition was not
discussed in commit aac82707fa ("ARM: dts: aspeed: Add AST2600 EDAC
into common devicetree"), and its inconsistent with the g4 and g5
dtsis.
Further, the corresponding driver instantiates its own regmap rather
than fetching the syscon regmap, in theory breaking any users of the
syscon, but of which there appear to be none in-tree.
Drop it for now, and we can add it back with the necessary rework if
it's ever required.
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
While sdhci-pltfm supports sdhci,wp-inverted, it also supports
the un-prefixed and specified wp-inverted property. Switch the EVB
devicetree to use the specified property to remove warnings when
checking the DTB.
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
The property isn't specified in the bindings and is not used by the
corresponding driver, so drop it.
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
The gpio-leds driver requires all GPIOs in a group to be available;
if any GPIO in the group is not available the whole group will not be
created. The hdd_led GPIO is only present after standby power is
enabled, which can prevent other LEDs in the same group from being
created and blocks properly setting 'bmc_ready_noled'.
Move the 'hdd_led' node into a separate gpio-leds group so that other
LEDs are not blocked and the 'bmc_ready_noled' flag can be set
correctly.
Fixes: b5dd162282 ("ARM: dts: aspeed: clemente: Add HDD LED GPIO")
Signed-off-by: Alex Wang <alex.ts.wang@fii-foxconn.com>
Link: https://patch.msgid.link/20251127-leo-dts-add-shunt-resistor-v2-1-c77dfbfb826c@fii-foxconn.com
[arj: Fix patch subject, add Fixes: tag]
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
The chassis power cycle process requires a forced shutdown before
cutting off the standby power. The SCM CPLD implements a hard shutdown
host function that is controlled through the IO expander in the
Clemente platform.
This change adds a new GPIO line named "shdn_force_l_cpld" to the
PCA9555 IO expander's gpio-line-names at index 10. When asserted,
this GPIO signals the CPLD to pull the HPM's SHDN_FORCE_L pin low,
which triggers a forced host shutdown.
Signed-off-by: Kimi Chen <kimi.zy.chen@fii-foxconn.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Add an IPMB node for OCP debug card to support IPMI communication.
Signed-off-by: Fred Chen <fredchen.openbmc@gmail.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Add IO expander emulated by the switch board CPLD to handle UART and SPI
mux control signals. Also add SGPIO labels with FM_MODULE_PWR_EN_N_*
signals, which control power to each ASIC module individually.
Signed-off-by: Fred Chen <fredchen.openbmc@gmail.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Add EEPROM devices on the I2C buses used for the boot and data NVMe
drives. These EEPROMs store FRU information for each drive, allowing
the BMC to identify.
Signed-off-by: Leo Wang <leo.jt.wang@gmail.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Add the SGPIO definition for detecting fanboard presence on the Harma
platform. This allows the BMC to determine whether the fanboard is
attached.
Signed-off-by: Daniel Hsu <Daniel-Hsu@quantatw.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Remove the external signal configuration from wdt1 to prevent the
WDTRST1 pin from being asserted during watchdog resets.
The WDTRST1 pin was originally configured to reset the TPM during
watchdog events. However, the pin is incorrectly routed to SRST#
on the hardware, causing unintended system resets. Since the TPM
is not currently utilized on this platform, remove the external
signal configuration to avoid the incorrect reset behavior.
Signed-off-by: Cosmo Chou <chou.cosmo@gmail.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Three new SoCs got added in existing arm64 chip families:
- Renesas R-Car X5H (R8A78000) is a new generation of automotive SoCs,
based on 16 Cortex-A720 (Armv9.2) cores, which makes the the currently
highest-perforance embedded SoC.
- TI AM62L is a new variant of the AM62 family of industrial SoCs, this
one comes without a GPU.
- Qualcomm MSM8937 (Snapdragon 430) is an older mobile phone chip based
on Cortex-A53, and closely related to MSM8917 (Snapdragn 425), which we
already support.
In addition, there are a good number of newly supported machines
across SoC families:
- Two Aspeed AST2600 (Cortex-A7) based BMC setups for large servers
- Mobile Phones and tables based on Mediatek MT6582, Nvidia Tegra124,
Qualcomm MSM8937 and Qualcomm MSM8939,
- Two Laptops based on Qualcomm SoCs: one using the older sdm850, the
other using x1p42100.
- One Router based on Rockchips RK3568
- 24 variants of the Enclustra Mercury system-on-module, all based on
32-bit Intel/Altera SocFPGA chips, plus two boards using 64-bit
SocFPGA Agilex chips..
- 30 industrial/embedded boards and single-board computers, using
various chips from NXP, Rockchips, Mediatek, TI, Amlogic, Qualcomm,
Spacemit, and Starfive.
In total there are 783 commits here, the majority of these improving
hardware support and cleaning up devicetree files across the tree, with
the majority of the changes going into the Qualcomm, NXP, Renesas and
Rockchips platforms.
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Merge tag 'soc-dt-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"Three new SoCs got added in existing arm64 chip families:
- Renesas R-Car X5H (R8A78000) is a new generation of automotive
SoCs, based on 16 Cortex-A720 (Armv9.2) cores, which makes the the
currently highest-perforance embedded SoC.
- TI AM62L is a new variant of the AM62 family of industrial SoCs,
this one comes without a GPU.
- Qualcomm MSM8937 (Snapdragon 430) is an older mobile phone chip
based on Cortex-A53, and closely related to MSM8917 (Snapdragn
425), which we already support.
In addition, there are a good number of newly supported machines
across SoC families:
- Two Aspeed AST2600 (Cortex-A7) based BMC setups for large servers
- Mobile Phones and tables based on Mediatek MT6582, Nvidia Tegra124,
Qualcomm MSM8937 and Qualcomm MSM8939,
- Two Laptops based on Qualcomm SoCs: one using the older sdm850, the
other using x1p42100.
- One Router based on Rockchips RK3568
- 24 variants of the Enclustra Mercury system-on-module, all based on
32-bit Intel/Altera SocFPGA chips, plus two boards using 64-bit
SocFPGA Agilex chips..
- 30 industrial/embedded boards and single-board computers, using
various chips from NXP, Rockchips, Mediatek, TI, Amlogic, Qualcomm,
Spacemit, and Starfive.
In total there are 783 commits here, the majority of these improving
hardware support and cleaning up devicetree files across the tree,
with the majority of the changes going into the Qualcomm, NXP, Renesas
and Rockchips platforms"
* tag 'soc-dt-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (782 commits)
arm64: dts: mediatek: mt8195: Fix address range for JPEG decoder core 1
ARM: dts: samsung: exynos4412-midas: turn off SDIO WLAN chip during system suspend
ARM: dts: samsung: exynos4210-trats: turn off SDIO WLAN chip during system suspend
ARM: dts: samsung: exynos4210-i9100: turn off SDIO WLAN chip during system suspend
ARM: dts: samsung: universal_c210: turn off SDIO WLAN chip during system suspend
arm64: dts: amlogic: meson-g12b: Fix L2 cache reference for S922X CPUs
arm64: dts: Add gpio_intc node for Amlogic S7D SoCs
arm64: dts: Add gpio_intc node for Amlogic S7 SoCs
arm64: dts: Add gpio_intc node for Amlogic S6 SoCs
arm64: dts: amlogic: s7d: add ao secure node
arm64: dts: amlogic: s7: add ao secure node
arm64: dts: amlogic: s6: add ao secure node
arm64: dts: amlogic: Fix the register name of the 'DBI' region
dts: arm64: amlogic: add a5 pinctrl node
arm64: dts: amlogic: s7d: add power domain controller node
arm64: dts: amlogic: s7: add power domain controller node
arm64: dts: amlogic: s6: add power domain controller node
dts: arm64: amlogic: Add ISP related nodes for C3
arm64: dts: meson: add initial device-tree for Tanix TX9 Pro
dt-bindings: arm: amlogic: add support for Tanix TX9 Pro
...
Enable AMD APML related features
- add amd sbrmi node for SoC power reading
- add amd sbtsi node for SoC temperature reading
- rename the P0_I3C_APML_ALERT_L GPIO to align with the naming
convention expected by the AMD APML tool
Signed-off-by: Fred Chen <fredchen.openbmc@gmail.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Add GPIO line name for userspace control or monitoring
- Add leak-related line names to report chassis leak event
- Add debug-card-mux to control debug card access
- Add FM_MAIN_PWREN_RMC_EN_ISO_R to receive RMC power control signal
Signed-off-by: Fred Chen <fredchen.openbmc@gmail.com>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
