mirror of
https://github.com/torvalds/linux.git
synced 2026-09-29 12:24:02 +02:00
master
809 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Linus Torvalds
|
c6cf4441a3 |
Devicetree updates for v7.3:
- Add a DT maintainer profile document - Various dt-check-style improvements - Add a devres managed reserved memory region init function - Print node name on any skipped reserved memory regions - Correctly handle optional argument in of_parse_phandle_with_args_map() - Convert ti,keystone-reset, ti,da850-vpif, TI L4 interconnect, TI SmartReflex, microchip,pic32mzda-dmt, microchip,pic32mzda-wdt, TI DA8XX MSTPRI bus, and Xen VM bindings to DT schema format - Add bindings for StarFive JHB100 plic, Allwinner A733 NMI controller, MediaTek MT8173 GPU, QCom Shikra, Eliza, and Maili cpu-bwmon, and QCom Shikra SCM firmware - A couple of syntax fixes found using PoC Rust implementation of dtschema tools - Clean-ups for typos, brackets, incorrect "::" usages, and white-space style -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAmqA0pYACgkQ+vtdtY28 YcOGLRAAsSVfV1r7n9SmPQ246dRQeVkNo3ZAEFuqqeBzJjMNyVyYn4iCcwkYDhaY rRlRpanmhbooUJfRRpxpgIv8XwWOiha8eq9mojnbGfgq00/8BEnD16A7bwNDaxsf /IUVKYQs8x7AK3nGLXvJ2BXQZzAZCnwylnsW6Pbkhns3xuc3lED4BGRRRsPH4T77 lMh2cA8JjeaY9sC/6aosTg1342nj+QpC2qJOfd2ONsWCKKD3zYAWWVFpj17J4o3d XDpLIjR1X6aOKoWOMDqmjnC/vwQ3Zzmz84zfArb4bl0O9A/ENQ1XYuNJ5tohxWd0 LfWMOD6dUIaquuoRUSvWrnafgSqumjTYzLZeK5KLDT2xqAnBO3sfizjFq9c4AHO8 TkU74DZiIGH2VCGCQtm7v5gZGbGKJ0g2TndCbQhEa/OyvaNfZpItGJWCHY3kg5xd Wn60sk1L/HnwItwGH47xxeksc1TiuhqH3zfr4ztj9fenUnuLtmkjdhu8wZGjpYFq 2Jf2KIUJov4WLN6cyP51vf5L1+OoaSfZ/6nuaO+9bAa/j+GQiZpRQI95yEOcXBd/ QbAL1tA8w9IRpN/bZ5l+Hw9ZO9Q1hpLTV92xqOPvVDXvDR7xi/7R4dvRm86m9IcT FTtNLLkz76V0DTqgHWfNtwxulYa69NrZjtD+VooVw1BWMo8ExmQ= =54fa -----END PGP SIGNATURE----- Merge tag 'devicetree-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: - Add a DT maintainer profile document - Various dt-check-style improvements - Add a devres managed reserved memory region init function - Print node name on any skipped reserved memory regions - Correctly handle optional argument in of_parse_phandle_with_args_map() - Convert ti,keystone-reset, ti,da850-vpif, TI L4 interconnect, TI SmartReflex, microchip,pic32mzda-dmt, microchip,pic32mzda-wdt, TI DA8XX MSTPRI bus, and Xen VM bindings to DT schema format - Add bindings for StarFive JHB100 plic, Allwinner A733 NMI controller, MediaTek MT8173 GPU, QCom Shikra, Eliza, and Maili cpu-bwmon, and QCom Shikra SCM firmware - A couple of syntax fixes found using PoC Rust implementation of dtschema tools - Clean-ups for typos, brackets, incorrect "::" usages, and white-space style * tag 'devicetree-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (40 commits) dt-bindings: interconnect: qcom-bwmon: Add Maili cpu-bwmon compatible dtc: dt-check-style: Simplify setting depth of DtsLine dtc: dt-check-style: Add missing /dts-v1/ to few test cases dt-bindings: power: reset: ti,keystone-reset: Convert to DT schema media: dt-bindings: ti,da850-vpif: Convert to dt-schema dt-bindings: devfreq: samsung,exynos-ppmu: Use standard regex syntax dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: Drop invalid JSON pointer dt-bindings: arm: omap: Convert L4 interconnect to DT schema dt-bindings: power: Convert TI SmartReflex to DT schema of: reserved_mem: Introduce devres-managed initialization function dt-bindings: interrupt-controller: Add StarFive JHB100 plic dt-bindings: irq: sun7i-nmi: Document the Allwinner A733 NMI controller dt-bindings: Correct white-space style dt-bindings: fix typos and brackets docs: dt: submitting-patches: Mention expectation about dt-check-style docs: dt: maintainer: Add Devicetree and OF maintainer profile document docs: dt: writing-schema: Extend expectations about example part of binding dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU of: base: Handle optional argument in of_parse_phandle_with_args_map() dt-bindings: update Sudeep Holla's email address ... |
||
|
Linus Torvalds
|
368cf60c36 |
soc: drivers for 7.3
The SoC driver changes once more consist of many small fixes and
cleanups, that are to a large part the result of automated testing. On
platform specific drivers, this includes SoC specific code for xilinx,
freescale/nxp, qualcomm, TI, aspeed, omap, tegra, samsung, rockchip,
renesas, ixp4xx. In firmware drivers, we see a similar picture for
SCMI and qcomtee.
Aside from these, we see actual new hardware support in a few
areas:
- The Apple platform gets a new driver for low power states
- Updates to Qualcomm platform drivers add several new
hardware specific features and additional SoCs.
- Amlogic SoC support for A1 and T7 is added
- The Mediatek MMSYS driver is refactored as a cleanup.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmqEtqAACgkQmmx57+YA
GNlpfQ//VD7d15DccC3OJCsG9s9vBF0Hd7etv8ceX3PWbIuLon8QBOR91/uJaaYd
33yWieJa3zNajOYqfNOAX7hD1N1UsXGmxJxpWcWlsfrhfXGiSctrQGxnOMdf0d6X
LLhWR5Q+7H9utKSFshFzdUA0aDDvsQhSBl/zmnC68+qd105XAddaPMXmw5jfDNNQ
6PO1f0iXwkkHel3Eq9EkNDomEWBndL7/s17f7IdRS0Sr+7iBp+Ey3ePG0sJ0MQBU
H7IifUfMr5GxfVhIM9yVmnvLH07OhNunJyzKhQkCiWQzFa/8biNhEvGH4kJ67Is0
XVB74chM/bo1EF6TVIY64ylpmCXPk5XWVwXZlhnwEI8npBFYrcSZJBAZ5vNUHMsT
2Rw4lCczQemFaBFVGzNw+8j8K7712Sm1yfiU2LlN871JfGYxpeaC9N6o+NB8Oikt
lS9fY8B3K2VzRM5w4Etp9SL3DPJ3N3LQ2gkCO0f/y+pu6n3IwrYGsJhocMOubcMn
ImkI+StNUtCizWUGhHqcsOlXIdyoYRXx+Ex3y6hk1QqBIPNQHdY1lfkCXHicbpxf
YVeUaelTGJp6mXFwx7Q10vD2679UyZYrMh4/cVsNskk1GlgDiiNCozVVdIa2/YnV
qQNyoAzwPupI9fhyoFSoSzblhrESgTPnuTc6Rkl9I0y4ki3cqVM=
=NeRc
-----END PGP SIGNATURE-----
Merge tag 'soc-drivers-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"The SoC driver changes once more consist of many small fixes and
cleanups, that are to a large part the result of automated testing.
On platform specific drivers, this includes SoC specific code for
xilinx, freescale/nxp, qualcomm, TI, aspeed, omap, tegra, samsung,
rockchip, renesas, ixp4xx. In firmware drivers, we see a similar
picture for SCMI and qcomtee.
Aside from these, we see actual new hardware support in a few areas:
- The Apple platform gets a new driver for low power states
- Updates to Qualcomm platform drivers add several new hardware
specific features and additional SoCs.
- Amlogic SoC support for A1 and T7 is added
- The Mediatek MMSYS driver is refactored as a cleanup"
* tag 'soc-drivers-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (157 commits)
soc: qcom: make QCOM_PDR_MSG selectable
soc: qcom: ubwc: Fix missing include
soc: qcom: ubwc: Fix link error when QCOM_SMEM=n
media: iris: Guard the QCOM_UBWC_CONFIG select with QCOM_SMEM
drm/msm: Guard the QCOM_UBWC_CONFIG select with QCOM_SMEM
dt-bindings: arm: qcom,ids: Add SoC ID for Snapdragon SDM 850
firmware: xilinx: Clear firmware notifiers across kexec transitions
firmware: xilinx: Release all peripheral devices from firmware
firmware: xilinx: Add support to clear EL3 PM state
firmware: xilinx: Propagate actual error from feature check
firmware: xilinx: Use TF-A feature check for TF-A-specific APIs
bus: fsl-mc: drop unused assignment of acpi_device_id::driver_data
soc: fsl: qe: check platform_driver_register() in qe_ic_of_init()
phy: lynx-10g: use RCW override procedure for dynamic protocol change
soc: fsl: guts: implement the RCW override procedure
dt-bindings: fsl: layerscape-dcfg: define DCFG_DCSR region
soc: fsl: guts: make fsl_soc_data available after fsl_guts_init()
soc: fsl: guts: make it easier to determine on which SoC we are running
soc: fsl: guts: add a central fsl_guts_read() function
soc: fsl: guts: add a global structure to hold state
...
|
||
|
Linus Torvalds
|
cbe8aadf15 |
soc: devicetree updates for 7.3
There are two new mystery SoCs with very little public information
about them so far, Qualcomm's Cortex-A78C based "Shikra" and
Altera's Cortex-A720 based Agilex72 SOCFPGA.
We have also gained support for a couple of SoCs from the
2023/2024 timeframe that have been in the making for a while:
- The Apple platform gains support for M3 Pro, Max and Ultra SoC,
following the basic M3 support from 7.2.
- Samsung Exynos 1580 is a high-end mobile phone SoC from 2024
- Canaan K230 is a RISC-V based 64-bit AI SoC, based on the
earlier K210 chip
- Sophgo SG2000 is a mixed Arm/RISC-V chip that was already
supported using the Arm core but is now also added for RISC-V
along with several other variants of the cv18xx series
In terms of newly added machines we have reference platforms
for all the chips above, plus
- only four 32-bit Arm boards: two older phones and two
older industrial/embedded boards; using Allwinner, Qualcomm and
Rockchip SoCs
- Three laptops und three phones using Qualcomm SoCs
- Ten 64-bit Rockchips based single-board computers, along with one
NAS box and a game console.
- Seven industrial/embedded boards and modules using NXP i.MX8/9 SoCs.
- A Lenovo desktop box based on NVIDIA Jetson Xavier NX
- A few more single-board computers based on Allwinnner A133,
Spacemit K1 and TI AM62.
As usual, there is a constant stream of minor cleanups and fixes
towards addressing the 'dt-check-style --mode strict' warnings,
and everyone is expected to address those warnings for new
submissions now.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmqDZaMACgkQmmx57+YA
GNkkiRAAusVNTkNVcpq+QGDhd6DfLd+d4vcvTJkBZ5WyJuqKs1qZPFIMQ0iMW1cY
hahBeYoowRX1oaB7KZc/MBE0IkOna35CEwiL6dm553xq+P208auqpNLpXTSKWsvx
jW4eYpdA6Bt6SM9J/583Ix71b5UFsLV+W3YKT2CBUZYn9yilAEz6kPa/Hxxa1Sia
3841Fdy6jcqusw1alzLQvrR7FxdtPFCs1f/a/GzBmZI7fxnj/cBwVghinSF9F0XW
BzDaUjMDzBYqSlMb7auNH0IpDeVuTx2Pch+YLrE8YVVPVf3nawd48ziwXO6zRsGx
HccLDuHpBqwnHsAh+bWi9UdxUSzjGW4KQ/W8Fj6O2SNqxPqrK2hyRYMp+76Tl65x
2diQOajmnZ4m8E5ToWsxpRxrlo6TKo33W63HglGIA24vr0gEi9FpA3kYiaWP2ZBD
qZz5xMeRmO1son1vtWX1CzsWFdogqBuGdztOyMoY4viSeY/ltT1EvIC0AiTIeSOt
krOFFDxwHvu+HOPJJ15VCVwEutUnGytB2nwBc/krhNS6MSlwg9DpY53RAhBxl0Jh
KXpPqBUpbl0Flty2rxdPx2EAt7MqeLTNXSSdzP7tvvumsT1Ik+zlPk+MkgLZ0Y5u
71fJrcij+0LeFDCzw81jGLoYSCw+9aNaELcF+OluL6rK8YFaBOE=
=RQan
-----END PGP SIGNATURE-----
Merge tag 'soc-dt-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"There are two new mystery SoCs with very little public information
about them so far, Qualcomm's Cortex-A78C based "Shikra" and Altera's
Cortex-A720 based Agilex72 SOCFPGA.
We have also gained support for a couple of SoCs from the 2023/2024
timeframe that have been in the making for a while:
- The Apple platform gains support for M3 Pro, Max and Ultra SoC,
following the basic M3 support from 7.2.
- Samsung Exynos 1580 is a high-end mobile phone SoC from 2024
- Canaan K230 is a RISC-V based 64-bit AI SoC, based on the earlier
K210 chip
- Sophgo SG2000 is a mixed Arm/RISC-V chip that was already supported
using the Arm core but is now also added for RISC-V along with
several other variants of the cv18xx series
In terms of newly added machines we have reference platforms for all
the chips above, plus
- Only four 32-bit Arm boards: two older phones and two older
industrial/embedded boards; using Allwinner, Qualcomm and Rockchip
SoCs
- Three laptops und three phones using Qualcomm SoCs
- Ten 64-bit Rockchips based single-board computers, along with one
NAS box and a game console.
- Seven industrial/embedded boards and modules using NXP i.MX8/9
SoCs.
- A Lenovo desktop box based on NVIDIA Jetson Xavier NX
- A few more single-board computers based on Allwinnner A133,
Spacemit K1 and TI AM62.
As usual, there is a constant stream of minor cleanups and fixes
towards addressing the 'dt-check-style --mode strict' warnings, and
everyone is expected to address those warnings for new submissions
now"
* tag 'soc-dt-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (864 commits)
Revert "riscv: dts: spacemit: k3: add i2s0-i2s5 nodes"
Documentation/process: maintainer-soc: Mention expectation about dt-check-style
ARM: dts: helios4: add SATA regulator supplies
ARM: dts: helios4: add vcc-supply to GPIO expander
ARM: dts: helios4: add vcc-supply to EEPROM
arm64: dts: turris-mox: fix usb3 phys
arm64: dts: ti: Correct white-space style
arm64: dts: ti: k3-am64: Fix MDIO clock reference for ICSSG0 node
arm64: dts: qcom: talos-evk: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
arm64: dts: qcom: sa8155p-adp: Fix swapped USB and UFS QMP PHY vdda-phy/vdda-pll supplies
arm64: dts: qcom: eliza-mtp: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
arm64: dts: qcom: lemans: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
arm64: dts: qcom: glymur: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
arm64: dts: qcom: kaanapali: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
arm64: dts: qcom: sar2130p: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
arm64: dts: qcom: sm8750: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
arm64: dts: qcom: sm8650: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
arm64: dts: qcom: purwa: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
arm64: dts: qcom: hamoa: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
arm64: dts: qcom: sc8180x: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
...
|
||
|
Rob Herring (Arm)
|
e8b51396b5 |
dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: Drop invalid JSON pointer
The $ref "arm,gic.yaml#/properties/#interrupt-cells" doesn't work when used with another json-schema implementation (rust). The issue is it not a valid URI due to the 2nd "#" character in the JSON pointer. Though a "#" is supposed to be valid within a JSON pointer. A possible solution is to encode the "#" as "%23" instead, but the dtschema tools don't handle that. Just avoid all these issues as the $ref only resolves to a "const: 3" schema and specify it directly. Link: https://patch.msgid.link/20260813145453.1919998-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
||
|
Ley Foon Tan
|
f423482666 |
dt-bindings: interrupt-controller: Add StarFive JHB100 plic
Add compatible string for StarFive JHB100 plic. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Link: https://patch.msgid.link/20260806122553.182449-3-changhuang.liang@starfivetech.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
||
|
Arnd Bergmann
|
e23817c994 |
Apple SoC DTS changes for 7.3
- Initial M3 Pro, Max and Ultra device trees, which are responsible for the majority of the diffstat. These include CPU cores, interrupt controller, power state, watchdog, serial pin/gpio controller, i2c and the boot framebuffer. They are now on par with the base M3 device trees. - HWMON sensors for M1/M2 - "pmgr-misc" nodes for M1/2 Pro/Max/Ultra which saves about 1W of power on these machines. The corresponding driver and dt-binding are part of the Apple SoC driver changes tag for this cycle. Signed-off-by: Sven Peter <sven@kernel.org> -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQS3vz815OHsEaWy0u9EEX0kKnUe6QUCanYC3AAKCRBEEX0kKnUe 6TjhAP48U0pnqD5rIzUKiXvrsf0kYgbUg4fuvxYTKAfTU2WXvgEApHwB/aS9W+EC AzBgYldnbJlVg5MhsBqG49l8+B7rPwo= =odXF -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmp5/PkACgkQmmx57+YA GNnWORAAlI7DAtGIPtoHaJNSQGVCyylEPgY23ZpIB6vraFnsBhHDdNY+sBEd1jI1 2M388XJmJ9dAbKf51pAAWiOtmW7TuuKclZWxekAZ37i+LBeL2E4034l/jLAR8ZHJ P37ogQlOpR7C/YOV2Ro4wQ3qST2OjjANOIYCzCp390ujzqsvBPPVo5U9sF+pVSCQ vHtXiPFck9CmxQAEfkg8XULhwc7NYLWg2aNtJ9YPmHI7+IGSjJgiXaX6JsZdPJwz tjCrOtCWJ3RVOT18vdD1TnDBQdrpk1yquGQkk/LMEZhqXAplprKdasqegdIvgUyC qXGZ62wiWKAg6QRlIQDCOw4Uj7mgjOeay83XgIOA+H4vRYd11SM0cMqaXlfn8DeH n0Wqt35X0/pNVIEUEIvCmPRdMw+qSAjr4JN005eEoG76Q4Ouaf9xvqvvbtnWWgql VYV5vSFKbkhhWuJcIwifB7d3eEk321dJHvdwuSpexLlFdM8nVu+1gHHeUn+VHBYC xXgv9K5ou8qvIeGHXqxFYoj6lvm1jwGijgc51ROHEfPuZmBDhr3Cin2H+I+imv6q +fc/aAX0MPoTgkdx9W/+qPZql73W+vmhlu0eYGbhSAOmtm68prrdDu6ckOaXVRbF w8lvAFd7Wa/RBulDZxieMzU/W6Z+FZ3BSBj4H1EqqfHrp7CoaPg= =azbS -----END PGP SIGNATURE----- Merge tag 'apple-soc-dt-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/dt Apple SoC DTS changes for 7.3 - Initial M3 Pro, Max and Ultra device trees, which are responsible for the majority of the diffstat. These include CPU cores, interrupt controller, power state, watchdog, serial pin/gpio controller, i2c and the boot framebuffer. They are now on par with the base M3 device trees. - HWMON sensors for M1/M2 - "pmgr-misc" nodes for M1/2 Pro/Max/Ultra which saves about 1W of power on these machines. The corresponding driver and dt-binding are part of the Apple SoC driver changes tag for this cycle. Signed-off-by: Sven Peter <sven@kernel.org> * tag 'apple-soc-dt-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux: (22 commits) arm64: dts: apple: Initial T6030 (M3 Pro) device trees arm64: dts: apple: Initial T603[124] (M3 Max and Ultra) device trees dt-bindings: pwm: apple,s5l-fpwm: Add t6030 and t6031 compatibles dt-bindings: i2c: apple,i2c: Add t6030 and t6031 compatibles dt-bindings: power: apple,pmgr-pwrstate: Add t6030 and t6031 compatibles dt-bindings: arm: apple: apple,pmgr: Add t6030 and t6031 compatibles dt-bindings: interrupt-controller: apple,aic2: Add apple,t6031-aic3 compatible dt-bindings: interrupt-controller: apple,aic2: Invert #interrupt-cells condition dt-bindings: arm: apple: Add M3 Pro/Max/Ultra devices (T603x) arm64: dts: apple: t60xx: jxxx: Add device-specific SMC hwmon sensors arm64: dts: apple: t8112: jxxx: Add device-specific SMC hwmon sensors arm64: dts: apple: t8103: jxxx: Add device-specific SMC hwmon sensors arm64: dts: apple: t602x: Add common SMC hwmon sensors arm64: dts: apple: t600x: Add common SMC hwmon sensors arm64: dts: apple: t8112: Add common SMC hwmon sensors arm64: dts: apple: t8103: Add common SMC hwmon sensors arm64: dts: apple: Add common SMC hwmon infrastructure arm64: dts: apple: t602x: Add SMC hwmon node arm64: dts: apple: t600x: Add SMC hwmon node arm64: dts: apple: t8103: Add SMC hwmon node ... Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Jerome Brunet
|
2bbb0e0334 |
dt-bindings: irq: sun7i-nmi: Document the Allwinner A733 NMI controller
The A733 NMI controller is compatible with the A523 one. Add an A733-specific compatible string, with the A523 as fallback. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260731-allwinner-a733-nmi-support-v1-1-61e4a0825b20@baylibre.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
||
|
Paul Louvel
|
890af4d046 |
dt-bindings: soc: fsl: qe: Set #interrupt-cells to 2 to support interrupt type encoding
The QUICC Engine port interrupt controller can be configured to generate an interrupt on either a high-to-low transition or any change in the signal state on the related GPIOs. Update the #interrupt-cells property to 2 so consumers can encode interrupt level information. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Paul Louvel <paul.louvel@bootlin.com> Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org> Link: https://lore.kernel.org/r/20260708-qe-pic-gpios-v2-2-1972044cfbd1@bootlin.com Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org> |
||
|
Janne Grunau
|
7869d82064 |
dt-bindings: interrupt-controller: apple,aic2: Add apple,t6031-aic3 compatible
The Apple M3 Max and Ultra SoCs use AICv3 as interrupt controller. It is compatible to the base M3 AICv3. Add "apple,t6031-aic3" as compatible and add it to the list for 4 #interrupt-cells used for multi-die SoCs. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Janne Grunau <j@jannau.net> Signed-off-by: Sven Peter <sven@kernel.org> |
||
|
Janne Grunau
|
7482c38040 |
dt-bindings: interrupt-controller: apple,aic2: Invert #interrupt-cells condition
The condition for 3 or 4 #interrupt-cells list compatibles for the 3
cells variant (not used in SoCs consisting out of multiple dies). This
includes the AICv3 base compatible "apple,t8122-aic3". This will match
compatible = "apple,t6031-aic3", "apple,t8122-aic3";
shared for M3 Max and Ultra based devices which require the additional
interrupt cell for the die number.
Instead list the compatibles used for multi-die SoCs explicitly and use
4 #interrupt-cells for them.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Janne Grunau <j@jannau.net>
Signed-off-by: Sven Peter <sven@kernel.org>
|
||
|
Arnd Bergmann
|
0bcfbb1f78 |
RISC-V devicetrees for v7.3 - early k230 material
Canaan: Support for the k230 SoC that was too late for the 7.2 window. Consists of some bindings not taken by the various subsystem maintainers, the original dts patches from Yangyu back in 2024 and the more recent clock, reset and pinctrl additions from various contributors. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCalE3fgAKCRB4tDGHoIJi 0tjdAQDTii/S9gka/j8cHfv3GGIEdMzGO6U+Y+c8IKp5W2S6BQEA/b62Eo2jBJUf D6hJ6K5POTzqoB6bw/VaKxVN2ssVSw4= =6yLO -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmpjksAACgkQmmx57+YA GNkjQg//b8WU1gJgM/n65o8ejebUaRER5sugfa7wqGpXL7MP/xXog+ij1+h8mVrS 6KWjfvkzFfYKrGIxWEqOH52swcDQqRwyIC6YGJ9y+qARtDNqHpk/GskashVaerE4 JuQQUF+Akq9ULoFWPFzdtibFTe+Abee7IP9fs0atmnMY/aToJdQRIpEKL1QnKM/i n8iO/+zNSIjD99Bi5CB4l89MnRAetbjKge8/havd533qEs91WqhnAtPUdehbZFJA 5upjsN8dzSnuqj7mf2tmL80hXx84ijkgkS7cxCyqTLYIh31yywtnvzExObMXn507 1Dy2WmKNaCPkvYFMb4Y5LkMBmGWAQaknCq4xQdMnPjCwcXjE/kJRFU4D9mTc2kNI Zom6K6WFQp4SAoYkaZXqk6UOjN0Chd5B1lW3dMbdMbeeCxx7tIjsI9+FN0eN26f1 94GRmn+E/Qm0973sfyJMZc7F9UDcV4Dm7cD5yn8oTCztaoRZSj09gYSDohAnt6CG 8K1vr93g6FotF0ANU2zljVtfQqXMJfPsemccK1GYcZzx3nuuT1cygK9lDYEzIxJC PytIi7K7hx1zRXN5/cLGKB0gXdmd0Onpj0MIUvOGphNjpfYRdc2J59xJ8jMvxXFl CYbd8m4RkMGAHZyOhkQwNtH0cE+zR+areE2TI3cETbL+HteP588= =ZTqc -----END PGP SIGNATURE----- Merge tag 'riscv-dt-for-v7.3-early-k230' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V devicetrees for v7.3 - early k230 material Canaan: Support for the k230 SoC that was too late for the 7.2 window. Consists of some bindings not taken by the various subsystem maintainers, the original dts patches from Yangyu back in 2024 and the more recent clock, reset and pinctrl additions from various contributors. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v7.3-early-k230' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: canaan: Add clock definition for K230 riscv: dts: canaan: add reset controller for K230 riscv: dts: canaan: k230: Add "b" ISA extension riscv: dts: canaan: Add k230's pinctrl node riscv: dts: canaan: Correct the formatting issues about k230 dts riscv: dts: add initial canmv-k230 and k230-evb dts dt-bindings: interrupt-controller: Add Canaan K230 PLIC dt-bindings: timer: Add Canaan K230 CLINT dt-bindings: add Canaan K230 boards compatible strings Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Markus Stockhausen
|
9d9faab6f5 |
dt-bindings: interrupt-controller: realtek,rtl-intc: Allow 2 interrupt cells
The Realtek Otto SoC interrupt controller supports hardware interrupt
routing to multiple parent CPU interrupt lines. To utilize this
multi-domain support, peripheral devices need a way to explicitly
specify their desired parent interrupt line in the device tree.
Update the "#interrupt-cells" property to accept either 1 or 2 cells.
1 cell: Specifies the hardware interrupt index, implicitly routing it
to the first available parent (maintaining backward compatibility).
2 cells: The first cell specifies the hardware interrupt index and
the second cell specifies the targeted parent interrupt index.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260605211646.2101652-2-markus.stockhausen@gmx.de
|
||
|
Linus Torvalds
|
09fb6892f3 |
Devicetree updates for v7.2:
DT core:
- Add support for handling multiple cells in "iommu-map" entries.
- Support only 1 entry in /reserved-memory "reg" entries. Support for
more than 1 entry has been broken.
- Fix a UAF on alloc_reserved_mem_array() failure
- Make "ibm,phandle" handling logic specific to PPC
- Use memcpy() instead of strcpy() for known length strings
- Ensure __of_find_n_match_cpu_property() handles malformed "reg"
entries
- Add various checks that expected strings are strings before accessing
them
- Drop redundant memset() when unflattening DT
DT bindings:
- Add a DTS style checker. Currently hooked up to dt_binding_check to
check examples.
- Convert st,nomadik platform, ti,omap-dmm, and ti,irq-crossbar
bindings to DT schema
- Add Apple System Management Controller hwmon, Qualcomm Hamoa Embedded
Controller, Qualcomm IPQ6018 PWM controller, fsl,mc1323, Samsung
SOFEF01-M DDIC panel, Freescale i.MX53 Television Encoder, Samsung S2M
series PMIC extcon, and MT6365 PMIC AuxADC schemas
- Extend bindings for QCom Maili and Nord PDC, QCom Hali fastrpc,
qcom,eliza-imem, qcom,oryon-1-5 CPU, and MT6365 Keys
- Consolidate "sram" property definitions
- Fix constraints on "nvmem" properties which only contain phandles and
no arg cells
- Another pass of fixing "phandle-array" constraints
- Add Gira vendor prefix
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAmoxvkAACgkQ+vtdtY28
YcMvzhAArPeBiRXPbA10csf2S9wtNuW5SX3rtPS4v87YMNstWpEW20ZGqwpFmns5
jzAvCjqlhMxpxH43eBM3GqaieU41GxCNGsveIyOnJeIK274hLk4p3kyJ2q6xOQYr
t2eC1NOiKFnIOM0ASXmIi5orzVnxHPLvcD9bdvcOWI/LMMK3loiY/CK5Cnps/ZaM
EbCWjxTD3JM+C9P2voaa2vEnpCW0w7Xc3ZXj8S1yxSyuILPcdKJikzP3l/LuEIrL
iy36q/9+JULMS8ooCN6VO0mZPYmB3DAraepHyJxO/hIJLVkO7O1SMIIcmukaRAbC
wf6RtdP498WagPxOOmocmh0k1pkAX4KFfqt9N13vKeUmLElWoaSbpp4v/YODlAr3
w6rSS3Z9Goh6m4ZwnyakENLJjqJdOcJcU9pJHA3EJmTSemChcpQ5GKMf5Sm2fI7O
nEtsuts+WfD+V2FR9qpHYEO6hNllsneJEk4RpSsHbfZorrQTLkDrJesahWsqKl76
wMM8ZWrZIs7vPouOim8LzFANL7myRH1wiJHHZIBCKC77sVNE78d0Bs5+Z118zEq1
eMGybSkbPfLiIYmDWnfnmrRL2+38R45mCzMGdCjhjBMtf0cF88e/TDgXwXiVhpIE
CcHr0COf0mOM+HZHUt23QPEhJZV93pxiXn4913LZfqh+FIAINyk=
=0d13
-----END PGP SIGNATURE-----
Merge tag 'devicetree-for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DT core:
- Add support for handling multiple cells in "iommu-map" entries
- Support only 1 entry in /reserved-memory "reg" entries. Support for
more than 1 entry has been broken
- Fix a UAF on alloc_reserved_mem_array() failure
- Make "ibm,phandle" handling logic specific to PPC
- Use memcpy() instead of strcpy() for known length strings
- Ensure __of_find_n_match_cpu_property() handles malformed "reg"
entries
- Add various checks that expected strings are strings before
accessing them
- Drop redundant memset() when unflattening DT
DT bindings:
- Add a DTS style checker. Currently hooked up to dt_binding_check to
check examples
- Convert st,nomadik platform, ti,omap-dmm, and ti,irq-crossbar
bindings to DT schema
- Add Apple System Management Controller hwmon, Qualcomm Hamoa
Embedded Controller, Qualcomm IPQ6018 PWM controller, fsl,mc1323,
Samsung SOFEF01-M DDIC panel, Freescale i.MX53 Television Encoder,
Samsung S2M series PMIC extcon, and MT6365 PMIC AuxADC schemas
- Extend bindings for QCom Maili and Nord PDC, QCom Hali fastrpc,
qcom,eliza-imem, qcom,oryon-1-5 CPU, and MT6365 Keys
- Consolidate "sram" property definitions
- Fix constraints on "nvmem" properties which only contain phandles
and no arg cells
- Another pass of fixing "phandle-array" constraints
- Add Gira vendor prefix"
* tag 'devicetree-for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (50 commits)
dt-bindings: interrupt-controller: qcom,pdc: Add Maili compatible string
dt-bindings: interrupt-controller: ti,irq-crossbar: Convert to DT schema
dt-bindings: vendor-prefixes: add Gira
dt-bindings: embedded-controller: Add Qualcomm reference device EC description
dt-bindings: pwm: add IPQ6018 binding
dt-bindings: hwmon: Add Apple System Management Controller hwmon schema
docs: dt: writing-schema: Clarify what is required in a schema
of: Respect #{iommu,msi}-cells in maps
of: Factor arguments passed to of_map_id() into a struct
of: Add convenience wrappers for of_map_id()
of: reserved_mem: zero total_reserved_mem_cnt if no valid /reserved-memory entry
of: reserved_mem: handle NULL name in of_reserved_mem_lookup()
dt-bindings: cache: l2c2x0: Add missing power-domains
dt-bindings: interrupt-controller: renesas,r9a09g077-icu: Fix reg size in example
dt-bindings: nvmem: consumer: Make 'nvmem' an array of one-item entries
drivers/of/overlay: Use memcpy() to copy known length strings
dt-bindings: add self-test fixtures for style checker
dt-bindings: wire style checker into dt_binding_check
scripts/jobserver-exec: propagate child exit status
dt-bindings: add DTS style checker
...
|
||
|
Linus Torvalds
|
aab799b1bd |
soc: devicetree updates for 7.2
There are fewer devicetree updates this time that the last few ones, with
five SoC types getting added:
- Qualcomm Dragonwing IPQ9650 is a new wireless networking SoC using
four Cortex-A55 and one Cortex-A78 core, which is a significant
upgrade from older generations
- ZTE zx297520v3 is an older low-end wireless SoC using a single
Cortex-A53 core, which so far can only run 32-bit kernels. This brings
back the ZX family of chips that was removed in 2021 after support
for the original zx296702 and zx296718 chips was never completed.
- Renesas R-Car M3Le (R8A779MD) is a variant of the R-Car M3-N (R8A77965)
automotive SoC.
- Apple t8122 (M3) is the 2023 generation of their laptop SoCs,
which has now been reverse-engineered to the point of having initial
kernel support for five laptop models.
- ASPEED AST27xx is their first baseboard managment controller using
a 64-bit core, the Cortex-A35, following earlier generations using
ARMv5/v6/v7 CPUs.
These all come with one or more initial boards, and in total there
are 39 new boards getting added across SoC families, including:
- Two NAS boxes using the old Cortina Systems Gemini SoC based on
an ARMv4 FA526 CPU core
- 18 industrial embedded boards using NXP i.MX6/8/9 and LX2160A
SoCs from Variscite, Toradex and SolidRun, plus a number of
overlays for combinations with additional boards
- One new carrier board and SoM using TI K3 AM62x, in addition to
new overlays for older SoMs
- Two new boards using Spacemit K3 (no relation with TI) RISC-V
SoCs.
- Three phones from Google, Nothing and Motorola, all using Qualcomm
Snapdragon SoCs
- AST26xx BMC support for two server boards
While there is still a significant number of patches improving hardware
support for the existing boards across vendors (NXP, Qualcomm, Renesas,
Rockchips, Mediatek, ...), a much smaller number of cleanups and warning
fixes have made it in this time.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmovyQ0ACgkQmmx57+YA
GNmE2hAAk4UguDtXr6fCYcIiBGqEtKhPmuvD98edmRyemg1x3ZbHIZn52rUqKFoz
HDi1BL7NkKdDuIWJ5DvqyHGLMg6kCEbiYSsjdkjN2Hcsx+I8NtokCR0hRtteNPQ9
f6kgDj9+VsWvXTsYKFU87qkK1bC5nVrLS7xxIuuCIYxULvSEX5GGJbHQ93qxNUam
6GrFcDHnozh9OfETSBw9bME16FiMxapgghPxMaAmVzuB+iGr4xyrEHmyu9gThsuJ
O2P04LIhu9j9CZOjaJ54+v41AtMIVE7xG1+MUC5JcWBc7OMVLE30uGgsW9jBKaii
Wsxa3D08+m1JYeFbhJR6tWAf4HbIEpudEoJmlSdwRhvYte15kU90f917aTNFYBow
sBf6G09t4ZLsDr9NzCx+cWUnoVLdlYv4auRGNxoWsxe4ed9G6c+yiZN2pBaFNXuT
wNJqrFstS9mszBaPItgt4e5Tck+IB0uKNqhbSWa3rFyKrXQ9SpZOKVN6cPlwFjhT
wWYZcAzUL8n2Sz71l/U/QqjN6hqnZWFghe9B3wr81/XQ4sPjWHWoTeRfnees+vFM
LtE77TGPW2KdZpRI38qfyKWWH3PwKaTtZ07ne8NOvh60zmhK+uUFGzzWAhKlO/Z2
a3tX8evXRTOb5NrvWzGlwpPwtE0R71oRIwxG1MlmFdlJzddI4Xc=
=EhYX
-----END PGP SIGNATURE-----
Merge tag 'soc-dt-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"There are fewer devicetree updates this time that the last few ones,
with five SoC types getting added:
- Qualcomm Dragonwing IPQ9650 is a new wireless networking SoC using
four Cortex-A55 and one Cortex-A78 core, which is a significant
upgrade from older generations
- ZTE zx297520v3 is an older low-end wireless SoC using a single
Cortex-A53 core, which so far can only run 32-bit kernels. This
brings back the ZX family of chips that was removed in 2021 after
support for the original zx296702 and zx296718 chips was never
completed.
- Renesas R-Car M3Le (R8A779MD) is a variant of the R-Car M3-N
(R8A77965) automotive SoC.
- Apple t8122 (M3) is the 2023 generation of their laptop SoCs, which
has now been reverse-engineered to the point of having initial
kernel support for five laptop models.
- ASPEED AST27xx is their first baseboard managment controller using
a 64-bit core, the Cortex-A35, following earlier generations using
ARMv5/v6/v7 CPUs.
These all come with one or more initial boards, and in total there are
39 new boards getting added across SoC families, including:
- Two NAS boxes using the old Cortina Systems Gemini SoC based on an
ARMv4 FA526 CPU core
- 18 industrial embedded boards using NXP i.MX6/8/9 and LX2160A SoCs
from Variscite, Toradex and SolidRun, plus a number of overlays for
combinations with additional boards
- One new carrier board and SoM using TI K3 AM62x, in addition to new
overlays for older SoMs
- Two new boards using Spacemit K3 (no relation with TI) RISC-V SoCs.
- Three phones from Google, Nothing and Motorola, all using Qualcomm
Snapdragon SoCs
- AST26xx BMC support for two server boards
While there is still a significant number of patches improving
hardware support for the existing boards across vendors (NXP,
Qualcomm, Renesas, Rockchips, Mediatek, ...), a much smaller number
of cleanups and warning fixes have made it in this time"
* tag 'soc-dt-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (665 commits)
arm64: dts: aspeed: Fix duplicate pinctrl labels and address scheme
arm64: dts: bst: enable eMMC controller in C1200
dt-bindings: display/lvds-codec: add ti,sn65lvds93
arm64: dts: allwinner: a523: Add missing GPIO interrupt
arm64: dts: lx2160a-rev2: avoid 32-bit pcie window system ram overlap
arm64: dts: aspeed: Add initial AST27xx SoC device tree
arm64: Kconfig: Add ASPEED SoC family Kconfig support
dt-bindings: arm: aspeed: Add AST2700 board compatible
arm64: dts: allwinner: a523: add gpadc node
arm64: dts: allwinner: Add EL2 virtual timer interrupt
ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node
dt-bindings: media: sun6i-a31-isp: Add optional interconnect properties
dt-bindings: media: sun6i-a31-csi: Add optional interconnect properties
arm64: dts: imx{91,93}-phyboard-segin: Add peb-av-18 overlays
arm64: dts: imx93-var-som-symphony: enable ADC
arm64: dts: imx93-var-som-symphony: enable TPM3 PWM
arm64: dts: imx93-var-som-symphony: keep RGB_SEL low
arm64: dts: imx93-var-som-symphony: enable UART7
arm64: dts: imx93-var-som-symphony: add TPM support
arm64: dts: imx91-var-som-symphony: fix RGB_SEL handling
...
|
||
|
Yijie Yang
|
faa25db089 |
dt-bindings: interrupt-controller: qcom,pdc: Add Maili compatible string
Register qcom,maili-pdc as a supported compatible string for the Qualcomm PDC interrupt controller binding. Signed-off-by: Yijie Yang <yijie.yang@oss.qualcomm.com> Link: https://patch.msgid.link/20260615-maili-pdc-v1-1-add21e8eec3e@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
||
|
Bhargav Joshi
|
b417b241df |
dt-bindings: interrupt-controller: ti,irq-crossbar: Convert to DT schema
Convert TI irq-crossbar binding from text format to DT schema. As part of conversion following changes are made: - Add '#interrupt-cells' as a required property which was missing in text binding - As irq-crossbar is interrupt-controller. Move binding from bindings/arm/omap to bindings/interrupt-controller Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com> Link: https://patch.msgid.link/20260612-crossbar-v3-1-266747bc2e86@gmail.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
||
|
Yangyu Chen
|
85dca15595 |
dt-bindings: interrupt-controller: Add Canaan K230 PLIC
Add compatible string for Canaan K230 PLIC. Signed-off-by: Yangyu Chen <cyy@cyyself.name> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Guo Ren <guoren@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
Geert Uytterhoeven
|
8e45719acd |
dt-bindings: interrupt-controller: renesas,r9a09g077-icu: Fix reg size in example
According to Figure 5.1 ("Unified memory map"), the safety register
block is 64 KiB large, just like the non-safety register block.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/364ff570c8a1845fab24bd89557f06c9e406f8de.1781105007.git.geert+renesas@glider.be
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
|
||
|
Joshua Milas
|
972e8823d9 |
dt-bindings: soc: sophgo: add sg2000 plic and clint documentation
Document the compatible strings for the sg2000 interrupt controller and timer. Signed-off-by: Joshua Milas <josh.milas@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260530173347.33533-4-josh.milas@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> |
||
|
Shawn Guo
|
8a09903a29 |
dt-bindings: interrupt-controller: Document PDC for Qualcomm Nord SoC
Document Power Domain Controller on Qualcomm Nord SoC. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260504080703.825328-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
||
|
Caleb James DeLisle
|
02bea6ff68 |
dt-bindings: interrupt-controller: econet: Add CPU interrupt mapping
In MIPS VEIC mode (Vectored External Interrupt Controller), the hardware stops directly dispatching CPU interrupts such as IPIs or CPU performance counters, and instead it communicates them to the external interrupt controller (the hardware described here) which prioritizes, renumbers, and integrates them with its own hardware interrupt pins. Interrupts from the external controller are then dispatched through a different method via a dispatch table. In effect, the external controller subsumes the CPU controller and becomes the root. 34K Manual (MD00534) Section 6.3.1.3 rev 1.13 page 136 Since there are interrupts which ought to be controlled by the CPU controller driver - particularly the IPI interrupts - we create a reverse mapping where those interrupts may be sent back to the CPU intc when they are received. This maintains the fiction that there is still a hierarchy, and keeps the DT the same no matter whether the processor is in VEIC mode or not. The econet,cpu-interrupt-map is optional and if omitted, it's assumed that no interrupts need to be mapped. Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260430164157.6026-2-cjd@cjdns.fr |
||
|
Xianwei Zhao
|
f51c99a0e5 |
dt-bindings: interrupt-controller: Add support for Amlogic A9 SoCs
Update dt-binding document for GPIO interrupt controller of Amlogic A9 SoCs. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260508-a9-gpio-irqchip-v1-2-9dc5f3e022e0@amlogic.com |
||
|
Changhuang Liang
|
a540d544db |
dt-bindings: interrupt-controller: Repurpose binding for unreleased jh8100 for jhb100
The StarFive JH8100 SoC was discontinued before production. The newly taped-out JHB100 SoC uses the same interrupt controller IP. Rename the binding file, compatible string, and MAINTAINERS entry from "jh8100" to "jhb100". In JHB100 SoC, The clocks and resets are not operated by users, but they exist in the hardware. Mark them as optional. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260416064751.632138-2-changhuang.liang@starfivetech.com |
||
|
Ryan Chen
|
51561ad8c8 |
dt-bindings: interrupt-controller: Describe AST2700-A2 hardware instead of A0
Introduce a new binding describing the AST2700 interrupt controller
architecture implemented in the A2 production silicon.
The AST2700 SoC has undergone multiple silicon revisions (A0, A1, A2)
prior to mass production. The interrupt architecture was substantially
reworked after the A0 revision for A1, and the A1 design is retained
unchanged in the A2 production silicon.
The existing AST2700 interrupt controller binding ("aspeed,ast2700-intc-ic")
was written against the pre-production A0 design.
That binding does not accurately describe the interrupt hierarchy and
routing model present in A1/A2, where interrupts can be routed to multiple
processor-local interrupt controllers (Primary Service Processor (PSP) GIC,
Secondary Service Processor (SSP)/Tertiary Service Processor (TSP) NVICs,
and BootMCU APLIC) depending on the execution context.
Remove the binding for the pre-production A0 design in favour of the
binding for the A2 production design. There is no significant user
impact from the removal as there are no existing devicetrees in any
of Linux, u-boot or Zephyr that make use of the A0 binding.
Hardware connectivity between interrupt controllers is expressed using
the aspeed,interrupt-ranges property.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260407-irqchip-v5-1-c0b0a300a057@aspeedtech.com
|
||
|
Linus Torvalds
|
e2d10998e4 |
Devicetree updates for v7.1:
DT core:
- Cleanup of the reserved memory code to keep CMA specifics in CMA code
- Add and convert several users to new of_machine_get_match() helper
- Validate nul termination in string properties
- Update dtc to upstream v1.7.2-69-g53373d135579
- Limit matching reserved memory devices to /reserved-memory nodes
- Fix some UAF in unittests
- Remove Baikal SoC bus driver
- Fix false DT_SPLIT_BINDING_PATCH checkpatch warning
- Allow fw_devlink device-tree on x86
- Fix kerneldoc return description for of_property_count_elems_of_size()
DT bindings:
- Add fsl,imx25-aips, fsl,imx25-tcq, qcom,eliza-pdc,
qcom,eliza-spmi-pmic-arb, qcom,hawi-imem, qcom,milos-imem,
qcom,hawi-pdc, and lg,sw49410 bindings
- Convert arm,vexpress-scc to DT schema
- Deprecate Qualcomm generic CPU compatibles. Add Apple M3 CPU cores.
- Move some dual-link display panels to the dual-link schema
- Drop mux controller node name constraints
- Remove Baikal SoC bus bindings
- Fix a false warning in the thermal trip node binding
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAmnhBKQACgkQ+vtdtY28
YcO7iw//ZHGjSI4WTwwtthgBsn108x0iRMpo3d8rYN6ESDEIgXELbEDFzWSbIzBB
yCWUUmbNzv1YcwUF+XOoiQzdMZP6GdSTL/vvj3KgRPDgkOgNlnEgxJEPyC1mbUf5
oJ5S/f8sr1+hfFp6LJiDnZTU6RcJHZSsLlwW4GfA87hjHCun8lQSfP+E4x1RyS4s
6+LA+mYQNk0OFfqmE/w/Jqn44nHqoduD3Ay/I/5sd8YECtowiI9ZZ+85GkYPtDFa
R5pW4eSoffYr5vXDTdCyBARSUxUcm++yIB/yAgi5B4xQCEKK5ds7M6YL0ylGXdey
8ezINGXHhFsc40e4Gp/13m6/jYy322PF6kEeUWb63uZ0djJMxba7SFmEAUs00zme
UQ8irtGay80tgRnS9btRChKFOqKcXFr5bsN5L6tkVdoJMTAziz7B77fwo7W+x+7b
MTdlUfFMupuQJWETte9o04TkGZ5/tqnlcbpF/iTws3vCyeFyZ0LWHueQpSwhO2oy
wzdDZ1VLHATPdVlGV757yfH9O8BkyHtdG8lXVLLoR0C1JOqUlyfScGxfLFwawUC8
cERw9bU4f2IT+lJbr5WqpG+BnQ6TnwoNOvqajXHAByDQ/Gd8MLZoX91ykZflaWxQ
EIvXVytWdwmQ4iReD+9ETPHBXC8v3W4+hkqrJxCAqVHPxBkXS40=
=Ia0F
-----END PGP SIGNATURE-----
Merge tag 'devicetree-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DT core:
- Cleanup of the reserved memory code to keep CMA specifics in CMA
code
- Add and convert several users to new of_machine_get_match() helper
- Validate nul termination in string properties
- Update dtc to upstream v1.7.2-69-g53373d135579
- Limit matching reserved memory devices to /reserved-memory nodes
- Fix some UAF in unittests
- Remove Baikal SoC bus driver
- Fix false DT_SPLIT_BINDING_PATCH checkpatch warning
- Allow fw_devlink device-tree on x86
- Fix kerneldoc return description for of_property_count_elems_of_size()
DT bindings:
- Add fsl,imx25-aips, fsl,imx25-tcq, qcom,eliza-pdc,
qcom,eliza-spmi-pmic-arb, qcom,hawi-imem, qcom,milos-imem,
qcom,hawi-pdc, and lg,sw49410 bindings
- Convert arm,vexpress-scc to DT schema
- Deprecate Qualcomm generic CPU compatibles. Add Apple M3 CPU cores.
- Move some dual-link display panels to the dual-link schema
- Drop mux controller node name constraints
- Remove Baikal SoC bus bindings
- Fix a false warning in the thermal trip node binding"
* tag 'devicetree-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (39 commits)
dt-bindings: display: panel: panel-simple: Add lg,sw49410 compatible
dt-bindings: display: ti, am65x-dss: Fix AM62L DSS reg and clock constraints
dt-bindings: display: simple: Move Innolux G156HCE-L01 panel to dual-link
dt-bindings: display: simple: Move AUO 21.5" FHD to dual-link
dt-bindings: thermal: Fix false warning with 'phandle' in trips nodes
of: unittest: fix use-after-free in testdrv_probe()
of: unittest: fix use-after-free in of_unittest_changeset()
dt-bindings: qcom,pdc: document the Hawi Power Domain Controller
dt-bindings: ARM: arm,vexpress-scc: convert to DT schema
drivers/of: fdt: validate flat DT string properties before string use
drivers/of: fdt: validate stdout-path properties before parsing them
dt-bindings: sram: Document qcom,hawi-imem compatible
dt-bindings: sram: Allow multiple-word prefixes to sram subnode
dt-bindings: sram: Document qcom,milos-imem
scripts/dtc: Update to upstream version v1.7.2-69-g53373d135579
of: property: Allow fw_devlink device-tree on x86
dt-bindings: arm: cpus: Add Apple M3 CPU core compatibles
dt-bindings: display: lt8912b: Drop redundant endpoint properties
dt-bindings: opp-v2: Fix example 3 CPU reg value
dt-bindings: connector: add pd-disable dependency
...
|
||
|
Linus Torvalds
|
31b43c079f |
soc: drivers for 7.1
The driver updates again are all over the place with many minor fixes
going into platform specific code. The most notable changes are:
- Support for Microchip pic64gx system controllers
- Work on cleaning up devicetree bindings for SoC drivers, and
converting them into the new format
- Lots of smaller changes for Qualcomm SoC drivers, including support
for a number of newly supported chips
- reset controller API cleanups and a new driver for Cix Sky1
- Reworks of the Tegra PMC and CBB drivers, along with a change
to how individual Tegra SoCs get selected in Kconfig and
BPMP firmware driver updates including a refresh of the ABI
header to match the version used by firmware
- STM32 updates to the firewall bus driver and support for
the debug bus through OP-TEE
- SCMI firmware driver improvements for reliability, in particular
for dealing with broken firmware interrupts
- Memory driver updates for Tegra, and a patch to remove the
unused Baikal T1 driver
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmnhCSYACgkQmmx57+YA
GNl2ow/+Pti7qbBE34WNyIuWOgZEzjo1OeLe/Y4LqkQmHcM9FJV3/rCadA/FkmD9
nH85WiRuUjIjzUiAl24SP2nkEcIU/yv8ECvROX46uAjhTByVHkaCedwl3ECW9RPA
IAYiTJPrQBNCmWZuGO4bZ3go6hHn4q4RSd2V8vrCw/J3b+wBSAPTPzsaWnWg4MiL
QYz7sBTwcNJaJuwJ7ZnHN/VgEOs9OgY6ejGJImiaVzBbsH7rNp7Cbs6t88X5rCXS
mbgMvVlYKbsOWj3kNyv98YFAGgzo59uEL+m+846U32w9o0nIgkmIS60RQ5k73JV4
QlhV1uT7PPtu7y7VbxfJ8KISxaRoex/+AZShmAWCul4YK75hEWT3mWGhM8cqeMUQ
U0ogpbekRjKdn2Bgfl6kHf38smusjJ1fOBr8QIZcdDJpEtxYtRmNpLUNNSc5vO+T
HvA79C8I8ydWGyqr1wRP1gDRBNc1BDYKxJO4ohvjnAPIeC01zArXCOyf0F3VtPzH
XSycnyW7eRUVi+4C3/cF8qzhW2y7Wx03ui5mCDIEcOzyVoGNqTrPNsbCvkNkyrdc
jqvWagZ4Ci8jaRxLAawnqHI/stvsHx9V+NPp6p07BsOxJMsuOqO4sInRhh5P6YvM
5wZCFUK37xPEqYvr+BFS9B/4jgw3Mg2Kj+gjxShwsLS5JtVDfZw=
=UB4F
-----END PGP SIGNATURE-----
Merge tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"The driver updates again are all over the place with many minor fixes
going into platform specific code. The most notable changes are:
- Support for Microchip pic64gx system controllers
- Work on cleaning up devicetree bindings for SoC drivers, and
converting them into the new format
- Lots of smaller changes for Qualcomm SoC drivers, including support
for a number of newly supported chips
- reset controller API cleanups and a new driver for Cix Sky1
- Reworks of the Tegra PMC and CBB drivers, along with a change to
how individual Tegra SoCs get selected in Kconfig and BPMP firmware
driver updates including a refresh of the ABI header to match the
version used by firmware
- STM32 updates to the firewall bus driver and support for the debug
bus through OP-TEE
- SCMI firmware driver improvements for reliability, in particular
for dealing with broken firmware interrupts
- Memory driver updates for Tegra, and a patch to remove the unused
Baikal T1 driver"
* tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (193 commits)
firmware: arm_ffa: Use the correct buffer size during RXTX_MAP
firmware: qcom: scm: Allow QSEECOM on Lenovo IdeaCentre Mini X
clk: spear: fix resource leak in clk_register_vco_pll()
reset: rzv2h-usb2phy: Add support for VBUS mux controller registration
reset: rzv2h-usb2phy: Convert to regmap API
dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/G3E USB2PHY reset
dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property
soc: microchip: add mpfs gpio interrupt mux driver
dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux
gpio: mpfs: Add interrupt support
soc: qcom: ubwc: add helpers to get programmable values
soc: qcom: ubwc: add helper to get min_acc length
firmware: qcom: scm: Register gunyah watchdog device
soc: qcom: socinfo: Add SoC ID for SA8650P
dt-bindings: arm: qcom,ids: Add SoC ID for SA8650P
firmware: qcom: scm: Allow QSEECOM on Mahua CRD
soc: qcom: wcnss: simplify allocation of req
soc: qcom: pd-mapper: Add support for Eliza
soc: qcom: aoss: compare against normalized cooling state
soc: qcom: llcc: fix v1 SB syndrome register offset
...
|
||
|
Mukesh Ojha
|
e9cd85a426 |
dt-bindings: qcom,pdc: document the Hawi Power Domain Controller
Document the Power Domain Controller on the Qualcomm Hawi SoC. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Link: https://patch.msgid.link/20260401125004.592925-1-mukesh.ojha@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
||
|
Krzysztof Kozlowski
|
d7dbdadad2 |
dt-bindings: Changes for v7.1-rc1
This contains a few conversions to DT schema along with various additions and fixes to reduce the amount of validation warnings. Included are also a new binding for the PCIe controller found on Tegra264 as well as compatible strings for the Jetson AGX Thor Developer Kit. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmnI8ZAACgkQ3SOs138+ s6G1lRAAvALxbMaizOUtlOjsPQOuE6OJ9VqeueLfMWI8YJuDf+OOC4IFtwbZxzeW ft28k8Ni4XLfOJVHuBN3ZyD04nudaIRQFyAW9ERdHLZDeyIaiq1y+aMH+YPdAp+i DPtKqLR+iAQ17rLokyIotHFGApFZghAd9ln1ZYZc9aOi9ZwrVQ3WEitbW36DJcMH 7WH7nxrf04vblv8DHZcu8p5DH9RmoU3qHxRteprwtiYX/ruwjD5KHOQLo2j+flZx YMayxN/lO3kVXQ0A65+t5nV4jevEQ4iTjtwjs0cps+xkXavcOO/SYhlqRjg5wbCv 1uLwS/ptjB3S+hD58jvqLfCUxLXvRx0xpBm5Vhs5eZgL0BPWT3O755Qow4zraDve ofGNbwA2SubVI2hgE/ZVPCU0X0mr89st16gWlflVeopJJk2kNAsfPUlCERPqbj+I +wuz8K1lfiBTkEw8Ceym2VEAH6D1MhkqnErwk9aW9yuYuXB9NtOjTxy/dELMHpFd Gt3BQxYug/xjV/FCtYj5x/lqkXZWsa4uBxilXzf84ScRa5NqfrwyLY1KBaRNOIch NlB4Bm0QhfBCXcTNeYF6XjIc6cIL83vCQK7hvBh9yEX3Ln+FBiqzF7jt1ZNdnm34 NzWOoPMh9FumoYxywmN1/oco9TOLebYGqszwG8jORBQG0YAwrEQ= =oPQj -----END PGP SIGNATURE----- Merge tag 'tegra-for-7.1-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers dt-bindings: Changes for v7.1-rc1 This contains a few conversions to DT schema along with various additions and fixes to reduce the amount of validation warnings. Included are also a new binding for the PCIe controller found on Tegra264 as well as compatible strings for the Jetson AGX Thor Developer Kit. * tag 'tegra-for-7.1-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: arm: tegra: Document Jetson AGX Thor DevKit dt-bindings: display: tegra: Document Tegra20 HDMI port dt-bindings: arm: tegra: Add Tegra238 CBB compatible strings dt-bindings: memory: tegra210: Mark EMC as cooling device dt-bindings: memory: Add Tegra210 memory controller bindings dt-bindings: phy: tegra: Document Tegra210 USB PHY dt-bindings: arm: tegra: Add missing compatible strings dt-bindings: interrupt-controller: tegra: Fix reg entries dt-bindings: clock: tegra124-dfll: Convert to json-schema dt-bindings: phy: tegra-xusb: Document Type C support dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> |
||
|
Thierry Reding
|
cafacd15e8 |
dt-bindings: interrupt-controller: tegra: Fix reg entries
Tegra210 takes exactly 6 "reg" property entries, as opposed to Tegra30 which supports only 5 entries. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> |
||
|
Ciprian Marian Costea
|
0b7973dfb7 |
dt-bindings: interrupt-controller: fsl,irqsteer: add S32N79 support
Add compatible string for the interrupt steering controller used in NXP S32N79 SoC. The S32N79 SoC differs from the i.MX version by not implementing the CHANCTRL register, but otherwise maintains the same programming model and register layout. Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> |
||
|
Biju Das
|
3aa78b828e |
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L SoC
Document RZ/G3L (R9A08G046) IRQC. The IRQC block on the RZ/G3L SoC is nearly identical to that found on the RZ/G3S SoC, with the following differences: it supports more external interrupts and GPT error interrupts, and adds registers for GPT/MTU interrupt selection and shared interrupt selection between external interrupt and TINT. A new compatible string "renesas,r9a08g046-irqc" is therefore introduced for the RZ/G3L SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260325192451.172562-3-biju.das.jz@bp.renesas.com |
||
|
Biju Das
|
7b7d32d93e |
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for interrupt-names
Simplify the bindings by using pattern property for interrupt-names. It also allows to change the ordering of interrupts. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260325192451.172562-2-biju.das.jz@bp.renesas.com |
||
|
Icenowy Zheng
|
41bf87bcac |
dt-bindings: interrupt-controller: Add LS7A PCH LPC
Loongson 7A series PCH contains an LPC controller with an interrupt controller. Add the device tree binding for the interrupt controller. Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260321092032.3502701-4-zhengxingda@iscas.ac.cn |
||
|
Geert Uytterhoeven
|
15cfc8984d |
dt-bindings: interrupt-controller: arm,gic-v3: Fix EPPI range
According to the "Arm Generic Interrupt Controller (GIC) Architecture
Specification, v3 and v4", revision H.b[1], there can be only 64
Extended PPI interrupts.
[1] https://developer.arm.com/documentation/ihi0069/hb/
Fixes:
|
||
|
Janne Grunau
|
0db190e68b |
dt-bindings: interrupt-controller: apple,aic2: Add AICv3
AIC version 3 as found on the Apple M3 (t8122) is very similar to AICv2 in its base functionality. It can use the same device tree bindings as AICv2 so add it to the AICv2 bindings. This interrupt controller is used on all Apple SoCs starting with M3 up to at least M5. The only apparent difference is the increased IRQ config offset. Apple's device tree codes this new offset as property of the "aic" node but the value stayed constant for all SoCs with "aic,3". Since the SoC specific compatible "apple,t8122-aic3" will be only used in the driver this offset can remain a driver implementation detail. Signed-off-by: Janne Grunau <j@jannau.net> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260223-irq-apple-aic3-v3-1-2b7328076b8d@jannau.net |
||
|
Abel Vesa
|
389a820af0 |
dt-bindings: qcom,pdc: document the Eliza Power Domain Controller
Document the Power Domain Controller on the Qualcomm Eliza SoC. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260223-eliza-pdc-v1-1-fcb17464fee2@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
||
|
Linus Torvalds
|
098b6e44cb |
Devicetree updates for v7.0:
DT core:
- Sync dtc/libfdt with upstream v1.7.2-62-ga26ef6400bd8
- Add a for_each_compatible_node_scoped() loop and convert users in
cpufreq, dmaengine, clk, cdx, powerpc and Arm
- Simplify of/platform.c with scoped loop helpers
- Add fw_devlink tracking for "mmc-pwrseq"
- Optimize fw_devlink callback code size for pinctrl-N properties
- Replace strcmp_suffix() with strends()
DT bindings:
- Support building single binding targets
- Convert google,goldfish-fb, cznic,turris-mox-rwtm, ti,prm-inst
- Add bindings for Freescale AVIC, Realtek RTD1xxx system controllers,
Microchip 25AA010A EEPROM, OnSemi FIN3385, IEI WT61P803 PUZZLE, Delta
Electronics DPS-800-AB power supply, Infineon IR35221 Digital
Multi-phase Controller, Infineon PXE1610 Digital Dual Output 6+1
VR12.5 & VR13 CPU Controller, socionext,uniphier-smpctrl, and
xlnx,zynqmp-firmware
- Lots of trivial binding fixes to address warnings in DTS files. These
are mostly for arm64 platforms which is getting closer to be warning
free. Some public shaming has helped.
- Fix I2C bus node names in examples
- Drop obsolete brcm,vulcan-soc binding
- Drop unreferenced binding headers
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAmmNLZEACgkQ+vtdtY28
YcPa+A/+Lpf1FLau//mfndvkzRUvuU5aF3eJdL1FPxfC64Js2cb9ZGSoEK+YDjaV
XzNIi2Z1j+i4+uf5MTvyGaqaVx3PcQBcQtb7pu+W1pt2KiOzfVqn66EmRsY3b4cc
twyOwx2sZMTOZambUfZreWwEl6uJiMowIbcLCsnVWihoiGVTnMpnV/jLcO9jISaP
fe42FX9qN4NL2QqWwcREYuWMuOH7MkHDRNpEhTouWosdmFCp3PkVZcuWv3NKjGMg
/tsH5X9QMr972A9s8Zk36ijvTv7NN+9t1GOtPS9KGpbwJmyPHr38mG1fsj+P0rY7
rOXRnT2PScN6kvKZuw0Rex5xeMxrQCzRkFLzyfq2LOsE0GAUyyR3qysNOdH8xO3Z
3TVMGVaelYw5T+ahie1+gf/H/t+8hGhX3teCo8ORFNYo7oLsA9qNclfd5SW2Acat
pPK80PXkqTRsQ9lVGfytPZJ+m5OhcTIBdI9ieEXk/kryDAL4dHcB2IIVHM2/qm50
aGW0Kh0d61Roe0PZ5GEqI/yWPVHZroXEBxT61tDKwPyGawcq4Gs3Sftd6RXbLi8h
+T6HzkHPZFlKaiLmBC1wqXnEKLd8h72qNjjDdXbRBdLXW6S5hGPtPiLv18ArlmmR
4eiFX1Tr+pUAt2W/IwZb9H84mGkbJODbI62x9k9rst/vLeHmnjs=
=RE7t
-----END PGP SIGNATURE-----
Merge tag 'devicetree-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DT core:
- Sync dtc/libfdt with upstream v1.7.2-62-ga26ef6400bd8
- Add a for_each_compatible_node_scoped() loop and convert users in
cpufreq, dmaengine, clk, cdx, powerpc and Arm
- Simplify of/platform.c with scoped loop helpers
- Add fw_devlink tracking for "mmc-pwrseq"
- Optimize fw_devlink callback code size for pinctrl-N properties
- Replace strcmp_suffix() with strends()
DT bindings:
- Support building single binding targets
- Convert google,goldfish-fb, cznic,turris-mox-rwtm, ti,prm-inst
- Add bindings for Freescale AVIC, Realtek RTD1xxx system
controllers, Microchip 25AA010A EEPROM, OnSemi FIN3385, IEI
WT61P803 PUZZLE, Delta Electronics DPS-800-AB power supply,
Infineon IR35221 Digital Multi-phase Controller, Infineon PXE1610
Digital Dual Output 6+1 VR12.5 & VR13 CPU Controller,
socionext,uniphier-smpctrl, and xlnx,zynqmp-firmware
- Lots of trivial binding fixes to address warnings in DTS files.
These are mostly for arm64 platforms which is getting closer to be
warning free. Some public shaming has helped.
- Fix I2C bus node names in examples
- Drop obsolete brcm,vulcan-soc binding
- Drop unreferenced binding headers"
* tag 'devicetree-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (60 commits)
dt-bindings: interrupt-controller: Add compatiblie string fsl,imx(1|25|27|31|35)-avic
dt-bindings: soc: imx: add fsl,aips and fsl,emi compatible strings
dt-bindings: display: bridge: lt8912b: Drop reset gpio requirement
dt-bindings: firmware: fsl,scu: Mark multi-channel MU layouts as deprecated
cpufreq: s5pv210: Simplify with scoped for each OF child loop
dmaengine: fsl_raid: Simplify with scoped for each OF child loop
clk: imx: imx31: Simplify with scoped for each OF child loop
clk: imx: imx27: Simplify with scoped for each OF child loop
cdx: Use mutex guard to simplify error handling
cdx: Simplify with scoped for each OF child loop
powerpc/wii: Simplify with scoped for each OF child loop
powerpc/fsp2: Simplify with scoped for each OF child loop
ARM: exynos: Simplify with scoped for each OF child loop
ARM: at91: Simplify with scoped for each OF child loop
of: Add for_each_compatible_node_scoped() helper
dt-bindings: Fix emails with spaces or missing brackets
scripts/dtc: Update to upstream version v1.7.2-62-ga26ef6400bd8
dt-bindings: crypto: inside-secure,safexcel: Mandate only ring IRQs
dt-bindings: crypto: inside-secure,safexcel: Add SoC compatibles
of: reserved_mem: Fix placement of __free() annotation
...
|
||
|
Linus Torvalds
|
6589b3d76d |
soc: devicetree updates for 7.0
There are a handful of new SoCs this time, all of these are
more or less related to chips in a wider family:
- SpacemiT Key Stone K3 is an 8-core risc-v chip, and the first
widely available RVA23 implementation. Note that this is
entirely unrelated with the similarly named Texas Instruments
K3 chip family that follwed the TI Keystone2 SoC.
- The Realtek Kent family of SoCs contains three chip models
rtd1501s, rtd1861b and rtd1920s, and is related to their earlier
Set-top-box and NAS products such as rtd1619, but is built
on newer Arm Cortex-A78 cores.
- The Qualcomm Milos family includes the Snapdragon 7s Gen 3
(SM7635) mobile phone SoC built around Armv9 Kryo cores of the Arm
Cortex-A720 generation. This one is used in the Fairphone Gen 6
- Qualcomm Kaanapali is a new SoC based around eight high
performance Oryon CPU cores
- NXP i.MX8QP and i.MX952 are both feature reduced versions of
chips we already support, i.e. the i.MX8QM and i.MX952, with
fewer CPU cores and I/O interfaces.
As part of a cleanup, a number of SoC specific devicetree files got
removed because they did not have a single board using the .dtsi files
and they were never compile tested as a result: Samsung s3c6400,
ST spear320s, ST stm32mp21xc/stm32mp23xc/stm32mp25xc, Renesas
r8a779m0/r8a779m2/r8a779m4/r8a779m6/r8a779m7/r8a779m8/r8a779mb/
r9a07g044c1/r9a07g044l1/r9a07g054l1/r9a09g047e37, and TI am3703/am3715.
All of these could be restored easily if a new board gets merged.
Broadcom/Cavium/Marvell ThunderX2 gets removed along with its only
machine, as all remaining users are assumed to be using ACPI
based firmware.
A relatively small number of 43 boards get added this time, and
almost all of them for arm64. Aside from the reference boards for
the newly added SoCs, this includes:
- Three server boards use 32-bit ASpeed BMCs
- One more reference board for 32-bit Microchip LAN9668
- 64-bit Arm single-board computers based on Amlogic s905y4,
CIX sky1, NXP ls1028a/imx8mn/imx8mp/imx91/imx93/imx95,
Qualcomm qcs6490/qrb2210 and Rockchip rk3568/rk3588s
- Carrier board for SOMs using Intel agilex5, Marvell Armada 7020,
NXP iMX8QP, Mediatek mt8370/mt8390 and rockchip rk3588
- Two mobile phones using Snapdragon 845
- A gaming device and a NAS box, both based on Rockchips rk356x
On top of the newly added boards and SoCs, there is a lot of
background activity going into cleanups, in particular towards
getting a warning-free dtc build, and the usual work on adding
support for more hardware on the previously added machines.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmmLSTIACgkQmmx57+YA
GNk6xw//bn239Nn6XUSrmm3b7SGDf+9AvdrukrUEOsIYBYUM7fkulVSINpVOSzZU
DAxLSCY1qfE9zP4x+hrYv922w9Rt19zPuEwFVCslbbTk9NN8IhmhIOs06o2jrvN3
HS/AcESV2SCUe0EVjDIdBgisKMGdbN2t8bdrFFOmqUkQ+7EJ2GvNL0MoaKrdF+Sr
ilt5Hhkl6ixbGDq2KEB2QQHQhYKa/5GdKS0CLTY4et/dZbjHVg9o6/sfgIhLINCz
wNb9CKnt1Gv5L3RWW2LxQrrNe5qhLmHq1vmPbxSJGrzqnOwY9Tcg4s1Io9EcDtyW
LZlq4PkLJV9oPVHgi0mygZ3ONVhWhCMVhTXg6Osi1aHJeEERuIaYMfeU7WD0jHv8
ZcGboxfyiQmphRJumL0C74uIuuXgdoKrv7gqQvo9dy+HRxdHW/7p8TQi9SSfh7kF
Iysc2ePMmqLd4WJCMxV+7FrT8oZxOL+/KfisCu6n/Qdv65kTWmBlLCK6XZrmWYyk
YKg48F8xpQaSmgevWePwhcH0a/TmgmoT+6xOfTuyo88k65FLXXmrFp14th2Kg5sI
60W9ur6ujPI3s19H9C3IQp7ub5Ermvj+g893zEB1e2CR9blfqRARV9zFSv4OMkq+
hQmqe5cU9/17k7wchFke4Y/FsS8W2oFFJ9o6czOTnh5NhlpVSJw=
=IK23
-----END PGP SIGNATURE-----
Merge tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"There are a handful of new SoCs this time, all of these are more or
less related to chips in a wider family:
- SpacemiT Key Stone K3 is an 8-core risc-v chip, and the first
widely available RVA23 implementation. Note that this is entirely
unrelated with the similarly named Texas Instruments K3 chip family
that follwed the TI Keystone2 SoC.
- The Realtek Kent family of SoCs contains three chip models
rtd1501s, rtd1861b and rtd1920s, and is related to their earlier
Set-top-box and NAS products such as rtd1619, but is built on newer
Arm Cortex-A78 cores.
- The Qualcomm Milos family includes the Snapdragon 7s Gen 3 (SM7635)
mobile phone SoC built around Armv9 Kryo cores of the Arm
Cortex-A720 generation. This one is used in the Fairphone Gen 6
- Qualcomm Kaanapali is a new SoC based around eight high performance
Oryon CPU cores
- NXP i.MX8QP and i.MX952 are both feature reduced versions of chips
we already support, i.e. the i.MX8QM and i.MX952, with fewer CPU
cores and I/O interfaces.
As part of a cleanup, a number of SoC specific devicetree files got
removed because they did not have a single board using the .dtsi files
and they were never compile tested as a result: Samsung s3c6400, ST
spear320s, ST stm32mp21xc/stm32mp23xc/stm32mp25xc, Renesas
r8a779m0/r8a779m2/r8a779m4/r8a779m6/r8a779m7/r8a779m8/r8a779mb/
r9a07g044c1/r9a07g044l1/r9a07g054l1/r9a09g047e37, and TI
am3703/am3715. All of these could be restored easily if a new board
gets merged.
Broadcom/Cavium/Marvell ThunderX2 gets removed along with its only
machine, as all remaining users are assumed to be using ACPI based
firmware.
A relatively small number of 43 boards get added this time, and almost
all of them for arm64. Aside from the reference boards for the newly
added SoCs, this includes:
- Three server boards use 32-bit ASpeed BMCs
- One more reference board for 32-bit Microchip LAN9668
- 64-bit Arm single-board computers based on Amlogic s905y4, CIX
sky1, NXP ls1028a/imx8mn/imx8mp/imx91/imx93/imx95, Qualcomm
qcs6490/qrb2210 and Rockchip rk3568/rk3588s
- Carrier board for SOMs using Intel agilex5, Marvell Armada 7020,
NXP iMX8QP, Mediatek mt8370/mt8390 and rockchip rk3588
- Two mobile phones using Snapdragon 845
- A gaming device and a NAS box, both based on Rockchips rk356x
On top of the newly added boards and SoCs, there is a lot of
background activity going into cleanups, in particular towards getting
a warning-free dtc build, and the usual work on adding support for
more hardware on the previously added machines"
* tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (757 commits)
dt-bindings: intel: Add Agilex eMMC support
arm64: dts: socfpga: agilex: add emmc support
arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node
ARM: dts: socfpga: fix dtbs_check warning for fpga-region
ARM: dts: socfpga: add #address-cells and #size-cells for sram node
dt-bindings: altera: document syscon as fallback for sys-mgr
arm64: dts: altera: Use lowercase hex
dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml
arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes
arm64: dts: socfpga: agilex5: add support for modular board
dt-bindings: intel: Add Agilex5 SoCFPGA modular board
arm64: dts: socfpga: agilex5: Add dma-coherent property
arm64: dts: realtek: Add Kent SoC and EVB device trees
dt-bindings: arm: realtek: Add Kent Soc family compatibles
ARM: dts: samsung: Drop s3c6400.dtsi
ARM: dts: nuvoton: Minor whitespace cleanup
MAINTAINERS: Add Falcon DB
arm64: dts: a7k: add COM Express boards
ARM: dts: microchip: Drop usb_a9g20-dab-mmx.dtsi
arm64: dts: rockchip: Fix rk3588 PCIe range mappings
...
|
||
|
Linus Torvalds
|
bdbddf72a2 |
soc: driver updates for 7.0
There are are a number of to firmware drivers, in particular the TEE
subsystem:
- a bus callback for TEE firmware that device drivers can register to
- sysfs support for tee firmware information
- minor updates to platform specific TEE drivers for AMD, NXP, Qualcomm
and the generic optee driver
- ARM SCMI firmware refactoring to improve the protocol discover
among other fixes and cleanups
- ARM FF-A firmware interoperability improvements
The reset controller and memory controller subsystems gain support for
additional hardware platforms from Mediatek, Renesas, NXP, Canaan and
SpacemiT.
Most of the other changes are for random drivers/soc code. Among
a number of cleanups and newly added hardware support, including:
- Mediatek MT8196 DVFS power management and mailbox support
- Qualcomm SCM firmware and MDT loader refactoring, as part of
the new Glymur platform support.
- NXP i.MX9 System Manager firmware support for accessing the
syslog
- Minor updates for TI, Renesas, Samsung, Apple, Marvell and AMD
SoCs.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmmLWqkACgkQmmx57+YA
GNmbPRAAt4qSMkLvVjGkjjuI3phIjEk9oCNBWDNRUtwdTpnP97cbFXI0jVo2vG7X
aKatSjHeqYe66QT1YFW+JXjJiPXQxtlZtquHomcShHQRd/fS34A1ip9l0sR/RbFV
qP8qMBWWlyND0DsUcE7ymRX/j74yOobdcjG/vG48X81wFxxFOHoNSwItRx5zIq+6
3KenZMoP6+uEQk4uq1USpr0mYAoIUPl0opV9UCjVUSzmYdYW2l/pJWlIqFuj8QZ7
X09qQg070GtYMSOwZfPwvSeV01tEZevIDW7ZF6tJuUNiHE8QMOUoNEWXj1L7hhOY
PUWfDJSKenzzqhMZzM0Vbds/MtGkG7BtCGjJc6zGTaDtO4ucBZcF3tL2KA5k6kp1
9domNvrAT4HGPC1DeWYYRf5RWe63253ev+UDFgEHIwdxj5jE9q9YrnRNvuKvTHcZ
FTYIiBakSMwnjVQt5x9Cm3F1JuQ7LpIN2Fkrq3AY3m85+mHnjdSWVN8jCB9Ko3xX
91ONHnxVyC2bU47yVmLXugWO1MhNeNKuZFKcgqlGImeBixEhT43P8j9b3NeMTVyA
P5iVMZw9om/3XtF5hVHz5ABHlOcFCY5QcKsSJZ9PMyPnjUyzg7Ige7pkZZknNJnb
wcYDQr/sEn83WU6uRRLm3qDbWmGR5tYFcgYYa9U4e8tsO7ZXaqw=
=rUYH
-----END PGP SIGNATURE-----
Merge tag 'soc-drivers-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"There are are a number of to firmware drivers, in particular the TEE
subsystem:
- a bus callback for TEE firmware that device drivers can register to
- sysfs support for tee firmware information
- minor updates to platform specific TEE drivers for AMD, NXP,
Qualcomm and the generic optee driver
- ARM SCMI firmware refactoring to improve the protocol discover
among other fixes and cleanups
- ARM FF-A firmware interoperability improvements
The reset controller and memory controller subsystems gain support for
additional hardware platforms from Mediatek, Renesas, NXP, Canaan and
SpacemiT.
Most of the other changes are for random drivers/soc code. Among a
number of cleanups and newly added hardware support, including:
- Mediatek MT8196 DVFS power management and mailbox support
- Qualcomm SCM firmware and MDT loader refactoring, as part of the
new Glymur platform support.
- NXP i.MX9 System Manager firmware support for accessing the syslog
- Minor updates for TI, Renesas, Samsung, Apple, Marvell and AMD
SoCs"
* tag 'soc-drivers-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (171 commits)
bus: fsl-mc: fix an error handling in fsl_mc_device_add()
reset: spacemit: Add SpacemiT K3 reset driver
reset: spacemit: Extract common K1 reset code
reset: Create subdirectory for SpacemiT drivers
dt-bindings: soc: spacemit: Add K3 reset support and IDs
reset: canaan: k230: drop OF dependency and enable by default
reset: rzg2l-usbphy-ctrl: Add suspend/resume support
reset: rzg2l-usbphy-ctrl: Propagate the return value of regmap_field_update_bits()
reset: gpio: check the return value of gpiod_set_value_cansleep()
reset: imx8mp-audiomix: Support i.MX8ULP SIM LPAV
reset: imx8mp-audiomix: Extend the driver usage
reset: imx8mp-audiomix: Switch to using regmap API
reset: imx8mp-audiomix: Drop unneeded macros
soc: fsl: qe: qe_ports_ic: Consolidate chained IRQ handler install/remove
soc: mediatek: mtk-cmdq: Add mminfra_offset adjustment for DRAM addresses
soc: mediatek: mtk-cmdq: Extend cmdq_pkt_write API for SoCs without subsys ID
soc: mediatek: mtk-cmdq: Add pa_base parsing for hardware without subsys ID support
soc: mediatek: mtk-cmdq: Add cmdq_get_mbox_priv() in cmdq_pkt_create()
mailbox: mtk-cmdq: Add driver data to support for MT8196
mailbox: mtk-cmdq: Add mminfra_offset configuration for DRAM transaction
...
|
||
|
Frank Li
|
a16f91f807 |
dt-bindings: interrupt-controller: Add compatiblie string fsl,imx(1|25|27|31|35)-avic
Add compatiblie string fsl,imx(1|25|27|31|35)-avic for i.MX3 SoCs (over 15 years old). Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260210221215.1575844-1-Frank.Li@nxp.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
||
|
Linus Torvalds
|
dc855b7771 |
Updates for interrupt chip drivers:
- Add support for the Renesas RZ/V2N SoC
- Add a new driver for the Renesas RZ/[TN]2H SoCs
- Preserve the register state of the RISCV APLIC interrupt controller accross
suspend/resume
- Reinitialize the RISCV IMSIC registers after suspend/resume
- Make the various Loongson interrupt chip drivers 32/64-bit aware
- Handle the number of hardware interrupts in the SIFIVE PLIC driver
correctly.
The hardware interrupt 0 is reserved which resulted in inconsistent
accounting. That went unnoticed as the off by one is only noticable when
the number of device interrupts is a multiple of 32.
- The usual device tree updates, cleanups and improvements all over the place.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmmJxQkQHHRnbHhAa2Vy
bmVsLm9yZwAKCRCmGPVMDXSYoapGEACTashfhOo6xIeLDiL4+AUbsj0l0uFyW4w4
PRErZxc1DcCOIL/AKYFVsFT85KfYM5ye+1bSTHC7evmjMSFvvDYm3Xss89k+mAoi
W/2QSpfC9viWuEFRstFvStcUNhxih+Sv+DCZM9UungaVAvZvnj0LoIjZsU3IjZOz
abbD/NMZgM3PSfw2LPCeurkhp3N91Yod6jaBtW2afE/wo1ftbXyaSFwSa++715Jz
BnDfNRxG5nMaXqBpwCPnZu5zKreQDiti1e0C/CtsGsbMfMOwkz9cr3LRMGtIoYxa
xnioc2ckL7wy3oVh7efVFTe7el61hYWbx1fbx+D4mv1mrOYYLyu59o2iKBkY1MP/
KKNRXwtS9HbezT6DHsNn7pX7ETdKNfdtF84/qxvYDHaog53Gy20ve4ioDOjx6VIG
z0rmwklACUJ1zp57+s6sYGJBCQakizwb5axgQ1RXG75sNrWLbsklPqrb+U7L7oDa
KAkwNShms4ZjNb5QHEPqB3IcUxbFgnuArZci7A6nhQfe9sDwWJafWNGnjMUuUdK1
fx0e1UkI9Gy+2yBKUJvZUZL4u93ToJUgX0Ucc37VDz9WaFFTSco1jadT9CCDKraU
gU3NHZeBIjT1xsk1Slnjq8k3Lp9b6Q7qNWL3u/4HfeMg8QwW+CM29xy5a0P5ifrc
v6W352Y1Zg==
=ZMMl
-----END PGP SIGNATURE-----
Merge tag 'irq-drivers-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq chip driver updates from Thomas Gleixner:
- Add support for the Renesas RZ/V2N SoC
- Add a new driver for the Renesas RZ/[TN]2H SoCs
- Preserve the register state of the RISCV APLIC interrupt controller
accross suspend/resume
- Reinitialize the RISCV IMSIC registers after suspend/resume
- Make the various Loongson interrupt chip drivers 32/64-bit aware
- Handle the number of hardware interrupts in the SIFIVE PLIC driver
correctly
The hardware interrupt 0 is reserved which resulted in inconsistent
accounting. That went unnoticed as the off by one is only noticable
when the number of device interrupts is a multiple of 32
- The usual device tree updates, cleanups and improvements all over the
place
* tag 'irq-drivers-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (24 commits)
irqchip/gic-v5: Fix spelling mistake "ouside" -> "outside"
dt-bindings: interrupt-controller: sifive,plic: Clarify the riscv,ndev meaning in PLIC
irqchip/sifive-plic: Handle number of hardware interrupts correctly
irqchip/aspeed-scu-ic: Remove unused variable mask
irqchip/ti-sci-intr: Allow parsing interrupt-types per-line
dt-bindings: interrupt-controller: ti,sci-intr: Per-line interrupt-types
irqchip/renesas-rzv2h: Add suspend/resume support
irqchip/aslint-sswi: Fix error check of of_io_request_and_map() result
irqchip: Allow LoongArch irqchip drivers on both 32BIT/64BIT
irqchip/loongson-pch-pic: Adjust irqchip driver for 32BIT/64BIT
irqchip/loongson-pch-msi: Adjust irqchip driver for 32BIT/64BIT
irqchip/loongson-htvec: Adjust irqchip driver for 32BIT/64BIT
irqchip/loongson-eiointc: Adjust irqchip driver for 32BIT/64BIT
irqchip/loongson-liointc: Adjust irqchip driver for 32BIT/64BIT
irqchip/loongarch-avec: Adjust irqchip driver for 32BIT/64BIT
irqchip/riscv-aplic: Preserve APLIC states across suspend/resume
irqchip/riscv-imsic: Add a CPU pm notifier to restore the IMSIC on exit
arm64: dts: renesas: r9a09g087: Add ICU support
arm64: dts: renesas: r9a09g077: Add ICU support
irqchip: Add RZ/{T2H,N2H} Interrupt Controller (ICU) driver
...
|
||
|
Yangyu Chen
|
889588d750 |
dt-bindings: interrupt-controller: sifive,plic: Clarify the riscv,ndev meaning in PLIC
In PLIC, interrupt source 0 is reserved and should not be used. Therefore, the valid interrupt sources are from 1 to riscv,ndev inclusive. Update the documentation to clarify this point. [ tglx: Fixup subject prefix ] Signed-off-by: Yangyu Chen <cyy@cyyself.name> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/tencent_720A4669773B1EE15EC720869C35C2F0490A@qq.com |
||
|
Arnd Bergmann
|
cfd00b7e26 |
FSL SOC Changes for 6.20
Freescale Management Complex: - Convert fsl-mc bus to bus callbacks - Fix a use-after-free - Drop redundant error messages - Fix ressources release on some error path Freescale QUICC Engine: - Add an interrupt controller for IO Ports - Use scoped for-each OF child loop -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTH/wu6mIr0ZW+Vui/dkHAmvKvPUwUCaX2wKAAKCRDdkHAmvKvP U8ZEAQCjVUaUt+nRVvd+/WzZy+dh4vT9r1FJeV4MtHSTfvSM+QD+P5eiz0RIvCAZ 0++CD7UTnPvpxlUMXX08cJRPLmgr1wA= =GjGO -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmmC+EIACgkQmmx57+YA GNnEtw/+Ov7AKkw2FpZYkpXhvzvIGvVy5HdAM4DbscedQF2qD/8Pr+tWcrM4avjW qIRvK1uAS1TSNWszze9htXd7CoHCViOuA0CUuIKp4Q1YO18fOW+eN3+uYNM0ylfg BNhY4u31EWS6F+tST30+W1eR1Oj5RfVZp2jXMKLeqjjb6qINQ4Gc3Mge+jXTbI47 M+imsNKwMMM/tDK4HNYiU7L52Y9Oo3UdnTH4LEgj7AvIQ2cZDW6n0PJUnlDAJjFJ dy7/BSZ9zdaxf8779Ma/0obJd67EIhDSEiW81hKaEp1xKhSdpwqlDkU3QKDmWAIh IbtlM8bl+5LK7tm7Olb7Zp4LC8N+2LZz3bR3kZlAlCVPK5ZVx5/23JFCHwHK+1hR nJklyChfYrN0zF3zFUvKWu77CRDEwwYH9hFNE2fa8XszMx1aH8FqxraYGqJwZpqj 9K4gexlJ/4HK477wFgyZN65mMIt0zbr9K024cY2f/HF3OvcmvM9HQs23iUcaTJO8 4D/b+BzwEo2aJxdvO+W7/6vqIyk3k7wPGQbO9DQMsL+jmVJ6xM1dH0UMjjEvzDUF E6RLigZtEzKGmg+EoM2YIIz456hqtX0Osct5irA5kLw8NX5UJN6po1u9xZAVWTW3 kYIZklaZ3Fc9AbRyFdf6w5//xRcCIzfsbXQiu5UFgHtbFZn5f7E= =+uwq -----END PGP SIGNATURE----- Merge tag 'soc_fsl-6.20-1' of https://git.kernel.org/pub/scm/linux/kernel/git/chleroy/linux into soc/drivers FSL SOC Changes for 6.20 Freescale Management Complex: - Convert fsl-mc bus to bus callbacks - Fix a use-after-free - Drop redundant error messages - Fix ressources release on some error path Freescale QUICC Engine: - Add an interrupt controller for IO Ports - Use scoped for-each OF child loop * tag 'soc_fsl-6.20-1' of https://git.kernel.org/pub/scm/linux/kernel/git/chleroy/linux: bus: fsl-mc: fix an error handling in fsl_mc_device_add() soc: fsl: qe: qe_ports_ic: Consolidate chained IRQ handler install/remove dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports soc: fsl: qe: Simplify with scoped for each OF child loop bus: fsl-mc: fix use-after-free in driver_override_show() bus: fsl-mc: Convert to bus callbacks bus: fsl-mc: Drop error message in probe function Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Binbin Zhou
|
5872df37c4 |
dt-bindings: interrupt-controller: loongson,pch-pic: Document address-cells
The Loongson PCH interrupt controller can be referenced in interrupt-map properties (e.g. in arch/loongarch/boot/dts/loongson-2k2000.dtsi), thus the nodes should have address-cells property. Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Link: https://patch.msgid.link/e531084ee65a695ec08d0f559caec067877fb9a5.1767505859.git.zhoubinbin@loongson.cn Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
||
|
Binbin Zhou
|
3efe078d9d |
dt-bindings: interrupt-controller: loongson,eiointc: Document address-cells
The Loongson Extend I/O interrupt controller can be referenced in interrupt-map properties (e.g. in arch/loongarch/boot/dts/loongson-2k0500.dtsi), thus the nodes should have address-cells property. Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Link: https://patch.msgid.link/3e903541d37432c88c27272094420b03418a607d.1767505859.git.zhoubinbin@loongson.cn Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
||
|
Binbin Zhou
|
08a953754a |
dt-bindings: interrupt-controller: loongson,liointc: Document address-cells
The Loongson local I/O interrupt controller can be referenced in interrupt-map properties (e.g. in arch/loongarch/boot/dts/loongson-2k1000.dtsi), thus the nodes should have address-cells property. Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Link: https://patch.msgid.link/fb3811b6bc387aa23adfc0aaf9a0a31c2d468e79.1767505859.git.zhoubinbin@loongson.cn Signed-off-by: Rob Herring (Arm) <robh@kernel.org> |
||
|
Arnd Bergmann
|
332a1ff488 |
RISC-V SpacemiT DT changes for 6.20
- Disable Ethernet PHY auto sleep mode - Add pinctrl IO power support - Add K3 Pico-ITX board - Add support for K3 SoC - Add DWC USB support - Add reset for eMMC(sdhci)/I2C - Add PCIe support - Support PMIC for Jupiter board -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQKvBAABCgCZFiEEtbq4ycMbcRVnAiPcMarqR1lNu+0FAmlyLBMbFIAAAAAABAAO bWFudTIsMi41KzEuMTEsMiwyXxSAAAAAAC4AKGlzc3Vlci1mcHJAbm90YXRpb25z Lm9wZW5wZ3AuZmlmdGhob3JzZW1hbi5uZXRCNUJBQjhDOUMzMUI3MTE1NjcwMjIz REMzMUFBRUE0NzU5NERCQkVEAAoJEDGq6kdZTbvtjlkQAJeh1kIb3QBscszEhgbK t92qwSMaG2sEXVuX0XIHjVRH1v0wgDxZLb21juqtln9X1yvhWE2dtNHRKToY+t4L +IjfIRULrqkzD9XrzTLlmU+OLfv9s8+j4DzXfaloCjSesBaJL3DLO5c4b89cYN2V Ze+9JmHUrG7o1PtD1YT9pyWp09uYi0+JvPJTG2t1xvLjBMhRpUp2A0Slo9yTIqEW fFz+irms+O1Ee70l/QNIPp6IBwDfOGXYNZr7uheQcqwTYkY7HQW3MhtWzqGdU4rI UJ2MJj01kfwHON3lHX5RSYk+Mh+HfjN8lRc7oiCrp4AOlHULOKHsKVbNKMBWmphz m/EopGThH4dxQYOJEFommTPYfDJ+hRadfAQZ1MDKKJM21biN1xgJ3kpw4R4oEHhn u7FgSGp+yLmSNSu7Y64f3Irq3Oq1lmaAuZKFQjTV4KZsnVPmajkBBcZ35KmpXsi/ A0rip/cTGSattKNKWXuCHJPk5TO6tSmDL961osQj3N7QrpNSFVH/15Dt6fkSH7yu 3qF3JZvCZZQljyeAMO3dvTFQhPf7oR9IZipOtF9XjDMzTmIXGCnr09dSEiFjzifQ Yr9KNJLf0HnyHpaGRBD8+W1PQnWZ8vFbLTy5TD9j7I5WenCu3IOr0c9pheavuwtx LROP3e5r2pZEjtayH1qfFiqZ =Uyut -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml6Sd0ACgkQmmx57+YA GNnayw/+Ioh+CJ1VKDjVXpMHEl+Siw0Fmk6n61DaNLxkhwD+tfx24ppJDsaI5I70 GmTRa7TH66iTE94KSbu5JJCWcIbBdVSQsoPUCqw62psie7SQB90BlLf+l7oKPUYi E46pUPr1dGSuuxRSsxFS9WFW9ura8MYYYlaUStOI66aYJoc0mVbwsekaZr3PCKr7 5QQUtFDCkssr7iR9T77mVd/EAfk7NIwGkLTYlqfekV4FDElkD0n841Vhl5Dhwqop 1kwMjYLzHTQwvzErB4bx51vFEj4GwHd4ukewa/Jht8OWsS2/lVA2UjVgH2at6asu VU6cC8RUFT7oZX4ytYJFa8wsNwzU23Ckj2xtjOg0ctpYTCuMmVvqA47r6vCIIzwS gnt6Smy9JWHDS6jvB4Xf5j0TV7w4luOPkng9QcH0O2NmZU50I111ryrsqGxS8vjv qpGOcZGJGalwGSyHt/lyZJmNG5K9xGU58Ws0tWihaTNSLLqDCOVDg1w6AmbCCT/3 wldnbzofvreogKCgqWyOU5neN67MYjGdcRge0jt/gmMEKF5eCFmRaU1NtapNeFFD yQfaXYEKPUIQx7GvQGH/5Lp0DgTz7Y+jhFnN/H5JfC6zdYF6OAe6HT/cTeJGFknQ qMJyh81sqlEQ+iJK+k/Y3y9KPAE3Km8DbB7kfJjDsdu8KO+61Ao= =dXF9 -----END PGP SIGNATURE----- Merge tag 'spacemit-dt-for-6.20-1' of https://github.com/spacemit-com/linux into soc/dt RISC-V SpacemiT DT changes for 6.20 - Disable Ethernet PHY auto sleep mode - Add pinctrl IO power support - Add K3 Pico-ITX board - Add support for K3 SoC - Add DWC USB support - Add reset for eMMC(sdhci)/I2C - Add PCIe support - Support PMIC for Jupiter board * tag 'spacemit-dt-for-6.20-1' of https://github.com/spacemit-com/linux: riscv: dts: spacemit: Disable ETH PHY sleep mode for OrangePi riscv: dts: spacemit: pinctrl: update register and IO power riscv: dts: spacemit: add K3 Pico-ITX board support riscv: dts: spacemit: add initial support for K3 SoC dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC dt-bindings: interrupt-controller: add SpacemiT K3 APLIC dt-bindings: timer: add SpacemiT K3 CLINT dt-bindings: riscv: add SpacemiT X100 CPU compatible riscv: dts: spacemit: k1: Add "b" ISA extension riscv: dts: spacemit: Enable USB3.0 on BananaPi-F3 riscv: dts: spacemit: Add DWC3 USB 3.0 controller node for K1 riscv: dts: spacemit: Add USB2 PHY node for K1 riscv: dts: spacemit: sdhci: add reset support riscv: dts: spacemit: add reset property riscv: dts: spacemit: PCIe and PHY-related updates riscv: dts: spacemit: Add a PCIe regulator riscv: dts: spacemit: Define the P1 PMIC regulators for Milk-V Jupiter riscv: dts: spacemit: Define fixed regulators for Milk-V Jupiter riscv: dts: spacemit: Enable i2c8 adapter for Milk-V Jupiter Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Aniket Limaye
|
7a30a7a6c8 |
dt-bindings: interrupt-controller: ti,sci-intr: Per-line interrupt-types
Update the bindings to allow setting per-line interrupt-types. Some Interrupt Router instances can only work with a specific trigger type (edge or level), while others act as simple passthroughs that preserve the source interrupt type unchanged. Make "ti,intr-trigger-type" property optional, with its absence indicating that the router acts as a passthrough. When absent, "#interrupt-cells" must be 2 to allow each interrupt source to specify its trigger type per-line. Signed-off-by: Aniket Limaye <a-limaye@ti.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260123-ul-driver-i2c-j722s-v4-1-b08625c487d5@ti.com |
||
|
Arnd Bergmann
|
733f0303c2 |
Qualcomm driver updates for v6.20
Support multiple wait queues in the SCM firmware interface and provide discovery of the wait queue interrupt to deal with the cases where bootloader didn't patch the DeviceTree with the IRQ information. Refactor the MDT loader and the SCM driver's peripheral authentication service interface and introduce support for passing a remoteproc resource table to the firmware. The remoteproc patches that uses this and uses this to configure the IOMMU are included here due to bidirectional dependencies. The end result is remoteproc support on the Glymur platform. Enable QSEECOM and thereby UEFI variable access, on the Surface Pro 11. Make the QMI interface endianness aware, to support ath1Xk on big endian machines. Add the Glymur support in LLCC driver. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmluWgUACgkQCx85Pw2Z rcX0UxAAjouQqOvIdStDcuq25dYbOe9EH+kwJUI5snU9zWcuFmn1+q9Qz6W6611I IYXWIfkyPaSqvngt53/zq/CgtmX9ez8FFK/+IzdaiuCRLVZZheC7nvg2SnQE+Xav qQIyFWtVI3ufT9x1I+27c42sYRbAXa5JHg+yOPMVG8I9ARK7gcgmkQ+1FL6fut0a C6nfwHg/mHt/TQ4iHDyrJ6Ttx9JWAXdXFl8ekOCe+eXTaiaGj3DgrN5EjRzhiilb lbxOXDzJ4CfwjfoT9eeXRe3GA2rTpY+gaIoOEBRcDkjHVJvRMAz3NqbeKgm40f+o 3iBLWWgHlsFBrspSzKWAUr7X84XO4gpm9w61TADUIeoHn6pb2DWN1P7SvrbdZGrr ASz3dQZT9w++5qxqjY9JWubNx3akt5bJLcHd1PrVXeZugUyAmoGMpm7LKgXNTV3q KKpvRwZN9h+Ebf+8y4Y2WUsQn+u/AXLZi2yoYBrZVUVRlsntsfxWT7eF47ROnIMv KoKVkOmglcB61HmUWolYdGEtCTarQlmOBA9wn0DQll64hfjppWX+/VmrleWMqECR 4dngxoj4/d4gXNB8H6BD3nftInqu8P9va82oT6yca/2Ce0WnA37IQ43l5yFpnejm VzCTPpzbKkcNZgAU51o0T2SzmrP6SN/LLq7XpDdz01rcPBCwTic= =8a2h -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmlw9LYACgkQmmx57+YA GNktRA//apmectfvVwEtqzYpPhPcZgGisBMS00YEJx3DbZCS5d628qol765m22sj jr8NinoGfPwSfWA4AoOAMMdylPnSVMlde3tg1yZS4S/4MmyyqP0VbiqiQ0B7nSap MeTfQVOgihhgJKfek66T2AL3xgWpyYGEe1UmkzLmpn0xxg/EGgTTI/N4uIz7s5zR eGrdugP1+4wQ22vOcUPA17IBklOHow8G2ejT8ChMc0yHtfER6yENOxMLKIQjMhps XJta5yjl8HmulmPqmfc84izNGaVst4So8J+rIXx/ZwmeegByKw4oWzZBk1WD0C6x IhGgRZ47oZiTP9i5lh1StxPp3+mynNqOigeNGCCuHOMOKD2U6mqdiWFeYlHW/EGe pVO+LH7c/3vUo2PFuQWAsme5ldaYZS4nhH9WNTyGkoULezl1mnZyLalRYVQGcx/0 vPUqiQflju5dqlu9Cl7PemZ2uItcRFt/ypKyYSgEgecPxzELlmZlop4Kqxv/aeXW Tx0PJWfgCXnu/gi1i9IAZIc869qBu+uyI/XtGMBAr3DcRu9r3xgsJEpd89lNp4bM 0fRM7ZaYqY3pExcQPuHeaQgCfo4tYsSkFbYbrbk/mU0QS80P54fIr4iBIokvQS0h e4tbTWZZ1gd6LAGMSGOvf9dGvhzoXD9kybVfxtKDn/kEPNR3BiQ= =X8K9 -----END PGP SIGNATURE----- Merge tag 'qcom-drivers-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers Qualcomm driver updates for v6.20 Support multiple wait queues in the SCM firmware interface and provide discovery of the wait queue interrupt to deal with the cases where bootloader didn't patch the DeviceTree with the IRQ information. Refactor the MDT loader and the SCM driver's peripheral authentication service interface and introduce support for passing a remoteproc resource table to the firmware. The remoteproc patches that uses this and uses this to configure the IOMMU are included here due to bidirectional dependencies. The end result is remoteproc support on the Glymur platform. Enable QSEECOM and thereby UEFI variable access, on the Surface Pro 11. Make the QMI interface endianness aware, to support ath1Xk on big endian machines. Add the Glymur support in LLCC driver. * tag 'qcom-drivers-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (33 commits) soc: qcom: preserve CPU endianness for QMI_DATA_LEN soc: qcom: fix QMI encoding/decoding for basic elements soc: qcom: check QMI basic element error codes soc: qcom: ubwc: add missing include remoteproc: qcom: pas: Enable Secure PAS support with IOMMU managed by Linux remoteproc: pas: Extend parse_fw callback to fetch resources via SMC call firmware: qcom_scm: Add qcom_scm_pas_get_rsc_table() to get resource table firmware: qcom_scm: Add SHM bridge handling for PAS when running without QHEE firmware: qcom_scm: Refactor qcom_scm_pas_init_image() firmware: qcom_scm: Add a prep version of auth_and_reset function soc: qcom: mdtloader: Remove qcom_mdt_pas_init() from exported symbols soc: qcom: mdtloader: Add PAS context aware qcom_mdt_pas_load() function remoteproc: pas: Replace metadata context with PAS context structure firmware: qcom_scm: Introduce PAS context allocator helper function firmware: qcom_scm: Rename peripheral as pas_id firmware: qcom_scm: Remove redundant piece of code dt-bindings: remoteproc: qcom,pas: Add iommus property soc: qcom: cmd-db: Use devm_memremap() to fix memory leak in cmd_db_dev_probe soc: qcom: pmic_glink_altmode: Consume TBT3/USB4 mode notifications dt-bindings: qcom,pdc: document the Milos Power Domain Controller ... Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Guodong Xu
|
a716729a3c |
dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC
Add compatible string for SpacemiT K3 IMSIC. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Guodong Xu <guodong@riscstar.com> Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-4-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan <dlan@kernel.org> |