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https://github.com/torvalds/linux.git
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RISC-V SpacemiT DT changes for 6.20
- Disable Ethernet PHY auto sleep mode - Add pinctrl IO power support - Add K3 Pico-ITX board - Add support for K3 SoC - Add DWC USB support - Add reset for eMMC(sdhci)/I2C - Add PCIe support - Support PMIC for Jupiter board -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQKvBAABCgCZFiEEtbq4ycMbcRVnAiPcMarqR1lNu+0FAmlyLBMbFIAAAAAABAAO bWFudTIsMi41KzEuMTEsMiwyXxSAAAAAAC4AKGlzc3Vlci1mcHJAbm90YXRpb25z Lm9wZW5wZ3AuZmlmdGhob3JzZW1hbi5uZXRCNUJBQjhDOUMzMUI3MTE1NjcwMjIz REMzMUFBRUE0NzU5NERCQkVEAAoJEDGq6kdZTbvtjlkQAJeh1kIb3QBscszEhgbK t92qwSMaG2sEXVuX0XIHjVRH1v0wgDxZLb21juqtln9X1yvhWE2dtNHRKToY+t4L +IjfIRULrqkzD9XrzTLlmU+OLfv9s8+j4DzXfaloCjSesBaJL3DLO5c4b89cYN2V Ze+9JmHUrG7o1PtD1YT9pyWp09uYi0+JvPJTG2t1xvLjBMhRpUp2A0Slo9yTIqEW fFz+irms+O1Ee70l/QNIPp6IBwDfOGXYNZr7uheQcqwTYkY7HQW3MhtWzqGdU4rI UJ2MJj01kfwHON3lHX5RSYk+Mh+HfjN8lRc7oiCrp4AOlHULOKHsKVbNKMBWmphz m/EopGThH4dxQYOJEFommTPYfDJ+hRadfAQZ1MDKKJM21biN1xgJ3kpw4R4oEHhn u7FgSGp+yLmSNSu7Y64f3Irq3Oq1lmaAuZKFQjTV4KZsnVPmajkBBcZ35KmpXsi/ A0rip/cTGSattKNKWXuCHJPk5TO6tSmDL961osQj3N7QrpNSFVH/15Dt6fkSH7yu 3qF3JZvCZZQljyeAMO3dvTFQhPf7oR9IZipOtF9XjDMzTmIXGCnr09dSEiFjzifQ Yr9KNJLf0HnyHpaGRBD8+W1PQnWZ8vFbLTy5TD9j7I5WenCu3IOr0c9pheavuwtx LROP3e5r2pZEjtayH1qfFiqZ =Uyut -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml6Sd0ACgkQmmx57+YA GNnayw/+Ioh+CJ1VKDjVXpMHEl+Siw0Fmk6n61DaNLxkhwD+tfx24ppJDsaI5I70 GmTRa7TH66iTE94KSbu5JJCWcIbBdVSQsoPUCqw62psie7SQB90BlLf+l7oKPUYi E46pUPr1dGSuuxRSsxFS9WFW9ura8MYYYlaUStOI66aYJoc0mVbwsekaZr3PCKr7 5QQUtFDCkssr7iR9T77mVd/EAfk7NIwGkLTYlqfekV4FDElkD0n841Vhl5Dhwqop 1kwMjYLzHTQwvzErB4bx51vFEj4GwHd4ukewa/Jht8OWsS2/lVA2UjVgH2at6asu VU6cC8RUFT7oZX4ytYJFa8wsNwzU23Ckj2xtjOg0ctpYTCuMmVvqA47r6vCIIzwS gnt6Smy9JWHDS6jvB4Xf5j0TV7w4luOPkng9QcH0O2NmZU50I111ryrsqGxS8vjv qpGOcZGJGalwGSyHt/lyZJmNG5K9xGU58Ws0tWihaTNSLLqDCOVDg1w6AmbCCT/3 wldnbzofvreogKCgqWyOU5neN67MYjGdcRge0jt/gmMEKF5eCFmRaU1NtapNeFFD yQfaXYEKPUIQx7GvQGH/5Lp0DgTz7Y+jhFnN/H5JfC6zdYF6OAe6HT/cTeJGFknQ qMJyh81sqlEQ+iJK+k/Y3y9KPAE3Km8DbB7kfJjDsdu8KO+61Ao= =dXF9 -----END PGP SIGNATURE----- Merge tag 'spacemit-dt-for-6.20-1' of https://github.com/spacemit-com/linux into soc/dt RISC-V SpacemiT DT changes for 6.20 - Disable Ethernet PHY auto sleep mode - Add pinctrl IO power support - Add K3 Pico-ITX board - Add support for K3 SoC - Add DWC USB support - Add reset for eMMC(sdhci)/I2C - Add PCIe support - Support PMIC for Jupiter board * tag 'spacemit-dt-for-6.20-1' of https://github.com/spacemit-com/linux: riscv: dts: spacemit: Disable ETH PHY sleep mode for OrangePi riscv: dts: spacemit: pinctrl: update register and IO power riscv: dts: spacemit: add K3 Pico-ITX board support riscv: dts: spacemit: add initial support for K3 SoC dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC dt-bindings: interrupt-controller: add SpacemiT K3 APLIC dt-bindings: timer: add SpacemiT K3 CLINT dt-bindings: riscv: add SpacemiT X100 CPU compatible riscv: dts: spacemit: k1: Add "b" ISA extension riscv: dts: spacemit: Enable USB3.0 on BananaPi-F3 riscv: dts: spacemit: Add DWC3 USB 3.0 controller node for K1 riscv: dts: spacemit: Add USB2 PHY node for K1 riscv: dts: spacemit: sdhci: add reset support riscv: dts: spacemit: add reset property riscv: dts: spacemit: PCIe and PHY-related updates riscv: dts: spacemit: Add a PCIe regulator riscv: dts: spacemit: Define the P1 PMIC regulators for Milk-V Jupiter riscv: dts: spacemit: Define fixed regulators for Milk-V Jupiter riscv: dts: spacemit: Enable i2c8 adapter for Milk-V Jupiter Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
332a1ff488
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@ -28,6 +28,7 @@ properties:
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items:
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- enum:
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- qemu,aplic
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- spacemit,k3-aplic
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- const: riscv,aplic
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reg:
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@ -48,6 +48,7 @@ properties:
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items:
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- enum:
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- qemu,imsics
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- spacemit,k3-imsics
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- const: riscv,imsics
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reg:
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@ -61,6 +61,7 @@ properties:
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- sifive,u7
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- sifive,u74
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- sifive,u74-mc
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- spacemit,x100
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- spacemit,x60
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- thead,c906
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- thead,c908
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@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SpacemiT SoC-based boards
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maintainers:
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- Guodong Xu <guodong@riscstar.com>
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- Yangyu Chen <cyy@cyyself.name>
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- Yixun Lan <dlan@gentoo.org>
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@ -26,6 +27,10 @@ properties:
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- xunlong,orangepi-r2s
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- xunlong,orangepi-rv2
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- const: spacemit,k1
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- items:
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- enum:
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- spacemit,k3-pico-itx
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- const: spacemit,k3
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additionalProperties: true
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@ -33,6 +33,7 @@ properties:
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- eswin,eic7700-clint # ESWIN EIC7700
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- sifive,fu540-c000-clint # SiFive FU540
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- spacemit,k1-clint # SpacemiT K1
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- spacemit,k3-clint # SpacemiT K3
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- starfive,jh7100-clint # StarFive JH7100
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- starfive,jh7110-clint # StarFive JH7110
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- starfive,jh8100-clint # StarFive JH8100
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@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb
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dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb
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dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb
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dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb
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dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb
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@ -33,6 +33,14 @@ led1 {
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};
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};
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pcie_vcc_3v3: pcie-vcc3v3 {
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compatible = "regulator-fixed";
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regulator-name = "PCIE_VCC3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_dc_in: dc-in-12v {
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compatible = "regulator-fixed";
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regulator-name = "dc_in_12v";
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@ -51,6 +59,31 @@ reg_vcc_4v: vcc-4v {
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regulator-always-on;
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vin-supply = <®_dc_in>;
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};
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usb3-vbus-5v {
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compatible = "regulator-fixed";
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regulator-name = "USB30_VBUS";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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usb3_hub_5v: usb3-hub-5v {
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compatible = "regulator-fixed";
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regulator-name = "USB30_HUB";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&combo_phy {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_3_cfg>;
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status = "okay";
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};
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&emmc {
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@ -264,8 +297,65 @@ dldo7 {
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};
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};
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&pcie1_phy {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie1_3_cfg>;
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status = "okay";
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};
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&pcie1_port {
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phys = <&pcie1_phy>;
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};
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&pcie1 {
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vpcie3v3-supply = <&pcie_vcc_3v3>;
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status = "okay";
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};
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&pcie2_phy {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie2_4_cfg>;
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status = "okay";
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};
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&pcie2_port {
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phys = <&pcie2_phy>;
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};
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&pcie2 {
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vpcie3v3-supply = <&pcie_vcc_3v3>;
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status = "okay";
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_2_cfg>;
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status = "okay";
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};
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&usbphy2 {
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status = "okay";
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};
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&usb_dwc3 {
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dr_mode = "host";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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hub_2_0: hub@1 {
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compatible = "usb2109,2817";
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reg = <0x1>;
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vdd-supply = <&usb3_hub_5v>;
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peer-hub = <&hub_3_0>;
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reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
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};
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hub_3_0: hub@2 {
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compatible = "usb2109,817";
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reg = <0x2>;
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vdd-supply = <&usb3_hub_5v>;
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peer-hub = <&hub_2_0>;
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reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
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};
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};
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@ -20,6 +20,25 @@ aliases {
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chosen {
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stdout-path = "serial0";
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};
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reg_dc_in: dc-in-12v {
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compatible = "regulator-fixed";
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regulator-name = "dc_in_12v";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_vcc_4v: vcc-4v {
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compatible = "regulator-fixed";
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regulator-name = "vcc_4v";
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regulator-min-microvolt = <4000000>;
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regulator-max-microvolt = <4000000>;
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regulator-boot-on;
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regulator-always-on;
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vin-supply = <®_dc_in>;
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};
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};
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ð0 {
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@ -72,6 +91,122 @@ &pdma {
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status = "okay";
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};
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&i2c8 {
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pinctrl-0 = <&i2c8_cfg>;
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pinctrl-names = "default";
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status = "okay";
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pmic@41 {
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compatible = "spacemit,p1";
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reg = <0x41>;
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interrupts = <64>;
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vin-supply = <®_vcc_4v>;
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regulators {
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buck1 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3450000>;
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regulator-ramp-delay = <5000>;
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regulator-always-on;
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};
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buck2 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3450000>;
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regulator-ramp-delay = <5000>;
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regulator-always-on;
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};
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buck3_1v8: buck3 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <1800000>;
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regulator-ramp-delay = <5000>;
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regulator-always-on;
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};
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buck4 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3300000>;
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regulator-ramp-delay = <5000>;
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regulator-always-on;
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};
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buck5 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3450000>;
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regulator-ramp-delay = <5000>;
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regulator-always-on;
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};
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buck6 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3450000>;
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regulator-ramp-delay = <5000>;
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regulator-always-on;
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};
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aldo1 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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};
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aldo2 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3400000>;
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};
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aldo3 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3400000>;
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};
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aldo4 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3400000>;
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};
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dldo1 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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};
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dldo2 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3400000>;
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};
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dldo3 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3400000>;
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};
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dldo4 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3400000>;
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regulator-always-on;
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};
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dldo5 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3400000>;
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};
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dldo6 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3400000>;
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regulator-always-on;
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};
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dldo7 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3400000>;
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};
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};
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_2_cfg>;
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|
|
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@ -52,6 +52,7 @@ mdio-bus {
|
|||
|
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rgmii0: phy@1 {
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reg = <0x1>;
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motorcomm,auto-sleep-disabled;
|
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};
|
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};
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||||
};
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@ -75,6 +76,7 @@ mdio-bus {
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|||
|
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rgmii1: phy@1 {
|
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reg = <0x1>;
|
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motorcomm,auto-sleep-disabled;
|
||||
};
|
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};
|
||||
};
|
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|
|
|
|||
|
|
@ -54,6 +54,7 @@ mdio-bus {
|
|||
|
||||
rgmii0: phy@1 {
|
||||
reg = <0x1>;
|
||||
motorcomm,auto-sleep-disabled;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -77,6 +78,7 @@ mdio-bus {
|
|||
|
||||
rgmii1: phy@1 {
|
||||
reg = <0x1>;
|
||||
motorcomm,auto-sleep-disabled;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -530,6 +530,39 @@ uart9-2-pins {
|
|||
};
|
||||
};
|
||||
|
||||
pcie0_3_cfg: pcie0-3-cfg {
|
||||
pcie0-3-pins {
|
||||
pinmux = <K1_PADCONF(54, 3)>, /* PERST# */
|
||||
<K1_PADCONF(55, 3)>, /* WAKE# */
|
||||
<K1_PADCONF(53, 3)>; /* CLKREQ# */
|
||||
|
||||
bias-pull-up = <0>;
|
||||
drive-strength = <21>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_3_cfg: pcie1-3-cfg {
|
||||
pcie1-3-pins {
|
||||
pinmux = <K1_PADCONF(59, 4)>, /* PERST# */
|
||||
<K1_PADCONF(60, 4)>, /* WAKE# */
|
||||
<K1_PADCONF(61, 4)>; /* CLKREQ# */
|
||||
|
||||
bias-pull-up = <0>;
|
||||
drive-strength = <21>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_4_cfg: pcie2-4-cfg {
|
||||
pcie2-4-pins {
|
||||
pinmux = <K1_PADCONF(62, 4)>, /* PERST# */
|
||||
<K1_PADCONF(112, 3)>, /* WAKE# */
|
||||
<K1_PADCONF(117, 4)>; /* CLKREQ# */
|
||||
|
||||
bias-pull-up = <0>;
|
||||
drive-strength = <21>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm14_1_cfg: pwm14-1-cfg {
|
||||
pwm14-1-pins {
|
||||
pinmux = <K1_PADCONF(44, 4)>;
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/clock/spacemit,k1-syscon.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
|
|
@ -53,9 +54,9 @@ cpu_0: cpu@0 {
|
|||
compatible = "spacemit,x60", "riscv";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
|
||||
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
|
||||
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
|
||||
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
|
||||
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
|
||||
|
|
@ -83,9 +84,9 @@ cpu_1: cpu@1 {
|
|||
compatible = "spacemit,x60", "riscv";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
|
||||
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
|
||||
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
|
||||
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
|
||||
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
|
||||
|
|
@ -113,9 +114,9 @@ cpu_2: cpu@2 {
|
|||
compatible = "spacemit,x60", "riscv";
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
|
||||
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
|
||||
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
|
||||
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
|
||||
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
|
||||
|
|
@ -143,9 +144,9 @@ cpu_3: cpu@3 {
|
|||
compatible = "spacemit,x60", "riscv";
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
|
||||
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
|
||||
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
|
||||
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
|
||||
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
|
||||
|
|
@ -173,9 +174,9 @@ cpu_4: cpu@4 {
|
|||
compatible = "spacemit,x60", "riscv";
|
||||
device_type = "cpu";
|
||||
reg = <4>;
|
||||
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
|
||||
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
|
||||
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
|
||||
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
|
||||
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
|
||||
|
|
@ -203,9 +204,9 @@ cpu_5: cpu@5 {
|
|||
compatible = "spacemit,x60", "riscv";
|
||||
device_type = "cpu";
|
||||
reg = <5>;
|
||||
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
|
||||
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
|
||||
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
|
||||
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
|
||||
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
|
||||
|
|
@ -233,9 +234,9 @@ cpu_6: cpu@6 {
|
|||
compatible = "spacemit,x60", "riscv";
|
||||
device_type = "cpu";
|
||||
reg = <6>;
|
||||
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
|
||||
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
|
||||
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
|
||||
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
|
||||
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
|
||||
|
|
@ -263,9 +264,9 @@ cpu_7: cpu@7 {
|
|||
compatible = "spacemit,x60", "riscv";
|
||||
device_type = "cpu";
|
||||
reg = <7>;
|
||||
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
|
||||
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
|
||||
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
|
||||
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
|
||||
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
|
||||
|
|
@ -367,6 +368,7 @@ i2c0: i2c@d4010800 {
|
|||
<&syscon_apbc CLK_TWSI0_BUS>;
|
||||
clock-names = "func", "bus";
|
||||
clock-frequency = <400000>;
|
||||
resets = <&syscon_apbc RESET_TWSI0>;
|
||||
interrupts = <36>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -380,6 +382,7 @@ i2c1: i2c@d4011000 {
|
|||
<&syscon_apbc CLK_TWSI1_BUS>;
|
||||
clock-names = "func", "bus";
|
||||
clock-frequency = <400000>;
|
||||
resets = <&syscon_apbc RESET_TWSI1>;
|
||||
interrupts = <37>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -393,6 +396,7 @@ i2c2: i2c@d4012000 {
|
|||
<&syscon_apbc CLK_TWSI2_BUS>;
|
||||
clock-names = "func", "bus";
|
||||
clock-frequency = <400000>;
|
||||
resets = <&syscon_apbc RESET_TWSI2>;
|
||||
interrupts = <38>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -406,6 +410,7 @@ i2c4: i2c@d4012800 {
|
|||
<&syscon_apbc CLK_TWSI4_BUS>;
|
||||
clock-names = "func", "bus";
|
||||
clock-frequency = <400000>;
|
||||
resets = <&syscon_apbc RESET_TWSI4>;
|
||||
interrupts = <40>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -419,10 +424,65 @@ i2c5: i2c@d4013800 {
|
|||
<&syscon_apbc CLK_TWSI5_BUS>;
|
||||
clock-names = "func", "bus";
|
||||
clock-frequency = <400000>;
|
||||
resets = <&syscon_apbc RESET_TWSI5>;
|
||||
interrupts = <41>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy2: phy@c0a30000 {
|
||||
compatible = "spacemit,k1-usb2-phy";
|
||||
reg = <0x0 0xc0a30000 0x0 0x200>;
|
||||
clocks = <&syscon_apmu CLK_USB30>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
combo_phy: phy@c0b10000 {
|
||||
compatible = "spacemit,k1-combo-phy";
|
||||
reg = <0x0 0xc0b10000 0x0 0x1000>;
|
||||
clocks = <&vctcxo_24m>,
|
||||
<&syscon_apmu CLK_PCIE0_DBI>,
|
||||
<&syscon_apmu CLK_PCIE0_MASTER>,
|
||||
<&syscon_apmu CLK_PCIE0_SLAVE>;
|
||||
clock-names = "refclk",
|
||||
"dbi",
|
||||
"mstr",
|
||||
"slv";
|
||||
resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
|
||||
<&syscon_apmu RESET_PCIE0_DBI>,
|
||||
<&syscon_apmu RESET_PCIE0_MASTER>,
|
||||
<&syscon_apmu RESET_PCIE0_SLAVE>;
|
||||
reset-names = "phy",
|
||||
"dbi",
|
||||
"mstr",
|
||||
"slv";
|
||||
#phy-cells = <1>;
|
||||
spacemit,apmu = <&syscon_apmu>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie1_phy: phy@c0c10000 {
|
||||
compatible = "spacemit,k1-pcie-phy";
|
||||
reg = <0x0 0xc0c10000 0x0 0x1000>;
|
||||
clocks = <&vctcxo_24m>;
|
||||
clock-names = "refclk";
|
||||
resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
|
||||
reset-names = "phy";
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie2_phy: phy@c0d10000 {
|
||||
compatible = "spacemit,k1-pcie-phy";
|
||||
reg = <0x0 0xc0d10000 0x0 0x1000>;
|
||||
clocks = <&vctcxo_24m>;
|
||||
clock-names = "refclk";
|
||||
resets = <&syscon_apmu RESET_PCIE2_GLOBAL>;
|
||||
reset-names = "phy";
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
syscon_apbc: system-controller@d4015000 {
|
||||
compatible = "spacemit,k1-syscon-apbc";
|
||||
reg = <0x0 0xd4015000 0x0 0x1000>;
|
||||
|
|
@ -443,6 +503,7 @@ i2c6: i2c@d4018800 {
|
|||
<&syscon_apbc CLK_TWSI6_BUS>;
|
||||
clock-names = "func", "bus";
|
||||
clock-frequency = <400000>;
|
||||
resets = <&syscon_apbc RESET_TWSI6>;
|
||||
interrupts = <70>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -546,6 +607,7 @@ i2c7: i2c@d401d000 {
|
|||
<&syscon_apbc CLK_TWSI7_BUS>;
|
||||
clock-names = "func", "bus";
|
||||
clock-frequency = <400000>;
|
||||
resets = <&syscon_apbc RESET_TWSI7>;
|
||||
interrupts = <18>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -559,16 +621,18 @@ i2c8: i2c@d401d800 {
|
|||
<&syscon_apbc CLK_TWSI8_BUS>;
|
||||
clock-names = "func", "bus";
|
||||
clock-frequency = <400000>;
|
||||
resets = <&syscon_apbc RESET_TWSI8>;
|
||||
interrupts = <19>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@d401e000 {
|
||||
compatible = "spacemit,k1-pinctrl";
|
||||
reg = <0x0 0xd401e000 0x0 0x400>;
|
||||
reg = <0x0 0xd401e000 0x0 0x1000>;
|
||||
clocks = <&syscon_apbc CLK_AIB>,
|
||||
<&syscon_apbc CLK_AIB_BUS>;
|
||||
clock-names = "func", "bus";
|
||||
spacemit,apbc = <&syscon_apbc>;
|
||||
};
|
||||
|
||||
pwm8: pwm@d4020000 {
|
||||
|
|
@ -969,6 +1033,135 @@ pcie-bus {
|
|||
#size-cells = <2>;
|
||||
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
|
||||
<0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>;
|
||||
pcie0: pcie@ca000000 {
|
||||
device_type = "pci";
|
||||
compatible = "spacemit,k1-pcie";
|
||||
reg = <0x0 0xca000000 0x0 0x00001000>,
|
||||
<0x0 0xca300000 0x0 0x0001ff24>,
|
||||
<0x0 0x8f000000 0x0 0x00002000>,
|
||||
<0x0 0xc0b20000 0x0 0x00001000>;
|
||||
reg-names = "dbi",
|
||||
"atu",
|
||||
"config",
|
||||
"link";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>;
|
||||
interrupts = <141>;
|
||||
interrupt-names = "msi";
|
||||
clocks = <&syscon_apmu CLK_PCIE0_DBI>,
|
||||
<&syscon_apmu CLK_PCIE0_MASTER>,
|
||||
<&syscon_apmu CLK_PCIE0_SLAVE>;
|
||||
clock-names = "dbi",
|
||||
"mstr",
|
||||
"slv";
|
||||
resets = <&syscon_apmu RESET_PCIE0_DBI>,
|
||||
<&syscon_apmu RESET_PCIE0_MASTER>,
|
||||
<&syscon_apmu RESET_PCIE0_SLAVE>;
|
||||
reset-names = "dbi",
|
||||
"mstr",
|
||||
"slv";
|
||||
spacemit,apmu = <&syscon_apmu 0x03cc>;
|
||||
status = "disabled";
|
||||
|
||||
pcie0_port: pcie@0 {
|
||||
device_type = "pci";
|
||||
compatible = "pciclass,0604";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1: pcie@ca400000 {
|
||||
device_type = "pci";
|
||||
compatible = "spacemit,k1-pcie";
|
||||
reg = <0x0 0xca400000 0x0 0x00001000>,
|
||||
<0x0 0xca700000 0x0 0x0001ff24>,
|
||||
<0x0 0x9f000000 0x0 0x00002000>,
|
||||
<0x0 0xc0c20000 0x0 0x00001000>;
|
||||
reg-names = "dbi",
|
||||
"atu",
|
||||
"config",
|
||||
"link";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>;
|
||||
interrupts = <142>;
|
||||
interrupt-names = "msi";
|
||||
clocks = <&syscon_apmu CLK_PCIE1_DBI>,
|
||||
<&syscon_apmu CLK_PCIE1_MASTER>,
|
||||
<&syscon_apmu CLK_PCIE1_SLAVE>;
|
||||
clock-names = "dbi",
|
||||
"mstr",
|
||||
"slv";
|
||||
resets = <&syscon_apmu RESET_PCIE1_DBI>,
|
||||
<&syscon_apmu RESET_PCIE1_MASTER>,
|
||||
<&syscon_apmu RESET_PCIE1_SLAVE>;
|
||||
reset-names = "dbi",
|
||||
"mstr",
|
||||
"slv";
|
||||
spacemit,apmu = <&syscon_apmu 0x3d4>;
|
||||
status = "disabled";
|
||||
|
||||
pcie1_port: pcie@0 {
|
||||
device_type = "pci";
|
||||
compatible = "pciclass,0604";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2: pcie@ca800000 {
|
||||
device_type = "pci";
|
||||
compatible = "spacemit,k1-pcie";
|
||||
reg = <0x0 0xca800000 0x0 0x00001000>,
|
||||
<0x0 0xcab00000 0x0 0x0001ff24>,
|
||||
<0x0 0xb7000000 0x0 0x00002000>,
|
||||
<0x0 0xc0d20000 0x0 0x00001000>;
|
||||
reg-names = "dbi",
|
||||
"atu",
|
||||
"config",
|
||||
"link";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>,
|
||||
<0x42000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000>,
|
||||
<0x02000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x07000000>;
|
||||
interrupts = <143>;
|
||||
interrupt-names = "msi";
|
||||
clocks = <&syscon_apmu CLK_PCIE2_DBI>,
|
||||
<&syscon_apmu CLK_PCIE2_MASTER>,
|
||||
<&syscon_apmu CLK_PCIE2_SLAVE>;
|
||||
clock-names = "dbi",
|
||||
"mstr",
|
||||
"slv";
|
||||
resets = <&syscon_apmu RESET_PCIE2_DBI>,
|
||||
<&syscon_apmu RESET_PCIE2_MASTER>,
|
||||
<&syscon_apmu RESET_PCIE2_SLAVE>;
|
||||
reset-names = "dbi",
|
||||
"mstr",
|
||||
"slv";
|
||||
spacemit,apmu = <&syscon_apmu 0x3dc>;
|
||||
status = "disabled";
|
||||
|
||||
pcie2_port: pcie@0 {
|
||||
device_type = "pci";
|
||||
compatible = "pciclass,0604";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
storage-bus {
|
||||
|
|
@ -978,12 +1171,39 @@ storage-bus {
|
|||
#size-cells = <2>;
|
||||
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
|
||||
|
||||
usb_dwc3: usb@c0a00000 {
|
||||
compatible = "spacemit,k1-dwc3";
|
||||
reg = <0x0 0xc0a00000 0x0 0x10000>;
|
||||
clocks = <&syscon_apmu CLK_USB30>;
|
||||
clock-names = "usbdrd30";
|
||||
interrupts = <125>;
|
||||
phys = <&usbphy2>, <&combo_phy PHY_TYPE_USB3>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
phy_type = "utmi";
|
||||
resets = <&syscon_apmu RESET_USB30_AHB>,
|
||||
<&syscon_apmu RESET_USB30_VCC>,
|
||||
<&syscon_apmu RESET_USB30_PHY>;
|
||||
reset-names = "ahb", "vcc", "phy";
|
||||
reset-delay = <2>;
|
||||
snps,hsphy_interface = "utmi";
|
||||
snps,dis_enblslpm_quirk;
|
||||
snps,dis-u2-freeclk-exists-quirk;
|
||||
snps,dis-del-phy-power-chg-quirk;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_u3_susphy_quirk;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
emmc: mmc@d4281000 {
|
||||
compatible = "spacemit,k1-sdhci";
|
||||
reg = <0x0 0xd4281000 0x0 0x200>;
|
||||
clocks = <&syscon_apmu CLK_SDH_AXI>,
|
||||
<&syscon_apmu CLK_SDH2>;
|
||||
clock-names = "core", "io";
|
||||
resets = <&syscon_apmu RESET_SDH_AXI>,
|
||||
<&syscon_apmu RESET_SDH2>;
|
||||
reset-names = "axi", "sdh";
|
||||
interrupts = <101>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
29
arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
Normal file
29
arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd
|
||||
* Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
|
||||
*/
|
||||
|
||||
#include "k3.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SpacemiT K3 Pico-ITX";
|
||||
compatible = "spacemit,k3-pico-itx", "spacemit,k3";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0";
|
||||
};
|
||||
|
||||
memory@100000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x1 0x00000000 0x4 0x00000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
578
arch/riscv/boot/dts/spacemit/k3.dtsi
Normal file
578
arch/riscv/boot/dts/spacemit/k3.dtsi
Normal file
|
|
@ -0,0 +1,578 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd
|
||||
* Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
model = "SpacemiT K3";
|
||||
compatible = "spacemit,k3";
|
||||
|
||||
cpus: cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
timebase-frequency = <24000000>;
|
||||
|
||||
cpu_0: cpu@0 {
|
||||
compatible = "spacemit,x100", "riscv";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
|
||||
"sha", "shcounterenw", "shgatpa", "shtvala",
|
||||
"shvsatpa", "shvstvala", "shvstvecd", "smaia",
|
||||
"smstateen", "ssaia", "ssccptr", "sscofpmf",
|
||||
"sscounterenw", "ssnpm", "ssstateen", "sstc",
|
||||
"sstvala", "sstvecd", "ssu64xl", "svade",
|
||||
"svinval", "svnapot", "svpbmt", "za64rs",
|
||||
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
|
||||
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
|
||||
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
|
||||
"ziccamoa", "ziccif", "zicclsm", "zicntr",
|
||||
"zicond", "zicsr", "zifencei", "zihintntl",
|
||||
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
|
||||
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
|
||||
"zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
|
||||
"zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-size = <65536>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2_cache0>;
|
||||
mmu-type = "riscv,sv39";
|
||||
|
||||
cpu0_intc: interrupt-controller {
|
||||
compatible = "riscv,cpu-intc";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
cpu_1: cpu@1 {
|
||||
compatible = "spacemit,x100", "riscv";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
|
||||
"sha", "shcounterenw", "shgatpa", "shtvala",
|
||||
"shvsatpa", "shvstvala", "shvstvecd", "smaia",
|
||||
"smstateen", "ssaia", "ssccptr", "sscofpmf",
|
||||
"sscounterenw", "ssnpm", "ssstateen", "sstc",
|
||||
"sstvala", "sstvecd", "ssu64xl", "svade",
|
||||
"svinval", "svnapot", "svpbmt", "za64rs",
|
||||
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
|
||||
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
|
||||
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
|
||||
"ziccamoa", "ziccif", "zicclsm", "zicntr",
|
||||
"zicond", "zicsr", "zifencei", "zihintntl",
|
||||
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
|
||||
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
|
||||
"zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
|
||||
"zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-size = <65536>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2_cache0>;
|
||||
mmu-type = "riscv,sv39";
|
||||
|
||||
cpu1_intc: interrupt-controller {
|
||||
compatible = "riscv,cpu-intc";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
cpu_2: cpu@2 {
|
||||
compatible = "spacemit,x100", "riscv";
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
|
||||
"sha", "shcounterenw", "shgatpa", "shtvala",
|
||||
"shvsatpa", "shvstvala", "shvstvecd", "smaia",
|
||||
"smstateen", "ssaia", "ssccptr", "sscofpmf",
|
||||
"sscounterenw", "ssnpm", "ssstateen", "sstc",
|
||||
"sstvala", "sstvecd", "ssu64xl", "svade",
|
||||
"svinval", "svnapot", "svpbmt", "za64rs",
|
||||
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
|
||||
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
|
||||
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
|
||||
"ziccamoa", "ziccif", "zicclsm", "zicntr",
|
||||
"zicond", "zicsr", "zifencei", "zihintntl",
|
||||
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
|
||||
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
|
||||
"zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
|
||||
"zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-size = <65536>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2_cache0>;
|
||||
mmu-type = "riscv,sv39";
|
||||
|
||||
cpu2_intc: interrupt-controller {
|
||||
compatible = "riscv,cpu-intc";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
cpu_3: cpu@3 {
|
||||
compatible = "spacemit,x100", "riscv";
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
|
||||
"sha", "shcounterenw", "shgatpa", "shtvala",
|
||||
"shvsatpa", "shvstvala", "shvstvecd", "smaia",
|
||||
"smstateen", "ssaia", "ssccptr", "sscofpmf",
|
||||
"sscounterenw", "ssnpm", "ssstateen", "sstc",
|
||||
"sstvala", "sstvecd", "ssu64xl", "svade",
|
||||
"svinval", "svnapot", "svpbmt", "za64rs",
|
||||
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
|
||||
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
|
||||
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
|
||||
"ziccamoa", "ziccif", "zicclsm", "zicntr",
|
||||
"zicond", "zicsr", "zifencei", "zihintntl",
|
||||
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
|
||||
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
|
||||
"zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
|
||||
"zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-size = <65536>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2_cache0>;
|
||||
mmu-type = "riscv,sv39";
|
||||
|
||||
cpu3_intc: interrupt-controller {
|
||||
compatible = "riscv,cpu-intc";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
cpu_4: cpu@4 {
|
||||
compatible = "spacemit,x100", "riscv";
|
||||
device_type = "cpu";
|
||||
reg = <4>;
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
|
||||
"sha", "shcounterenw", "shgatpa", "shtvala",
|
||||
"shvsatpa", "shvstvala", "shvstvecd", "smaia",
|
||||
"smstateen", "ssaia", "ssccptr", "sscofpmf",
|
||||
"sscounterenw", "ssnpm", "ssstateen", "sstc",
|
||||
"sstvala", "sstvecd", "ssu64xl", "svade",
|
||||
"svinval", "svnapot", "svpbmt", "za64rs",
|
||||
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
|
||||
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
|
||||
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
|
||||
"ziccamoa", "ziccif", "zicclsm", "zicntr",
|
||||
"zicond", "zicsr", "zifencei", "zihintntl",
|
||||
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
|
||||
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
|
||||
"zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
|
||||
"zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-size = <65536>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2_cache1>;
|
||||
mmu-type = "riscv,sv39";
|
||||
|
||||
cpu4_intc: interrupt-controller {
|
||||
compatible = "riscv,cpu-intc";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
cpu_5: cpu@5 {
|
||||
compatible = "spacemit,x100", "riscv";
|
||||
device_type = "cpu";
|
||||
reg = <5>;
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
|
||||
"sha", "shcounterenw", "shgatpa", "shtvala",
|
||||
"shvsatpa", "shvstvala", "shvstvecd", "smaia",
|
||||
"smstateen", "ssaia", "ssccptr", "sscofpmf",
|
||||
"sscounterenw", "ssnpm", "ssstateen", "sstc",
|
||||
"sstvala", "sstvecd", "ssu64xl", "svade",
|
||||
"svinval", "svnapot", "svpbmt", "za64rs",
|
||||
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
|
||||
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
|
||||
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
|
||||
"ziccamoa", "ziccif", "zicclsm", "zicntr",
|
||||
"zicond", "zicsr", "zifencei", "zihintntl",
|
||||
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
|
||||
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
|
||||
"zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
|
||||
"zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-size = <65536>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2_cache1>;
|
||||
mmu-type = "riscv,sv39";
|
||||
|
||||
cpu5_intc: interrupt-controller {
|
||||
compatible = "riscv,cpu-intc";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
cpu_6: cpu@6 {
|
||||
compatible = "spacemit,x100", "riscv";
|
||||
device_type = "cpu";
|
||||
reg = <6>;
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
|
||||
"sha", "shcounterenw", "shgatpa", "shtvala",
|
||||
"shvsatpa", "shvstvala", "shvstvecd", "smaia",
|
||||
"smstateen", "ssaia", "ssccptr", "sscofpmf",
|
||||
"sscounterenw", "ssnpm", "ssstateen", "sstc",
|
||||
"sstvala", "sstvecd", "ssu64xl", "svade",
|
||||
"svinval", "svnapot", "svpbmt", "za64rs",
|
||||
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
|
||||
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
|
||||
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
|
||||
"ziccamoa", "ziccif", "zicclsm", "zicntr",
|
||||
"zicond", "zicsr", "zifencei", "zihintntl",
|
||||
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
|
||||
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
|
||||
"zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
|
||||
"zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-size = <65536>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2_cache1>;
|
||||
mmu-type = "riscv,sv39";
|
||||
|
||||
cpu6_intc: interrupt-controller {
|
||||
compatible = "riscv,cpu-intc";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
cpu_7: cpu@7 {
|
||||
compatible = "spacemit,x100", "riscv";
|
||||
device_type = "cpu";
|
||||
reg = <7>;
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
|
||||
"sha", "shcounterenw", "shgatpa", "shtvala",
|
||||
"shvsatpa", "shvstvala", "shvstvecd", "smaia",
|
||||
"smstateen", "ssaia", "ssccptr", "sscofpmf",
|
||||
"sscounterenw", "ssnpm", "ssstateen", "sstc",
|
||||
"sstvala", "sstvecd", "ssu64xl", "svade",
|
||||
"svinval", "svnapot", "svpbmt", "za64rs",
|
||||
"zawrs", "zba", "zbb", "zbc", "zbs", "zca",
|
||||
"zcb", "zcd", "zcmop", "zfa", "zfbfmin",
|
||||
"zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
|
||||
"ziccamoa", "ziccif", "zicclsm", "zicntr",
|
||||
"zicond", "zicsr", "zifencei", "zihintntl",
|
||||
"zihintpause", "zihpm", "zimop", "zkt", "zvbb",
|
||||
"zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
|
||||
"zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
|
||||
"zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-size = <65536>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&l2_cache1>;
|
||||
mmu-type = "riscv,sv39";
|
||||
|
||||
cpu7_intc: interrupt-controller {
|
||||
compatible = "riscv,cpu-intc";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
l2_cache0: cache-controller-0 {
|
||||
compatible = "cache";
|
||||
cache-block-size = <64>;
|
||||
cache-level = <2>;
|
||||
cache-size = <4194304>;
|
||||
cache-sets = <4096>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
l2_cache1: cache-controller-1 {
|
||||
compatible = "cache";
|
||||
cache-block-size = <64>;
|
||||
cache-level = <2>;
|
||||
cache-size = <4194304>;
|
||||
cache-sets = <4096>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu_1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu_2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu_3>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&cpu_4>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu_5>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu_6>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu_7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&saplic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
dma-noncoherent;
|
||||
ranges;
|
||||
|
||||
uart0: serial@d4017000 {
|
||||
compatible = "spacemit,k3-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd4017000 0x0 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <14700000>;
|
||||
interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@d4017100 {
|
||||
compatible = "spacemit,k3-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd4017100 0x0 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <14700000>;
|
||||
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@d4017200 {
|
||||
compatible = "spacemit,k3-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd4017200 0x0 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <14700000>;
|
||||
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@d4017300 {
|
||||
compatible = "spacemit,k3-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd4017300 0x0 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <14700000>;
|
||||
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@d4017400 {
|
||||
compatible = "spacemit,k3-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd4017400 0x0 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <14700000>;
|
||||
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart6: serial@d4017500 {
|
||||
compatible = "spacemit,k3-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd4017500 0x0 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <14700000>;
|
||||
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart7: serial@d4017600 {
|
||||
compatible = "spacemit,k3-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd4017600 0x0 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <14700000>;
|
||||
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart8: serial@d4017700 {
|
||||
compatible = "spacemit,k3-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd4017700 0x0 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <14700000>;
|
||||
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart9: serial@d4017800 {
|
||||
compatible = "spacemit,k3-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd4017800 0x0 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <14700000>;
|
||||
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart10: serial@d401f000 {
|
||||
compatible = "spacemit,k3-uart", "intel,xscale-uart";
|
||||
reg = <0x0 0xd401f000 0x0 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <14700000>;
|
||||
interrupts = <281 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
simsic: interrupt-controller@e0400000 {
|
||||
compatible = "spacemit,k3-imsics", "riscv,imsics";
|
||||
reg = <0x0 0xe0400000 0x0 0x200000>;
|
||||
#interrupt-cells = <0>;
|
||||
#msi-cells = <0>;
|
||||
interrupt-controller;
|
||||
interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>,
|
||||
<&cpu2_intc 9>, <&cpu3_intc 9>,
|
||||
<&cpu4_intc 9>, <&cpu5_intc 9>,
|
||||
<&cpu6_intc 9>, <&cpu7_intc 9>;
|
||||
msi-controller;
|
||||
riscv,guest-index-bits = <6>;
|
||||
riscv,hart-index-bits = <4>;
|
||||
riscv,num-guest-ids = <511>;
|
||||
riscv,num-ids = <511>;
|
||||
};
|
||||
|
||||
saplic: interrupt-controller@e0804000 {
|
||||
compatible = "spacemit,k3-aplic", "riscv,aplic";
|
||||
reg = <0x0 0xe0804000 0x0 0x4000>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
msi-parent = <&simsic>;
|
||||
riscv,num-sources = <512>;
|
||||
};
|
||||
|
||||
clint: timer@e081c000 {
|
||||
compatible = "spacemit,k3-clint", "sifive,clint0";
|
||||
reg = <0x0 0xe081c000 0x0 0x4000>;
|
||||
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
|
||||
<&cpu1_intc 3>, <&cpu1_intc 7>,
|
||||
<&cpu2_intc 3>, <&cpu2_intc 7>,
|
||||
<&cpu3_intc 3>, <&cpu3_intc 7>,
|
||||
<&cpu4_intc 3>, <&cpu4_intc 7>,
|
||||
<&cpu5_intc 3>, <&cpu5_intc 7>,
|
||||
<&cpu6_intc 3>, <&cpu6_intc 7>,
|
||||
<&cpu7_intc 3>, <&cpu7_intc 7>;
|
||||
};
|
||||
|
||||
mimsic: interrupt-controller@f1000000 {
|
||||
compatible = "spacemit,k3-imsics", "riscv,imsics";
|
||||
reg = <0x0 0xf1000000 0x0 0x10000>;
|
||||
#interrupt-cells = <0>;
|
||||
#msi-cells = <0>;
|
||||
interrupt-controller;
|
||||
interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>,
|
||||
<&cpu2_intc 11>, <&cpu3_intc 11>,
|
||||
<&cpu4_intc 11>, <&cpu5_intc 11>,
|
||||
<&cpu6_intc 11>, <&cpu7_intc 11>;
|
||||
msi-controller;
|
||||
riscv,guest-index-bits = <6>;
|
||||
riscv,hart-index-bits = <4>;
|
||||
riscv,num-guest-ids = <511>;
|
||||
riscv,num-ids = <511>;
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
maplic: interrupt-controller@f1800000 {
|
||||
compatible = "spacemit,k3-aplic", "riscv,aplic";
|
||||
reg = <0x0 0xf1800000 0x0 0x4000>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
msi-parent = <&mimsic>;
|
||||
riscv,children = <&saplic>;
|
||||
riscv,delegation = <&saplic 1 512>;
|
||||
riscv,num-sources = <512>;
|
||||
status = "reserved";
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user