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Samsung DTS ARM64 changes for v6.20, part two
Add DPU clock management unit nodes to Google GS101. -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmlx4t4QHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD1556EACSVx9fbk3LlULtLAtOk355gsQCLteY6cTz 9sCOCErGe7szk0jtV3bk4vrKg/ONwM6g5hUOfrZlMcHuQZdjd6PHNKdQLX5+RKWc 2mA1AKy2p1LfrVUyka7fiaEU4xYEHdb8IUamM7aHjBhIp+5+t6YMvrCuOcd1/QYK sOwCP8sT+mVQJnpu+k26XoBMulZfB1HGWL43fk80y94GhQX6nLMdHrSdlO+SShaa jTBD3YHfllmlUQdmAVeSJiMy02goivnjoanPFG32j+4Cn+KD/8w+yz/aMtrBynvS Pwdo2jX6F8J3GsaoqFkutps7zGEPEFDeoaFQgcoD/mWng3iHfluHIKOoFLGTe59W AkSngskkHhUPQGUSYpRap5N3CYmBjtBliks5FlSChqaz1baP+YXmIFz2uquEm0R+ yNo8Jpx4hSH7+YzRNPshLRIkkkhJKPDCMj8umPC+Of+aA6KTeijHV+uhWygsLjqG LmpWWwLMIWzX0yTtW7aKZ7oxzekB+sUVb5A87QtnM18zbINDX1q+zxdKF4iMvfqn DndeJOpfDu8b13aZ8MEPUuXmGk6aYQwP4dhfv0dc76yToms2VKNLywic+qQsnB95 td83D2KXY2WYmU7jTJtw+4ivkhD4KgEAg/5n1fIhv0IT7VrZmumBZdfhr5lDLLYV DLoyuh6qzQ== =LRtY -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml6SUAACgkQmmx57+YA GNkLgBAAqj9l8kZW222GMkdwO0GxoPRPG+IQdQMLD/Z7y7d2NLajpzMhxQnMkkN/ HdNFRlEercKQ3OWuilnHbw7hrx61LSbmiVOWiDZRrmI9Wxh7YBSjRFx1WKzk/EZa P9LjLd9A2NXRxcCnA/QT54BKJHtgHnaI7uzYTHwFEUcGu9hHgh9dm6LXuQCweGeL 0RirrXJ1cylnLgIM09NwwTcFRobpElWbMGMy45+hw6HSlpWNDCaob0KvfkE+J84c Pj8OHb9+NILaZhuMEEtnWzymxu9Al8s9TPIFUsv/rx4r5S7kS9klZJqISrwWRc5G e+7rHo8QgTM6j4S4tal99XeNAEm/I+l/2D2GoB8xxB2vpiyhdXbRkqzGxNBw9Ras jRtC+ykQGG5i9d1DLzA6SGpglrYU0MYZKvTDDSOLGmHtDpP0ttgnhNpaWA5jHD6t zLmnHbwpFrTLIF43BHeSlMf7s3wtY1jlCQqtKj/egxyAgooBj12Krc0IDug3cebV nJv9eG9dkrO1KQn4Eeds85gsGaZs2Is0e03C2nyU9isoNqKyFLWeSPgZHGii1FSC S6msWCPfo9Yhiypq5/Dpnd29FN7dekpOp1qVSHuPyhNDbPHcIB8ROPO+Wv1Zsuur hlljRvYKQzDj7NzysR9xyRnvkIOI3FJRxy+m0BdtN0zOe7LxkwM= =2Af+ -----END PGP SIGNATURE----- Merge tag 'samsung-dt64-6.20-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt Samsung DTS ARM64 changes for v6.20, part two Add DPU clock management unit nodes to Google GS101. * tag 'samsung-dt64-6.20-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos: gs101: add cmu_dpu and sysreg_dpu dt nodes dt-bindings: clock: google,gs101-clock: Add DPU clock management unit dt-bindings: clock: google,gs101-clock: fix alphanumeric ordering Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
c8f7de01d9
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@ -29,9 +29,10 @@ properties:
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enum:
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- google,gs101-cmu-top
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- google,gs101-cmu-apm
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- google,gs101-cmu-misc
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- google,gs101-cmu-dpu
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- google,gs101-cmu-hsi0
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- google,gs101-cmu-hsi2
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- google,gs101-cmu-misc
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- google,gs101-cmu-peric0
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- google,gs101-cmu-peric1
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@ -77,6 +78,24 @@ allOf:
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items:
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- const: oscclk
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- if:
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properties:
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compatible:
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contains:
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const: google,gs101-cmu-dpu
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (24.576 MHz)
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- description: DPU bus clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: bus
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- if:
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properties:
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compatible:
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@ -1815,6 +1815,23 @@ pinctrl_gsacore: pinctrl@17a80000 {
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status = "disabled";
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};
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cmu_dpu: clock-controller@1c000000 {
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compatible = "google,gs101-cmu-dpu";
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reg = <0x1c000000 0x10000>;
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#clock-cells = <1>;
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clocks = <&ext_24_5m>,
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<&cmu_top CLK_DOUT_CMU_DPU_BUS>;
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clock-names = "oscclk", "bus";
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samsung,sysreg = <&sysreg_dpu>;
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};
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sysreg_dpu: syscon@1c020000 {
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compatible = "google,gs101-dpu-sysreg", "syscon";
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reg = <0x1c020000 0x10000>;
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clocks = <&cmu_dpu CLK_GOUT_DPU_SYSREG_DPU_PCLK>;
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};
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cmu_top: clock-controller@1e080000 {
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compatible = "google,gs101-cmu-top";
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reg = <0x1e080000 0x10000>;
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@ -313,6 +313,42 @@
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#define CLK_APM_PLL_DIV4_APM 70
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#define CLK_APM_PLL_DIV16_APM 71
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/* CMU_DPU */
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#define CLK_MOUT_DPU_BUS_USER 1
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#define CLK_DOUT_DPU_BUSP 2
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#define CLK_GOUT_DPU_PCLK 3
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#define CLK_GOUT_DPU_CLK_DPU_OSCCLK_CLK 4
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#define CLK_GOUT_DPU_AD_APB_DPU_DMA_PCLKM 5
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#define CLK_GOUT_DPU_DPUF_ACLK_DMA 6
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#define CLK_GOUT_DPU_DPUF_ACLK_DPP 7
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#define CLK_GOUT_DPU_D_TZPC_DPU_PCLK 8
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#define CLK_GOUT_DPU_GPC_DPU_PCLK 9
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#define CLK_GOUT_DPU_LHM_AXI_P_DPU_I_CLK 10
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#define CLK_GOUT_DPU_LHS_AXI_D0_DPU_I_CLK 11
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#define CLK_GOUT_DPU_LHS_AXI_D1_DPU_I_CLK 12
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#define CLK_GOUT_DPU_LHS_AXI_D2_DPU_I_CLK 13
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#define CLK_GOUT_DPU_PPMU_DPUD0_ACLK 14
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#define CLK_GOUT_DPU_PPMU_DPUD0_PCLK 15
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#define CLK_GOUT_DPU_PPMU_DPUD1_ACLK 16
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#define CLK_GOUT_DPU_PPMU_DPUD1_PCLK 17
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#define CLK_GOUT_DPU_PPMU_DPUD2_ACLK 18
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#define CLK_GOUT_DPU_PPMU_DPUD2_PCLK 19
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#define CLK_GOUT_DPU_CLK_DPU_BUSD_CLK 20
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#define CLK_GOUT_DPU_CLK_DPU_BUSP_CLK 21
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#define CLK_GOUT_DPU_SSMT_DPU0_ACLK 22
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#define CLK_GOUT_DPU_SSMT_DPU0_PCLK 23
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#define CLK_GOUT_DPU_SSMT_DPU1_ACLK 24
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#define CLK_GOUT_DPU_SSMT_DPU1_PCLK 25
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#define CLK_GOUT_DPU_SSMT_DPU2_ACLK 26
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#define CLK_GOUT_DPU_SSMT_DPU2_PCLK 27
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#define CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S1 28
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#define CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S2 29
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#define CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S1 30
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#define CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S2 31
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#define CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S1 32
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#define CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S2 33
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#define CLK_GOUT_DPU_SYSREG_DPU_PCLK 34
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/* CMU_HSI0 */
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#define CLK_FOUT_USB_PLL 1
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#define CLK_MOUT_PLL_USB 2
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