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arm64: dts: exynos: gs101: add cmu_dpu and sysreg_dpu dt nodes

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Enable the cmu_dpu clock management unit. It feeds some of the display
IPs. Additionally add the sysreg_dpu node which contains the
BUSCOMPONENT_DRCG_EN and MEMCLK registers required by cmu_dpu to enable
dynamic root clock gating of bus components.

Reviewed-by: André Draszik <andre.draszik@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://patch.msgid.link/20260113-dpu-clocks-v3-5-cb85424f2c72@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Peter Griffin 2026-01-13 10:59:02 +00:00 committed by Krzysztof Kozlowski
parent 791d34232c
commit 024d8f4aa3
1 changed files with 17 additions and 0 deletions
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17
arch/arm64/boot/dts/exynos/google/gs101.dtsi
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@ -1815,6 +1815,23 @@ pinctrl_gsacore: pinctrl@17a80000 {
status = "disabled";
};
cmu_dpu: clock-controller@1c000000 {
compatible = "google,gs101-cmu-dpu";
reg = <0x1c000000 0x10000>;
#clock-cells = <1>;
clocks = <&ext_24_5m>,
<&cmu_top CLK_DOUT_CMU_DPU_BUS>;
clock-names = "oscclk", "bus";
samsung,sysreg = <&sysreg_dpu>;
};
sysreg_dpu: syscon@1c020000 {
compatible = "google,gs101-dpu-sysreg", "syscon";
reg = <0x1c020000 0x10000>;
clocks = <&cmu_dpu CLK_GOUT_DPU_SYSREG_DPU_PCLK>;
};
cmu_top: clock-controller@1e080000 {
compatible = "google,gs101-cmu-top";
reg = <0x1e080000 0x10000>;